From patchwork Mon Apr 11 10:14:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12808916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 862E6C433FE for ; Mon, 11 Apr 2022 10:14:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345190AbiDKKQj (ORCPT ); Mon, 11 Apr 2022 06:16:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345183AbiDKKQg (ORCPT ); Mon, 11 Apr 2022 06:16:36 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA8C313F34; Mon, 11 Apr 2022 03:14:21 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id u3so22273238wrg.3; Mon, 11 Apr 2022 03:14:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jo7tWOSsCgtTcP6fE9H4HS3FFxnoGMJ2maOVgOmkHE0=; b=iffnUFjHZ2UOEaWor02KSBDnkhR+50d4cHTv5sJrZLKIftrT3gOx/8t9yy9ghrllcH hrTz6lStIHzsI9qPxNEGxAYapYmFm4krK7g6O+u+k4XAz5/QrOwKoXKFzpPezbp2BLcg D6D8sJGRCUzG6AfJKIxPoUl/1e+C6OOmidpaiXaggZFqJiMAnxfV6vCM6P2Np00+aq0G kmeomBJewPcQh8aEarE2Lbv50fdEnypEyDECd5jBWSmYNLIKdFhpRUIJA3oMT89L2o2U Uz2Fhh2zlbPB5fSlgPqasq5IANy388K8CRTl7CuaTGSi/6J54vUKltqxqO7Dq47xM57a TEBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jo7tWOSsCgtTcP6fE9H4HS3FFxnoGMJ2maOVgOmkHE0=; b=XbfZrKG6xWwZ/aJgfzp5L6/WPlGx+ZQAlzrVhm5z3qDCGHptdF0i+t5qGqycS/VkGg Rq/TFRqUOI4ganLXIcR8rVNB9Ybxc5oA9OqZboOHmwt0KU1xeSjOk/Jfg6qDHGSN+in6 md+hl/46/Wt1GlX7Z0q2fW9luRugD6hnKxHhFRvslsASEsYutcG0J3s5tSY0gmwIlCMP mJ1x9/V+y/x7CN6ZPkmRPHjpTigCqgrNrZxc0l4Fw5rnFSv75dQ8dtHY+ulMWmoWhfn1 QD9x3JlcWVnM3nv3aRu/mKt2+hmdJ1Vrtr0oom/01WoCff7gt8gc45Dg590SySPU5fWm +AdA== X-Gm-Message-State: AOAM531vAK2Jo1VIquItKi9EieW+/NyhNAAFnEUQuuVn++RW58p/jtfN CPKMCanBLoWtYGk98Y24ACk= X-Google-Smtp-Source: ABdhPJysaIoFhiHSoTtVAJlzluzsNoNwqWc02I9Ga2xJWOEVrVRS1MIE4uRlj8kxMK6F/cmvbMY4sg== X-Received: by 2002:adf:ff8d:0:b0:207:a0e2:4487 with SMTP id j13-20020adfff8d000000b00207a0e24487mr7597532wrr.570.1649672060359; Mon, 11 Apr 2022 03:14:20 -0700 (PDT) Received: from localhost (92.40.202.18.threembb.co.uk. [92.40.202.18]) by smtp.gmail.com with ESMTPSA id g16-20020a05600c4ed000b0038ceb0b21b4sm20526369wmq.24.2022.04.11.03.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 03:14:19 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, paulburton@kernel.org, tsbogend@alpha.franken.de, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [RESEND PATCH 1/3] clk: ingenic: Allow specifying common clock flags Date: Mon, 11 Apr 2022 11:14:39 +0100 Message-Id: <20220411101441.17020-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> References: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks. For example, the CLK_IS_CRITICAL flag is needed for some clocks (such as CPU or memory) to stop them being automatically disabled. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 2 +- drivers/clk/ingenic/cgu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index af31633a8862..861c50d6cb24 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -660,7 +660,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) ingenic_clk->idx = idx; clk_init.name = clk_info->name; - clk_init.flags = 0; + clk_init.flags = clk_info->flags; clk_init.parent_names = parent_names; caps = clk_info->type; diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index bfc2b9c38a41..147b7df0d657 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -136,6 +136,7 @@ struct ingenic_cgu_custom_info { * struct ingenic_cgu_clk_info - information about a clock * @name: name of the clock * @type: a bitmask formed from CGU_CLK_* values + * @flags: common clock flags to set on this clock * @parents: an array of the indices of potential parents of this clock * within the clock_info array of the CGU, or -1 in entries * which correspond to no valid parent @@ -161,6 +162,8 @@ struct ingenic_cgu_clk_info { CGU_CLK_CUSTOM = BIT(7), } type; + unsigned long flags; + int parents[4]; union { From patchwork Mon Apr 11 10:14:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12808919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A10E5C433EF for ; Mon, 11 Apr 2022 10:14:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345194AbiDKKQq (ORCPT ); Mon, 11 Apr 2022 06:16:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345192AbiDKKQl (ORCPT ); Mon, 11 Apr 2022 06:16:41 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B13D15A3E; Mon, 11 Apr 2022 03:14:23 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id i20so9135244wrb.13; Mon, 11 Apr 2022 03:14:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tyBB/Xj3enrJji4q8ldrhQ7YvWPei4kEZRP/O9pYwzk=; b=mbr9aqRZ5bzJ9j2PgE8Xj+D9T/7K4bQ/jR9gAnh6Xs6AuyThMdOGBZHFf4sFV87qX8 g7GXlztvfjO+OQeBoTJ424CgutocIFWHX/HPq67JS3mQ0f4PORvJ7ILT4z9zuzVPzVkh 2y8Unupg0jnRWB6jPnTZZ//bT7hVElz/FPjB3ziwJhadRO328FLZ3wVvQhFsYPHyOvaT bp3drfquwnBgLhIk14soPzWaKxpTwWI5DsinRqeuJLVrNHN7cRoYuFJcN5t6sMg1/Mmb FQ7GU5NSI5rMHx4A3HVKE21bJwHqqDZ+FdwzEdtEVBzKTMbiCnQmV4i2722H3qjPqC1K fk5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tyBB/Xj3enrJji4q8ldrhQ7YvWPei4kEZRP/O9pYwzk=; b=mq7XsVIkIzWR4eBwCOFPWb6yJMPcHZKVkhCcINNdKJ2PuaWr/7mGrJJD0+WuEDXdd7 +dK9ICsJMpyO6XoH9TqaO1vUitUHMfjV2us7E8UYAF1/d44p59RShvxiV1E6+n1V8m5L YvZY0ELy7eUdrQ2Rb69voG+Z+JWfDdAU2bJmrahIhVzgwiLHGyQjntj0wyPvFhaAVfVK 2Ae+SKyQpdL+9noPwIC7/Er3UoyYV2nML8MQJoQpyHXDSlALCnLU2RGY52YLR73mSmZJ 7L8Z76DqXs0jvR4/4lH2/uPct/bT2ePo+ULAILEJhCTIAhZptqOg/o/9tsifLJZ/fN1Z OEuw== X-Gm-Message-State: AOAM533hPl4cRKbuxP9K7LHMClTWE97N2ah2Igoy15yd0YlCbPtb/Zpo g+xlvbFmMyO6rXDJct/s17U= X-Google-Smtp-Source: ABdhPJx+Ei6S/56jT1hFmrSWUx9/eUny5uuJpcLdHYWtZI1+mBb25ide2DZRM67n7urcJAHmZLUgXA== X-Received: by 2002:adf:d1c6:0:b0:205:dbfb:7892 with SMTP id b6-20020adfd1c6000000b00205dbfb7892mr24423661wrd.193.1649672061630; Mon, 11 Apr 2022 03:14:21 -0700 (PDT) Received: from localhost (92.40.202.18.threembb.co.uk. [92.40.202.18]) by smtp.gmail.com with ESMTPSA id g16-20020a05600c4ed000b0038ceb0b21b4sm20526369wmq.24.2022.04.11.03.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 03:14:21 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, paulburton@kernel.org, tsbogend@alpha.franken.de, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [RESEND PATCH 2/3] clk: ingenic: Mark critical clocks in Ingenic SoCs Date: Mon, 11 Apr 2022 11:14:40 +0100 Message-Id: <20220411101441.17020-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> References: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Consider the CPU, L2 cache, and memory as critical to ensure they are not disabled. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/jz4725b-cgu.c | 2 ++ drivers/clk/ingenic/jz4740-cgu.c | 2 ++ drivers/clk/ingenic/jz4760-cgu.c | 2 ++ drivers/clk/ingenic/jz4770-cgu.c | 1 + drivers/clk/ingenic/jz4780-cgu.c | 3 +++ drivers/clk/ingenic/x1000-cgu.c | 3 +++ drivers/clk/ingenic/x1830-cgu.c | 3 +++ 7 files changed, 16 insertions(+) diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 15d61793f53b..c209a170be5d 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -87,6 +87,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -114,6 +115,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 43ffb62c42bb..2b6f7a9fcea8 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -102,6 +102,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -129,6 +130,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c index 8fdd383560fb..7920df2cee1a 100644 --- a/drivers/clk/ingenic/jz4760-cgu.c +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -143,6 +143,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -175,6 +176,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { }, [JZ4760_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 7ef91257630e..02b266c2a537 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -149,6 +149,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index e357c228e0f1..014674486038 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -341,12 +341,14 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_CPU] = { "cpu", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, }, [JZ4780_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, }, @@ -380,6 +382,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 3c4d5a77ccbd..1bd421cc2ab3 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -251,6 +251,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, + .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 30 }, @@ -258,6 +259,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -290,6 +292,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .flags = CLK_IS_CRITICAL, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index e01ec2dc7a1a..b08e318aa095 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -225,6 +225,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, + .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR1, 15 }, @@ -232,6 +233,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -264,6 +266,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .flags = CLK_IS_CRITICAL, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, From patchwork Mon Apr 11 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[92.40.202.18]) by smtp.gmail.com with ESMTPSA id g16-20020a05600c4ed000b0038ceb0b21b4sm20526369wmq.24.2022.04.11.03.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 03:14:22 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, paulburton@kernel.org, tsbogend@alpha.franken.de, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [RESEND PATCH 3/3] mips: ingenic: Do not manually reference the CPU clock Date: Mon, 11 Apr 2022 11:14:41 +0100 Message-Id: <20220411101441.17020-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> References: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It isn't necessary to manually walk the device tree and enable the CPU clock anymore. The CPU and other necessary clocks are now flagged as critical in the clock driver, which accomplishes the same thing in a more declarative fashion. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- arch/mips/generic/board-ingenic.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c index 3f44f14bdb33..c422bbc890ed 100644 --- a/arch/mips/generic/board-ingenic.c +++ b/arch/mips/generic/board-ingenic.c @@ -131,36 +131,10 @@ static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = { static int __init ingenic_pm_init(void) { - struct device_node *cpu_node; - struct clk *cpu0_clk; - int ret; - if (boot_cpu_type() == CPU_XBURST) { if (IS_ENABLED(CONFIG_PM_SLEEP)) suspend_set_ops(&ingenic_pm_ops); _machine_halt = ingenic_halt; - - /* - * Unconditionally enable the clock for the first CPU. - * This makes sure that the PLL that feeds the CPU won't be - * stopped while the kernel is running. - */ - cpu_node = of_get_cpu_node(0, NULL); - if (!cpu_node) { - pr_err("Unable to get CPU node\n"); - } else { - cpu0_clk = of_clk_get(cpu_node, 0); - if (IS_ERR(cpu0_clk)) { - pr_err("Unable to get CPU0 clock\n"); - return PTR_ERR(cpu0_clk); - } - - ret = clk_prepare_enable(cpu0_clk); - if (ret) { - pr_err("Unable to enable CPU0 clock\n"); - return ret; - } - } } return 0;