From patchwork Mon Apr 11 15:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Krummenacher X-Patchwork-Id: 12809314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31F9AC433F5 for ; Mon, 11 Apr 2022 15:22:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id E8084C385AE; Mon, 11 Apr 2022 15:22:52 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 1D2AFC385A9; Mon, 11 Apr 2022 15:22:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 1D2AFC385A9 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wm1-f50.google.com with SMTP id n126-20020a1c2784000000b0038e8af3e788so8736418wmn.1; Mon, 11 Apr 2022 08:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dHT+2Pz3E8Ryq2hYcOXh5PKgBGdNhWwwwHyntc5u2ik=; b=DCN5hYPL3TOIgfntIt6LQldg0+mkVhN0+mCa0V4Fhv+OcBoOEMYfBtG0YwnZjfoATA wWRLHFHCTjfDBr0OnDfZ2HPXG4i+nIDYnez6smujxBAV7dlV9idjXDOhD968gTJT+3iT XvGhLDzE7ORk6MQH+jZHJ/6hC24m5IlOkQv31JfIMg4pvHL8DrIurgBhkVg2Uw42uHSy TdBIkFcn801Sy8s8rJ5qkpTg7yh0WimGR64xku1qRwNLRkk1KmJSO5v6OxBp34jB5BJL hzrXYc8fOkoKkMc/RXLSBYBMTIeSuo4SzofByFCZxFs83TkmFe6no1ejsvEo4lVxDzEk 0FGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dHT+2Pz3E8Ryq2hYcOXh5PKgBGdNhWwwwHyntc5u2ik=; b=UkZlbPDD+ctA63f5n2nu1HI+e3jDP6ZqDibc0EoobptQeWvnVZftw3vja+WDLU+rwq ZJknz6YbZ7A+s6Jm1Qt1cqMfsicxUTBAL/59cbcmAvZGZiCcpsHpuG1UryMh/Qe2Mwsk OcgSYTjy9cFsP2BH3u515YRpel6kSfkRsC4c1cWVUlUSx1JD+RxkyDJL3i/+E50m4LH2 kVNt0yT4677DgrA0ykIojvlJuGtb6Ty4LVNl00st+2sqY6GTzZWTY6tAoXJdc8Vblv/U VJIPD4OMZo1ZX3blNRLXKEad3rHyrE4asqRaYeO0/iDDyT5NAnNTR9X7IYK1rwc5vLOd iCxA== X-Gm-Message-State: AOAM530bQzlTsukfYf1qqAzakm/5NQKAb8hlcWLlma6gFtwGdrWxs6Wu cqJ8Jff7ZxOk+ct2nLVKk1E= X-Google-Smtp-Source: ABdhPJy3nFu/hwIUXPeYBaVcqnuDaTm9nXde1AMXsLOvZJqJUi3Omd9v8Hxwiw16sg/xo8I6cXM1Dw== X-Received: by 2002:a05:600c:1f0b:b0:38c:b121:c65f with SMTP id bd11-20020a05600c1f0b00b0038cb121c65fmr28833299wmb.124.1649690570416; Mon, 11 Apr 2022 08:22:50 -0700 (PDT) Received: from linuxdev2.toradex.int (31-10-206-124.static.upc.ch. [31.10.206.124]) by smtp.gmail.com with ESMTPSA id a9-20020a7bc1c9000000b0038eb67e966esm5209374wmj.29.2022.04.11.08.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:22:50 -0700 (PDT) From: Max Krummenacher To: max.krummenacher@toradex.com List-Id: Cc: Arnd Bergmann , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Olof Johansson , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v2 03/14] ARM: dts: imx6dl-colibri: Drop dedicated v1.1 device tree Date: Mon, 11 Apr 2022 17:22:23 +0200 Message-Id: <20220411152234.12678-4-max.oss.09@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220411152234.12678-1-max.oss.09@gmail.com> References: <20220411152234.12678-1-max.oss.09@gmail.com> MIME-Version: 1.0 From: Max Krummenacher Drop Colibri V1.1 device tree, this is just a duplicate of Colibri V1.0 with the possibility to use SD cards in UHS mode if the carrier board does not have 3.3V pull up resistor. The dedicated device tree kept the feature switched of by setting the no-1-8-v property and thus does not offer anything different than what the regular device tree does. Thus drop the dedicated device tree and merge the preparation to allow enabling the feature should a carrier without pull ups be used into the regular device tree. Signed-off-by: Max Krummenacher --- (no changes since v1) arch/arm/boot/dts/Makefile | 1 - .../boot/dts/imx6dl-colibri-v1_1-eval-v3.dts | 31 ------------- .../boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi | 44 ------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 29 +++++++++++- 4 files changed, 27 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts delete mode 100644 arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 252353fb4e3b..ae3cac8e653b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,7 +459,6 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-v1_1-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts deleted file mode 100644 index 223275f028f1..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "imx6dl-colibri-eval-v3.dts" -#include "imx6qdl-colibri-v1_1-uhs.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", - "toradex,colibri_imx6dl-v1_1", - "toradex,colibri_imx6dl-eval-v3", - "toradex,colibri_imx6dl", - "fsl,imx6dl"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; - /* - * Please make sure your carrier board does not pull-up any of - * the MMC/SD signals to 3.3 volt before attempting to activate - * UHS-I support. - * To let signaling voltage be changed to 1.8V, please - * delete no-1-8-v property (example below): - * /delete-property/no-1-8-v; - */ -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi deleted file mode 100644 index 7672fbfc29be..000000000000 --- a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&iomuxc { - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 - >; - }; -}; - -/* Colibri MMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <&vgen3_reg>; - wakeup-source; - keep-power-in-suspend; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 4e2a309c93fa..16d38bc78b2a 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -370,11 +370,14 @@ /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ disable-wp; - vqmmc-supply = <®_module_3v3>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; bus-width = <4>; no-1-8-v; status = "disabled"; @@ -692,6 +695,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 From patchwork Mon Apr 11 15:22:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Krummenacher X-Patchwork-Id: 12809315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9DF8C433F5 for ; Mon, 11 Apr 2022 15:23:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id D0900C385A9; Mon, 11 Apr 2022 15:23:01 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 01EEDC385A3; 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[31.10.206.124]) by smtp.gmail.com with ESMTPSA id a9-20020a7bc1c9000000b0038eb67e966esm5209374wmj.29.2022.04.11.08.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:22:58 -0700 (PDT) From: Max Krummenacher To: max.krummenacher@toradex.com List-Id: Cc: Arnd Bergmann , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Olof Johansson , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v2 12/14] ARM: dts: imx6dl-colibri: Add support for Toradex Iris carrier boards Date: Mon, 11 Apr 2022 17:22:32 +0200 Message-Id: <20220411152234.12678-13-max.oss.09@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220411152234.12678-1-max.oss.09@gmail.com> References: <20220411152234.12678-1-max.oss.09@gmail.com> MIME-Version: 1.0 From: Max Krummenacher Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm Computer Module family Carrier Board. Additional details available at https://www.toradex.com/products/carrier-board/iris-carrier-board Signed-off-by: Max Krummenacher --- (no changes since v1) arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts | 46 ++++++ arch/arm/boot/dts/imx6dl-colibri-iris.dts | 152 +++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ae3cac8e653b..cb4cf5453a9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,6 +459,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..3a6d3889760d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; + + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + cap-power-off-card; + /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ + /* /delete-property/ no-1-8-v; */ + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..cf77d894f6d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; + + /* + * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one + * wants to turn the transceiver off, that property has to be deleted + * and the gpio handled in userspace. + * The same applies to uart-b-c-on-x14-enable where the UART_B and + * UART_C transceiver is turned on. + */ + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; + + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_gpio_iris + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + >; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; From patchwork Mon Apr 11 15:22:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Krummenacher X-Patchwork-Id: 12809316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB502C433EF for ; Mon, 11 Apr 2022 15:23:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id C3873C385AB; Mon, 11 Apr 2022 15:23:02 +0000 (UTC) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id EF728C385A3; Mon, 11 Apr 2022 15:23:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org EF728C385A3 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f44.google.com with SMTP id e8so7156532wra.7; Mon, 11 Apr 2022 08:23:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ekfMytrXwLVzydWFQD06PuCm7n67RUjTXkiwu4FLXvs=; b=aPxWMdR75gd/4D6Lsy6bAdNv0SFjCryWfPLl0w8KOOFtNAf6s1SZSqbCXAVbLWd+pJ 2tTqjN3kozCFtNuc/PN8hFZqutlTtsh/gHPGftDNhxG4JPtbZST4fWvNiuo+T7gD7RQl KzfBE/DA1IKlP/reHOiDpH6HeD4XrFZgxm6ac22fWqoXeEOMZTRosDaETGcLRg3unKWL nPJPPc9qkiYLpcE8KqrfdhRDPcvA0xdrlinX/RGxfnIhohqNJhhXaIosDMuDTcIrZmff cnE6kGmOQ/AqZcsskhOq8ko0TJ0mREy2BZKs/dkcFGqKYi22PK4Jy2ayKpnUdP+CNRy0 cSDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ekfMytrXwLVzydWFQD06PuCm7n67RUjTXkiwu4FLXvs=; b=PoQ01TXX/Rrb3AJfb8356wAhiU/JwJUiAkNSQWClqQGfuknyEtdduBlqS6z6WGfPfF skztvjtdt/IEyottAAb3i2pQEYIK8v3CQljR1JFwBhU5yZew9QUf/AgOkVB8mnEClbfK px3CQUK/APaSqUFmaKZ5WBVSMSCBRUFmUDH1o0meuwyINp0/0GHDqL2RjaWxU5O0zN/s km7vndV4M6k/+RbVj6VlTISZ206/LZojve9od0hOavC2JR1FrGtIXtqOTTIlzH1YUtmf csOXydGOjSIAoMC81mWpwFleqTz3onAh3/TRQ6aUiS8156zgi0k8c9iyIwVyGSIWKAKf ++fQ== X-Gm-Message-State: AOAM532kagyuHt2R7NPcKX+M/DYlOomsCNoZUkj+fPjcH2i4hqxH5yhQ K/BGi9Wp08vbFQmno0kc4rE= X-Google-Smtp-Source: ABdhPJw5in+mLmhkhW+3PfyFB6K3625bOXc51YWBV1OlklZNsIStdVNwB/LtUZwhDul2D2AeAHJ4vQ== X-Received: by 2002:a05:6000:18ae:b0:204:62a:20f4 with SMTP id b14-20020a05600018ae00b00204062a20f4mr26767163wri.640.1649690580241; Mon, 11 Apr 2022 08:23:00 -0700 (PDT) Received: from linuxdev2.toradex.int (31-10-206-124.static.upc.ch. [31.10.206.124]) by smtp.gmail.com with ESMTPSA id a9-20020a7bc1c9000000b0038eb67e966esm5209374wmj.29.2022.04.11.08.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:22:59 -0700 (PDT) From: Max Krummenacher To: max.krummenacher@toradex.com List-Id: Cc: Arnd Bergmann , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Olof Johansson , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v2 13/14] ARM: dts: imx6dl-colibri: Add support for Toradex Aster carrier board Date: Mon, 11 Apr 2022 17:22:33 +0200 Message-Id: <20220411152234.12678-14-max.oss.09@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220411152234.12678-1-max.oss.09@gmail.com> References: <20220411152234.12678-1-max.oss.09@gmail.com> MIME-Version: 1.0 From: Max Krummenacher Add support for Toradex Aster, small form-factor with header compatible with Arduino Uno and Raspberry Pi (RPi) maker boards. Additional detail available at https://www.toradex.com/products/carrier-boards/aster-carrier-board Signed-off-by: Max Krummenacher --- (no changes since v1) arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-colibri-aster.dts | 113 +++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-aster.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cb4cf5453a9f..f0e5fc7e5274 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -458,6 +458,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ imx6dl-colibri-eval-v3.dtb \ imx6dl-colibri-iris.dtb \ imx6dl-colibri-iris-v2.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..74e8a6cd8bed --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_csi_gpio_1 + &pinctrl_gpio_2 + &pinctrl_gpio_aster + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + &pinctrl_weim_gpio_5 + >; + + pinctrl_gpio_aster: gpioaster { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +};