From patchwork Fri Apr 15 21:06:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5449EC433F5 for ; Fri, 15 Apr 2022 21:08:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SIvLbz3iXAKaor+aFjLtfcswQxkVVAXV/CF4qeuWMz0=; b=AlYKXNtzh6IDBu OAB00h/BqC3fqnz5suTsPphyDjur2rnJlGoXpLoRbXmP5VLRBECb0aC709MoQspYeuTBumdGR5Q4A vqRIaHWyT5iQTBv2DeyQ8uGW4QkGNacAmwM0dVddty+gId3itnQvtZ6hRBu4r/sWFUerBn5vIWrSE jLaho6gAxv5O00ChqHpUPZ6mOVyJgUGfCC2+O5KHg/qjRgZwmkR3fsBYqFvXP2kQ6wupKttHnbY1K j2VaIoZrxpfgQb5ldvXuM5M/2JaS1daPPoK4UyMhYSJVRlzXvglzqRglRLQs6Dp8Ga+1wq4fvxlEJ pjTl51su25SNNe5F8HEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfT9F-00BJiO-Ai; Fri, 15 Apr 2022 21:06:33 +0000 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfT9A-00BJff-UN; Fri, 15 Apr 2022 21:06:31 +0000 Received: by mail-qv1-xf2a.google.com with SMTP id a10so7157473qvm.8; Fri, 15 Apr 2022 14:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMYeeN0iZUy6EfrHqDAGGWFWHi99PGIp7rnql4YH69k=; b=jVy4wLQXJ5Xiw1bj4CpGcPN5pnCX6r59sOQO66Jz2Vvt9y4Tzwih3hlFcvyeCRD4Hr LG25pmwmM7+PyhWhkrHsXBYgNA8egqCTX/GQpcuiu6Z3xr6hQaQ674okap8z7lUy6jWH cI/MZpMTQQiQEtnnhPPF3nS2ALkqeJB3ADFpyVw3h1HJRB32It3hjvY5e+/WxOe6LS9p ZArv72BnSZ4UFPQCo6s86Gyg39ezv/dxU+L7EUHvsIKugHNqdCRkYJ+3Ut1aZ4aXxcsg YsXNTagZdOsdTXEW82dZ0JfC00y5Xlc3ZGqxfiowc/pXWOgMcQN9oy4bonSI9KD2lUHy eLhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMYeeN0iZUy6EfrHqDAGGWFWHi99PGIp7rnql4YH69k=; b=oR3EYDZSfXpF/QFGPzhoYJqkXM8wGQzJn+WuXAmfjFfU6cKM5r4Zwk4w3UKPk3Ic2h y7wA5RbHK3CmVvY3qAAa8K4BLQEz85YCnGQeJ4ueDOjgYPlLq442ZSDYpFAJ++DjZVrl PrM5QsDxRGOlyF6IAmXlTHToVA3sZ9NMxrhh0UdLkUx87FsuXeYDriNMgR42/qMGSWaM HcX4GqIE7kMcbcrUvU0hiJi6n3i+pmfV7sc1q8cYiZOZG4nqyg98oxpNTR40trj/7cXD kjEYjkyg6r0epYPvmBDpcy79NOQ1xKo4RtL/osDW2/PucwBhBe36FZoT9mVqZEemrSjD 6dKA== X-Gm-Message-State: AOAM531hzfqWgprtDXe9b8pAO+hXb9ILNafx+f1EE/4Y73/8BeztPnkW FlJhTKzXcEFmjvNU/2OGfnw= X-Google-Smtp-Source: ABdhPJxbrMCYX9pst0yUUj30dL5YGetX2lKuySfQVgVFm/cqlONSsHjg0w3yNcEDpoX2+Hn5wU7qSw== X-Received: by 2002:a05:6214:2aa5:b0:446:3a3d:bdf with SMTP id js5-20020a0562142aa500b004463a3d0bdfmr499333qvb.55.1650056787492; Fri, 15 Apr 2022 14:06:27 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w8-20020a05620a148800b0069c4884c990sm2838664qkj.108.2022.04.15.14.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 14:06:27 -0700 (PDT) From: Peter Geis To: Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: pci: remove fallback from Rockchip DesignWare binding Date: Fri, 15 Apr 2022 17:06:18 -0400 Message-Id: <20220415210621.538109-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220415210621.538109-1-pgwipeout@gmail.com> References: <20220415210621.538109-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220415_140629_011446_B742E5F6 X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The snps,dw-pcie binds to a standalone driver. It is not fully compatible with the Rockchip implementation and causes a hang if it binds to the device. Remove this binding as a valid fallback. Signed-off-by: Peter Geis --- .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..bc0a9d1db750 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -19,20 +19,10 @@ description: |+ allOf: - $ref: /schemas/pci/pci-bus.yaml# -# We need a select here so we don't match all nodes with 'snps,dw-pcie' -select: - properties: - compatible: - contains: - const: rockchip,rk3568-pcie - required: - - compatible - properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie reg: items: @@ -110,7 +100,7 @@ examples: #size-cells = <2>; pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; From patchwork Fri Apr 15 21:06:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBD1DC433EF for ; Fri, 15 Apr 2022 21:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 15 Apr 2022 14:06:28 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w8-20020a05620a148800b0069c4884c990sm2838664qkj.108.2022.04.15.14.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 14:06:28 -0700 (PDT) From: Peter Geis To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] PCI: dwc: rockchip: add legacy interrupt support Date: Fri, 15 Apr 2022 17:06:19 -0400 Message-Id: <20220415210621.538109-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220415210621.538109-1-pgwipeout@gmail.com> References: <20220415210621.538109-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220415_140631_037894_D71A112B X-CRM114-Status: GOOD ( 19.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The legacy interrupts on the rk356x pcie controller are handled by a single muxed interrupt. Add irq domain support to the pcie-dw-rockchip driver to support the virtual domain. Signed-off-by: Peter Geis --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 112 +++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index c9b341e55cbb..863374604fb1 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -10,9 +10,12 @@ #include #include +#include +#include #include #include #include +#include #include #include #include @@ -36,10 +39,13 @@ #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c #define PCIE_CLIENT_GENERAL_DEBUG 0x104 -#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) +#define PCIE_LEGACY_INT_ENABLE GENMASK(3, 0) +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) struct rockchip_pcie { @@ -51,6 +57,8 @@ struct rockchip_pcie { struct reset_control *rst; struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; + struct irq_domain *irq_domain; + raw_spinlock_t irq_lock; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, @@ -65,6 +73,94 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, writel_relaxed(val, rockchip->apb_base + reg); } +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); + unsigned long reg, hwirq; + + chained_irq_enter(chip, desc); + + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); + + for_each_set_bit(hwirq, ®, 8) + generic_handle_domain_irq(rockchip->irq_domain, hwirq); + + chained_irq_exit(chip, desc); +} + +static void rockchip_intx_mask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* disable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val |= PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static void rockchip_intx_unmask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* enable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val &= ~PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static struct irq_chip rockchip_intx_irq_chip = { + .name = "INTx", + .irq_mask = rockchip_intx_mask, + .irq_unmask = rockchip_intx_unmask, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, +}; + +static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = rockchip_pcie_intx_map, +}; + +static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->pci.dev; + struct device_node *intc; + + raw_spin_lock_init(&rockchip->irq_lock); + + intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); + if (!intc) { + dev_err(dev, "missing child interrupt-controller node\n"); + return -EINVAL; + } + + rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, + &intx_domain_ops, rockchip); + of_node_put(intc); + if (!rockchip->irq_domain) { + dev_err(dev, "failed to get a INTx IRQ domain\n"); + return -EINVAL; + } + + return 0; +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -111,7 +207,19 @@ static int rockchip_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + struct device *dev = rockchip->pci.dev; u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + int irq, ret; + + irq = of_irq_get_byname(dev->of_node, "legacy"); + if (irq < 0) + return irq; + + ret = rockchip_pcie_init_irq_domain(rockchip); + if (ret < 0) + dev_err(dev, "failed to init irq domain\n"); + + irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip); /* LTSSM enable control mode */ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); From patchwork Fri Apr 15 21:06:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 904EDC433EF for ; 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Fri, 15 Apr 2022 14:06:29 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller Date: Fri, 15 Apr 2022 17:06:20 -0400 Message-Id: <20220415210621.538109-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220415210621.538109-1-pgwipeout@gmail.com> References: <20220415210621.538109-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220415_140630_982038_1CCC2016 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pcie2x1 controller is commong between the rk3568 and rk3566. It is a single lane pcie2 compliant controller. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 68 ++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index ca20d7b91fe5..d5131f5aaf73 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -270,10 +270,17 @@ gic: interrupt-controller@fd400000 { <0x0 0xfd460000 0 0x80000>; /* GICR */ interrupts = ; interrupt-controller; + ranges; #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; + #address-cells = <2>; + #size-cells = <2>; + + its: interrupt-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { @@ -722,6 +729,61 @@ qos_vop_m1: qos@fe1a8100 { reg = <0x0 0xfe1a8100 0x0 0x20>; }; + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x00000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 + 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; + }; + + }; + sdmmc0: mmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2b0000 0x0 0x4000>; From patchwork Fri Apr 15 21:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BEBBC433F5 for ; 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Fri, 15 Apr 2022 14:06:30 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: rockchip: enable pcie controller on quartz64-a Date: Fri, 15 Apr 2022 17:06:21 -0400 Message-Id: <20220415210621.538109-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220415210621.538109-1-pgwipeout@gmail.com> References: <20220415210621.538109-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220415_140632_289650_4ED9681C X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the nodes to enable the pcie controller on the quartz64 model a board. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 141a433429b5..85926d46337d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -125,6 +125,18 @@ vbus: vbus { vin-supply = <&vcc12v_dcin>; }; + vcc3v3_pcie_p: vcc3v3_pcie_p { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + vcc5v0_usb: vcc5v0_usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -201,6 +213,10 @@ &combphy1 { status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -509,6 +525,14 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie_p>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -534,6 +558,16 @@ diy_led_enable_h: diy-led-enable-h { }; }; + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;