From patchwork Mon Apr 18 18:49:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12817046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 846C4C433F5 for ; Mon, 18 Apr 2022 18:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347476AbiDRSwq (ORCPT ); Mon, 18 Apr 2022 14:52:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234453AbiDRSwq (ORCPT ); Mon, 18 Apr 2022 14:52:46 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1E801D33F; Mon, 18 Apr 2022 11:50:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1650307795; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7nc5sIEFkzgJ2j9U+7Rs4qBYEvdcvvjY3ksRsV+cjhc=; b=0zEbo+PYGQgtMfZM6hGiyltpSPPhFv8Y6+yi5oZYU78tTx4Vkcn8sr25so6RaGPhgkhRBD DeRV7xdx24/fVfMveXZv3OhVITOodRIvVfZcFS4CiC0NXL8rtbhzcjhIwldqUE4JeJjBGh AEuxC66TNNwuE8EgsyqV4/+n2doloCE= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni Cc: list@opendingux.net, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Cercueil , Rob Herring , Krzysztof Kozlowski Subject: [PATCH 1/5] dt-bindings: rtc: Rework compatible strings and add #clock-cells Date: Mon, 18 Apr 2022 19:49:29 +0100 Message-Id: <20220418184933.13172-2-paul@crapouillou.net> In-Reply-To: <20220418184933.13172-1-paul@crapouillou.net> References: <20220418184933.13172-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The RTC in the JZ4770 is compatible with the JZ4760, but has an extra register that permits to configure the behaviour of the CLK32K pin. The same goes for the RTC in the JZ4780. Therefore, the ingenic,jz4770-rtc and ingenic,jz4780-rtc strings do not fall back anymore to ingenic,jz4760-rtc. The ingenic,jz4780-rtc string now falls back to the ingenic,jz4770-rtc string. Additionally, since the RTCs in the JZ4770 and JZ4780 support outputting the input oscillator's clock to the CLK32K pin, the RTC node is now also a clock provider on these SoCs, so a #clock-cells property is added. Signed-off-by: Paul Cercueil Cc: Rob Herring Cc: Krzysztof Kozlowski --- Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml index b235b2441997..57393c3ac724 100644 --- a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml @@ -18,14 +18,14 @@ properties: - enum: - ingenic,jz4740-rtc - ingenic,jz4760-rtc + - ingenic,jz4770-rtc - items: - const: ingenic,jz4725b-rtc - const: ingenic,jz4740-rtc - items: - enum: - - ingenic,jz4770-rtc - ingenic,jz4780-rtc - - const: ingenic,jz4760-rtc + - const: ingenic,jz4770-rtc reg: maxItems: 1 @@ -39,6 +39,9 @@ properties: clock-names: const: rtc + "#clock-cells": + const: 0 + system-power-controller: description: | Indicates that the RTC is responsible for powering OFF From patchwork Mon Apr 18 18:49:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12817048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75986C433FE for ; Mon, 18 Apr 2022 18:50:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234453AbiDRSxB (ORCPT ); Mon, 18 Apr 2022 14:53:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347494AbiDRSw6 (ORCPT ); Mon, 18 Apr 2022 14:52:58 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3167E2409F; Mon, 18 Apr 2022 11:50:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1650307796; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PoJz1zVmmGsJWV0gMARBBVsLegYd3/w6zzW9TULqzRM=; b=tFVojG5TYy5pIwBa9Ykk6LKaEOCGbPlWvBhnBoMlhTy/vyAF6qWDLIBhsrBXjwWfTD+Upf pWn5DNE0FfXlVuBORXtxE9X6+UeUiOTi/zbrVS0dDXfpDVLna+sD8wJbR+9lHnF2oDFcKH 09031E8+v0AlwoDLaq5egDfCeG8Dqqw= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni Cc: list@opendingux.net, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Cercueil Subject: [PATCH 2/5] rtc: jz4740: Use readl_poll_timeout Date: Mon, 18 Apr 2022 19:49:30 +0100 Message-Id: <20220418184933.13172-3-paul@crapouillou.net> In-Reply-To: <20220418184933.13172-1-paul@crapouillou.net> References: <20220418184933.13172-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use readl_poll_timeout() from instead of using custom poll loops. The timeout settings are different, but that shouldn't be much of a problem. Instead of polling 10000 times in a close loop, it polls for one millisecond. Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 6e51df72fd65..119baf168b32 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -69,19 +70,15 @@ static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg) static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc) { uint32_t ctrl; - int timeout = 10000; - do { - ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); - } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); - - return timeout ? 0 : -EIO; + return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, + ctrl & JZ_RTC_CTRL_WRDY, 0, 1000); } static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc) { uint32_t ctrl; - int ret, timeout = 10000; + int ret; ret = jz4740_rtc_wait_write_ready(rtc); if (ret != 0) @@ -89,11 +86,8 @@ static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc) writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); - do { - ctrl = readl(rtc->base + JZ_REG_RTC_WENR); - } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); - - return timeout ? 0 : -EIO; + return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, + ctrl & JZ_RTC_WENR_WEN, 0, 1000); } static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg, From patchwork Mon Apr 18 18:49:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12817047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85409C4332F for ; Mon, 18 Apr 2022 18:50:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347499AbiDRSxD (ORCPT ); Mon, 18 Apr 2022 14:53:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347492AbiDRSxB (ORCPT ); Mon, 18 Apr 2022 14:53:01 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3A5F2F39B; Mon, 18 Apr 2022 11:50:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1650307797; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gTydCTe/7cAyLlIMweK5uFG1GYH9QzGk2uqsrqg28Oo=; b=HEvosaXqUAJaM43ThX9L/5w3WJ5BrXLFRg2EUIjxmL/MdlW+LOPXb1fnpElIc/Dgkc9Xng aeTnMj+yhDrIWcGaCC964jixem3O3aRwgx1mr8OTX9vqrAhNRorIHgk/BaM4exFfF3q13i 23jRa11lv0AXN4W/s74zEnjewY7HOwI= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni Cc: list@opendingux.net, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Cercueil Subject: [PATCH 3/5] rtc: jz4740: Reset scratchpad register on power loss Date: Mon, 18 Apr 2022 19:49:31 +0100 Message-Id: <20220418184933.13172-4-paul@crapouillou.net> In-Reply-To: <20220418184933.13172-1-paul@crapouillou.net> References: <20220418184933.13172-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On power loss, reading the RTC value would fail as the scratchpad lost its magic value, until the hardware clock was set once again. To avoid that, reset the RTC value to Epoch in the probe if we detect that the scratchpad lost its magic value. Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 119baf168b32..aac5f68bf626 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -42,6 +42,9 @@ /* Magic value to enable writes on jz4780 */ #define JZ_RTC_WENR_MAGIC 0xA55A +/* Value written to the scratchpad to detect power losses */ +#define JZ_RTC_SCRATCHPAD_MAGIC 0x12345678 + #define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 #define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 @@ -134,10 +137,11 @@ static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask, static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time) { struct jz4740_rtc *rtc = dev_get_drvdata(dev); - uint32_t secs, secs2; + uint32_t secs, secs2, magic; int timeout = 5; - if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678) + magic = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD); + if (magic != JZ_RTC_SCRATCHPAD_MAGIC) return -EINVAL; /* If the seconds register is read while it is updated, it can contain a @@ -169,7 +173,8 @@ static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time) if (ret) return ret; - return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678); + return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, + JZ_RTC_SCRATCHPAD_MAGIC); } static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) @@ -307,6 +312,7 @@ static int jz4740_rtc_probe(struct platform_device *pdev) struct jz4740_rtc *rtc; unsigned long rate; struct clk *clk; + uint32_t magic; int ret, irq; rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); @@ -369,6 +375,18 @@ static int jz4740_rtc_probe(struct platform_device *pdev) /* Each 1 Hz pulse should happen after (rate) ticks */ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1); + magic = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD); + if (magic != JZ_RTC_SCRATCHPAD_MAGIC) { + /* + * If the scratchpad doesn't hold our magic value, then a + * power loss occurred. Reset to Epoch. + */ + struct rtc_time time; + + rtc_time64_to_tm(0, &time); + jz4740_rtc_set_time(dev, &time); + } + ret = devm_rtc_register_device(rtc->rtc); if (ret) return ret; From patchwork Mon Apr 18 18:49:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12817049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1190C433F5 for ; Mon, 18 Apr 2022 18:50:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347525AbiDRSxQ (ORCPT ); Mon, 18 Apr 2022 14:53:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347516AbiDRSxJ (ORCPT ); Mon, 18 Apr 2022 14:53:09 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3752722514; Mon, 18 Apr 2022 11:50:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1650307798; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZlyW45e+iUvXF1qLLn4ctjlyJZvRF5CDmcQahzk9/7c=; b=xvUbwuzxpT1C5eNIIh5SuS7eC7kyLp0vD6wa7o0r5T9+0juVMN+RGwSQnN43Cv7DcxTIOR V/BrU3mFoYoWe4k6yGWi5RMcXCUo+HckygFA5zH2eeypi2LEno9dUCBCTZNLYiVgxmCg2K lrmtCZob3rSKMzTsOx1W6cSvhCPxZKU= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni Cc: list@opendingux.net, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Cercueil Subject: [PATCH 4/5] rtc: jz4740: Register clock provider for the CLK32K pin Date: Mon, 18 Apr 2022 19:49:32 +0100 Message-Id: <20220418184933.13172-5-paul@crapouillou.net> In-Reply-To: <20220418184933.13172-1-paul@crapouillou.net> References: <20220418184933.13172-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On JZ4770 and JZ4780, the CLK32K pin is configurable. By default, it is configured as a GPIO in input mode, and its value can be read through GPIO PD14. With this change, clients can now request the 32 kHz clock on the CLK32K pin, through Device Tree. This clock is simply a pass-through of the input oscillator's clock with enable/disable operations. This will permit the WiFi/Bluetooth chip to work on the MIPS CI20 board, which does source one of its clocks from the CLK32K pin. Signed-off-by: Paul Cercueil Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/rtc/rtc-jz4740.c | 50 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index aac5f68bf626..f4c9b6058f07 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -26,6 +27,7 @@ #define JZ_REG_RTC_WAKEUP_FILTER 0x24 #define JZ_REG_RTC_RESET_COUNTER 0x28 #define JZ_REG_RTC_SCRATCHPAD 0x34 +#define JZ_REG_RTC_CKPCR 0x40 /* The following are present on the jz4780 */ #define JZ_REG_RTC_WENR 0x3C @@ -48,10 +50,13 @@ #define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 #define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 +#define JZ_RTC_CKPCR_CK32PULL_DIS BIT(4) +#define JZ_RTC_CKPCR_CK32CTL_EN (BIT(2) | BIT(1)) + enum jz4740_rtc_type { ID_JZ4740, ID_JZ4760, - ID_JZ4780, + ID_JZ4770, }; struct jz4740_rtc { @@ -60,6 +65,8 @@ struct jz4740_rtc { struct rtc_device *rtc; + struct clk_hw clk32k; + spinlock_t lock; }; @@ -264,7 +271,8 @@ static void jz4740_rtc_clk_disable(void *data) static const struct of_device_id jz4740_rtc_of_match[] = { { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 }, { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 }, - { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 }, + { .compatible = "ingenic,jz4770-rtc", .data = (void *)ID_JZ4770 }, + { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4770 }, {}, }; MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match); @@ -305,6 +313,27 @@ static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc, jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks); } +static int jz4740_rtc_clk32k_enable(struct clk_hw *hw) +{ + struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k); + + return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, + JZ_RTC_CKPCR_CK32PULL_DIS | + JZ_RTC_CKPCR_CK32CTL_EN); +} + +static void jz4740_rtc_clk32k_disable(struct clk_hw *hw) +{ + struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k); + + jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, 0); +} + +static const struct clk_ops jz4740_rtc_clk32k_ops = { + .enable = jz4740_rtc_clk32k_enable, + .disable = jz4740_rtc_clk32k_disable, +}; + static int jz4740_rtc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -407,6 +436,23 @@ static int jz4740_rtc_probe(struct platform_device *pdev) dev_warn(dev, "Poweroff handler already present!\n"); } + if (rtc->type == ID_JZ4770) { + rtc->clk32k.init = CLK_HW_INIT("clk32k", "rtc", + &jz4740_rtc_clk32k_ops, 0); + + ret = devm_clk_hw_register(dev, &rtc->clk32k); + if (ret) { + dev_err(dev, "Unable to register clk32k clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &rtc->clk32k); + if (ret) { + dev_err(dev, "Unable to register clk32k clock provider: %d\n", ret); + return ret; + } + } + return 0; } From patchwork Mon Apr 18 18:49:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12817050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13FD0C4332F for ; Mon, 18 Apr 2022 18:51:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235160AbiDRSyY (ORCPT ); Mon, 18 Apr 2022 14:54:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347541AbiDRSxV (ORCPT ); Mon, 18 Apr 2022 14:53:21 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF6502409F; Mon, 18 Apr 2022 11:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1650307798; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c/CT07nqqL/kRUfaHG3whhK5ysTGqgD0sA53BitiVSo=; b=P/2SAq3V8XLIIw3N33ms4X7AHzfiKEDhTzzLbmZEhHIdJ5TuaQtBKB5nHUqwJ4DzEbNcuJ HPKn1kEAJ7i0umFwILtCLvi7LEi1dQfpguqWX680yq5mBPy11xljkr8+zlonLjRze+5l42 mPQIc9Sh3Q5jiz7f4MM+HBUI9MHgWUU= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni Cc: list@opendingux.net, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Cercueil Subject: [PATCH 5/5] rtc: jz4740: Support for fine-tuning the RTC clock Date: Mon, 18 Apr 2022 19:49:33 +0100 Message-Id: <20220418184933.13172-6-paul@crapouillou.net> In-Reply-To: <20220418184933.13172-1-paul@crapouillou.net> References: <20220418184933.13172-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Write the NC1HZ and ADJC register fields, which allow to tweak the frequency of the RTC clock, so that it can run as accurately as possible. Signed-off-by: Paul Cercueil Reported-by: kernel test robot --- drivers/rtc/rtc-jz4740.c | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index f4c9b6058f07..f275e58a9cea 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -5,6 +5,7 @@ * JZ4740 SoC RTC driver */ +#include #include #include #include @@ -41,6 +42,9 @@ #define JZ_RTC_CTRL_AE BIT(2) #define JZ_RTC_CTRL_ENABLE BIT(0) +#define JZ_RTC_REGULATOR_NC1HZ_MASK GENMASK(15, 0) +#define JZ_RTC_REGULATOR_ADJC_MASK GENMASK(25, 16) + /* Magic value to enable writes on jz4780 */ #define JZ_RTC_WENR_MAGIC 0xA55A @@ -64,6 +68,7 @@ struct jz4740_rtc { enum jz4740_rtc_type type; struct rtc_device *rtc; + struct clk *clk; struct clk_hw clk32k; @@ -222,12 +227,51 @@ static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable); } +static int jz4740_rtc_read_offset(struct device *dev, long *offset) +{ + struct jz4740_rtc *rtc = dev_get_drvdata(dev); + long rate = clk_get_rate(rtc->clk); + s32 nc1hz, adjc, offset1k; + u32 reg; + + reg = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_REGULATOR); + nc1hz = FIELD_GET(JZ_RTC_REGULATOR_NC1HZ_MASK, reg); + adjc = FIELD_GET(JZ_RTC_REGULATOR_ADJC_MASK, reg); + + offset1k = (nc1hz - rate + 1) * 1024L + adjc; + *offset = offset1k * 1000000L / (rate * 1024L); + + return 0; +} + +static int jz4740_rtc_set_offset(struct device *dev, long offset) +{ + struct jz4740_rtc *rtc = dev_get_drvdata(dev); + long rate = clk_get_rate(rtc->clk); + s32 offset1k, adjc, nc1hz; + + offset1k = div_s64_rem(offset * rate * 1024LL, 1000000LL, &adjc); + nc1hz = rate - 1 + offset1k / 1024L; + + if (adjc < 0) { + nc1hz--; + adjc += 1024; + } + + nc1hz = FIELD_PREP(JZ_RTC_REGULATOR_NC1HZ_MASK, nc1hz); + adjc = FIELD_PREP(JZ_RTC_REGULATOR_ADJC_MASK, adjc); + + return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, nc1hz | adjc); +} + static const struct rtc_class_ops jz4740_rtc_ops = { .read_time = jz4740_rtc_read_time, .set_time = jz4740_rtc_set_time, .read_alarm = jz4740_rtc_read_alarm, .set_alarm = jz4740_rtc_set_alarm, .alarm_irq_enable = jz4740_rtc_alarm_irq_enable, + .read_offset = jz4740_rtc_read_offset, + .set_offset = jz4740_rtc_set_offset, }; static irqreturn_t jz4740_rtc_irq(int irq, void *data) @@ -378,6 +422,7 @@ static int jz4740_rtc_probe(struct platform_device *pdev) spin_lock_init(&rtc->lock); + rtc->clk = clk; platform_set_drvdata(pdev, rtc); device_init_wakeup(dev, 1);