From patchwork Tue Apr 19 08:46:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12817628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92243C433F5 for ; Tue, 19 Apr 2022 08:47:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344465AbiDSItz (ORCPT ); Tue, 19 Apr 2022 04:49:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240442AbiDSIty (ORCPT ); Tue, 19 Apr 2022 04:49:54 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2132D22B0D; Tue, 19 Apr 2022 01:47:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650358032; x=1681894032; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=lfyGlOwBn9Oqk37H4rCgm5uXFJD2It20JCnLmPhZ6qc=; b=nKUze+PQ/ooAXXn2udk4YcGVo3KvxcEdHO6u74CcAUCoiFoeE5QH+Ngz 6ICMtfLqpmpr3qf7KZ9d9halBXPrtvTOp1iRegOdcsjqtQBjHk0ZEVr5h nRXpJRZH15vy5oYL+q6pA/Ok8hqgqfggk9jksYygUUgKUCxxvepKVWhsb tmnvsCktu522tfeNU9d67kjPYFGkZ7e3OV3q/MP47hRkoos2SPzHhT1M9 lyE+ORp4Uf1WkM7G20cAFoRJc0Y8XXukYPvGJpgUtGuX2OCbpeLa0Pw3c xN5svtCE+sVo3N4DHprQSnqdr3L3yDFnmL5Q7MqeARGbrgc3jD1j3kTCR Q==; X-IronPort-AV: E=Sophos;i="5.90,272,1643670000"; d="scan'208";a="23351059" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 19 Apr 2022 10:47:08 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Tue, 19 Apr 2022 10:47:08 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Tue, 19 Apr 2022 10:47:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650358028; x=1681894028; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=lfyGlOwBn9Oqk37H4rCgm5uXFJD2It20JCnLmPhZ6qc=; b=RlbZYs6HbEw/+0ju8CZhkYtUstSpLJf9etbQRRkb5MkyHLqGTXty7gGs AWMIaG5Oqa2iCru62idW4JbbQdvphu7ckJXNLp+7sc+c1RXR2Q8dDONTh OsPAWcxsy+TQ5LQmK0xwmL5v9K3bAMxhdjch8hzgYz1U7lVVbnoTH7/QQ ge0S1dM1LC4mlYz9DH238Rb3Uxd7ZpXkaj6Pa0Pk16Hahk9eEDgRhI5fT Ep0mJeqCytzu3uz3EC5UqS8rgT0Ovt2vNR7Fzkk0Fluf4CE6KdFH5VB33 4wVFKQLdjNo91TuR3g3ydOUJp06klAZ676OxwomCv7LMgwU6+EXKfoHHG A==; X-IronPort-AV: E=Sophos;i="5.90,272,1643670000"; d="scan'208";a="23351045" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 19 Apr 2022 10:47:02 +0200 Received: from localhost.localdomain (SCHIFFERM-M2.tq-net.de [10.121.49.14]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id CE4CF280070; Tue, 19 Apr 2022 10:46:57 +0200 (CEST) From: Matthias Schiffer To: Mark Brown Cc: Pratyush Yadav , Tudor Ambarus , Vignesh Raghavendra , Ramuthevar Vadivel Murugan , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH 1/2] spi: cadence-quadspi: further simplify cqspi_set_protocol() Date: Tue, 19 Apr 2022 10:46:39 +0200 Message-Id: <20220419084640.191299-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org - Remove checks for unsupported modes that are already handled by supports_op(). This allows to change the function to return void. - Distinguishing DTR and non-DTR modes is not necessary for the setup of the bus widths - Only cmd DTR flag needs to be checked, supports_op() already checks that the DTR flags of all relevant parts of the op match - Check nbytes instead of buswidth for 0, for consistency with supports_op() etc. Signed-off-by: Matthias Schiffer --- drivers/spi/spi-cadence-quadspi.c | 73 +++++-------------------------- 1 file changed, 10 insertions(+), 63 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 19686fb47bb3..96d14f3847b5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -368,58 +368,13 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) return dummy_clk; } -static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) +static void cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op) { - /* - * For an op to be DTR, cmd phase along with every other non-empty - * phase should have dtr field set to 1. If an op phase has zero - * nbytes, ignore its dtr field; otherwise, check its dtr field. - */ - f_pdata->dtr = op->cmd.dtr && - (!op->addr.nbytes || op->addr.dtr) && - (!op->data.nbytes || op->data.dtr); - - f_pdata->inst_width = 0; - if (op->cmd.buswidth) - f_pdata->inst_width = ilog2(op->cmd.buswidth); - - f_pdata->addr_width = 0; - if (op->addr.buswidth) - f_pdata->addr_width = ilog2(op->addr.buswidth); - - f_pdata->data_width = 0; - if (op->data.buswidth) - f_pdata->data_width = ilog2(op->data.buswidth); - - /* Right now we only support 8-8-8 DTR mode. */ - if (f_pdata->dtr) { - switch (op->cmd.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - - switch (op->addr.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - - switch (op->data.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - } - - return 0; + f_pdata->inst_width = op->cmd.nbytes ? ilog2(op->cmd.buswidth) : 0; + f_pdata->addr_width = op->addr.nbytes ? ilog2(op->addr.buswidth) : 0; + f_pdata->data_width = op->data.nbytes ? ilog2(op->data.buswidth) : 0; + f_pdata->dtr = op->cmd.dtr; } static int cqspi_wait_idle(struct cqspi_st *cqspi) @@ -549,9 +504,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, size_t read_len; int status; - status = cqspi_set_protocol(f_pdata, op); - if (status) - return status; + cqspi_set_protocol(f_pdata, op); status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, f_pdata->dtr); @@ -622,9 +575,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, size_t write_len; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; + cqspi_set_protocol(f_pdata, op); ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, f_pdata->dtr); @@ -1244,9 +1195,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, const u_char *buf = op->data.buf.out; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; + cqspi_set_protocol(f_pdata, op); ret = cqspi_write_setup(f_pdata, op); if (ret) @@ -1348,9 +1297,7 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, int ret; ddata = of_device_get_match_data(dev); - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; + cqspi_set_protocol(f_pdata, op); ret = cqspi_read_setup(f_pdata, op); if (ret) From patchwork Tue Apr 19 08:46:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12817629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AF8EC433EF for ; Tue, 19 Apr 2022 08:47:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240442AbiDSIt6 (ORCPT ); Tue, 19 Apr 2022 04:49:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346851AbiDSIt4 (ORCPT ); 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19 Apr 2022 10:47:02 +0200 Received: from localhost.localdomain (SCHIFFERM-M2.tq-net.de [10.121.49.14]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 013C8280075; Tue, 19 Apr 2022 10:46:57 +0200 (CEST) From: Matthias Schiffer To: Mark Brown Cc: Pratyush Yadav , Tudor Ambarus , Vignesh Raghavendra , Ramuthevar Vadivel Murugan , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH 2/2] spi: cadence-quadspi: allow operations with cmd/addr buswidth >1 Date: Tue, 19 Apr 2022 10:46:40 +0200 Message-Id: <20220419084640.191299-2-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220419084640.191299-1-matthias.schiffer@ew.tq-group.com> References: <20220419084640.191299-1-matthias.schiffer@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org With the improved cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previosly allowed 8-8-8 ops). Signed-off-by: Matthias Schiffer --- drivers/spi/spi-cadence-quadspi.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 96d14f3847b5..08f39f52e32a 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1370,13 +1370,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, return false; if (op->data.nbytes && op->data.buswidth != 8) return false; - } else if (all_false) { - /* Only 1-1-X ops are supported without DTR */ - if (op->cmd.nbytes && op->cmd.buswidth > 1) - return false; - if (op->addr.nbytes && op->addr.buswidth > 1) - return false; - } else { + } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; }