From patchwork Tue Apr 19 10:27:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12817730 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7426C433EF for ; Tue, 19 Apr 2022 10:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242181AbiDSKaM (ORCPT ); Tue, 19 Apr 2022 06:30:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242166AbiDSKaJ (ORCPT ); Tue, 19 Apr 2022 06:30:09 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CAFE2655E for ; Tue, 19 Apr 2022 03:27:24 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id c190-20020a1c35c7000000b0038e37907b5bso1261355wma.0 for ; Tue, 19 Apr 2022 03:27:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SsebvKOYokXaJagvEDFDSbIazWtZdVMdtGwXTxdqiEY=; b=jCgzCTInl5IYOadrG9WDwFXRlUaAFQKPa6+CFdtUoSxDB4KkPlkiBl3IKhCRBFz8ow kWvz1UUfALZmImtqLEZ8McF68KFtZwgn3lYgJmMOSJixHZYCyLkcV4PMmoFMWsYaqabj ZgxznfG7Q7LWIKyZwL00L2TEdksyVf3ZBupcLAcXDhgkJS26oiF5AC03lfkgpSWb73hz f4mC1zzsI0H95ZK98paeSKnNge3FYtmtaRL0RT+29KJSyO8P+JXYQE2CANeirHrUTtwo wUixSclnO5Nsn1sDH/R5vKzx0IaAMiXg5OqlXxS8xbCXhDEuNinJ8iQG5MYkhk+g+3Pm J8aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SsebvKOYokXaJagvEDFDSbIazWtZdVMdtGwXTxdqiEY=; b=mNypTiGE+QR3u7OKuChJFubSprWznlAN2rPZpkgbQgjrQ/IbmcYWmOaE/Q9SGU6cde qy0jjxMc+4+wpmVQo8rJVIlcCdUJE4QqSVqSseHc7jy4X6RvZL4+IalhrKaN7ImTCzBr CR1+EYA7mx6FtFvlOgLxgByKIgiiGVTEWPa0FCZidz0bVf33WQI4/CQPk9eNqqzkbXA0 4099btVtWnB8perqh9KDuocDx12s8gg8jI9IiRj00R1e92e/SPBeVy1g9YH9xuNahurD Jo2i7tSuPZgKvNYguvdFuHiCING8FbKjD9tEyaiOI7L5m+lnFBQSBCrAmOdL+gHllQNk QqRA== X-Gm-Message-State: AOAM5339yT05NVkRaJp+UO17Qx33kLGR64gz+KclIJ8A0Ym9cSHjNCYv QBGFB20eKDGST0v9IXJrzTsIb3BXX4Z8qULD X-Google-Smtp-Source: ABdhPJyCrFR4HvGsP59e4e8wADqqvbLSyhuuYKUKr/nq6q+fcw9b60JbuuOLkElcBc+65zkvYPLrvg== X-Received: by 2002:a1c:2744:0:b0:382:a9b7:1c8a with SMTP id n65-20020a1c2744000000b00382a9b71c8amr14715656wmn.187.1650364042725; Tue, 19 Apr 2022 03:27:22 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id m4-20020a7bcb84000000b00389efb7a5b4sm19036166wmi.17.2022.04.19.03.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 03:27:22 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Alexandru Ardelean Subject: [PATCH v2 1/3] dt-bindings: net: adin: document phy clock output properties Date: Tue, 19 Apr 2022 13:27:07 +0300 Message-Id: <20220419102709.26432-2-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220419102709.26432-1-josua@solid-run.com> References: <20220410104626.11517-1-josua@solid-run.com> <20220419102709.26432-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add DT properties to configure both pins. Signed-off-by: Josua Mayer Reviewed-by: Andrew Lunn --- V1 -> V2: changed clkout property to enum V1 -> V2: added property for CLK25_REF pin .../devicetree/bindings/net/adi,adin.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 1129f2b58e98..3e0c6304f190 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -36,6 +36,23 @@ properties: enum: [ 4, 8, 12, 16, 20, 24 ] default: 8 + adi,phy-output-clock: + description: Select clock output on GP_CLK pin. Three clocks are available: + A 25MHz reference, a free-running 125MHz and a recovered 125MHz. + The phy can also automatically switch between the reference and the + respective 125MHz clocks based on its internal state. + $ref: /schemas/types.yaml#/definitions/string + enum: + - 25mhz-reference + - 125mhz-free-running + - 125mhz-recovered + - adaptive-free-running + - adaptive-recovered + + adi,phy-output-reference-clock: + description: Enable 25MHz reference clock output on CLK25_REF pin. + $ref: /schemas/types.yaml#/definitions/flag + unevaluatedProperties: false examples: From patchwork Tue Apr 19 10:27:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12817731 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37578C433EF for ; Tue, 19 Apr 2022 10:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242187AbiDSKaN (ORCPT ); Tue, 19 Apr 2022 06:30:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242200AbiDSKaL (ORCPT ); Tue, 19 Apr 2022 06:30:11 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6C8C27B04 for ; Tue, 19 Apr 2022 03:27:28 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id g18so21755319wrb.10 for ; Tue, 19 Apr 2022 03:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G6dhAVYyP/wywNlXMOP4V43Gf3+8APppoWjfx5jTK/w=; b=3UN1h382knsq7/ihsf5/UGJAe2yzIlCc0lwTnZ/xfBu8RM60dJZheaJbCLPr1Dx6Td pYhaNwfjGwv0wNjJPVfNP66Ar59GT+hT87QoQCPy7SJeBKnQzK3mpNZo81Jn1ltSJ10O AZSqGvFdlVLCr8ACQKy47oG5aaTExoF/Jds0zqv78ymyHdXyO65F3DjcOHGJIkgpHKJ9 web1lgonzOvq69fis9w3SVB8aThcnT3+hnrjCJLMWlw0olcu74mSI4QDsAMc/Xtw8GAk NTJLXa5r82V6JzkNsLhWZWV+JWcSRls/GFfaXhgsEWrk65VNemSi8JAemKMDRum7ggEm Y9PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G6dhAVYyP/wywNlXMOP4V43Gf3+8APppoWjfx5jTK/w=; b=bZ6HAWGdH6HwIBqxQrBvzR2i7gSQ4niK2Xe5mNmNfAyguf1N5OvPdRrI7N+1N7Ghwk g+Ika+D90sS2xf+DoS3USpm8HAxiibLIMoff+GtWILgvFfFWq2NCcweAnDdjCTiazaK2 prEoECLNt1t7q+A3zasKXVwj6eDdsmGeg1dJ8FVK7BwHOwFbBIj0Dl7KgCKXkJd6tsVf iFze9btmjDf7ZRewlFmXsoptfBeGRm68w3CL5F4gUM8rqlEmJwLzrFG0KDPqTYzMa1zq UNYq1d24Y3qA64klACGsaAyeKQVu7fBtJSzpfCewFjXRGM1DJsRgiM30Pcxn3U0R55hk u/Jw== X-Gm-Message-State: AOAM531QbgCCBVzI0362d37EZlKJOUw0WVtV631AiwmmFw/eSFwsah6p hVUNmwvY4yJbhDA+nPg+7GLdf0Nvia3CCgRx X-Google-Smtp-Source: ABdhPJxQhf8jq3gLp+KKe2oI0YbYBbttyCeoLBSaF26ZDhwb/mhs6B5Ed4Xp0OMI0PFaRON2zlMc1A== X-Received: by 2002:a05:6000:110f:b0:207:a89b:ddf9 with SMTP id z15-20020a056000110f00b00207a89bddf9mr11410223wrw.371.1650364047004; Tue, 19 Apr 2022 03:27:27 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id m4-20020a7bcb84000000b00389efb7a5b4sm19036166wmi.17.2022.04.19.03.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 03:27:26 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , Paolo Abeni Subject: [PATCH v2 2/3] net: phy: adin: add support for clock output Date: Tue, 19 Apr 2022 13:27:08 +0300 Message-Id: <20220419102709.26432-3-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220419102709.26432-1-josua@solid-run.com> References: <20220410104626.11517-1-josua@solid-run.com> <20220419102709.26432-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer Reported-by: kernel test robot --- V1 -> V2: revised dts property name for clock(s) V1 -> V2: implemented all 6 bits in the clock configuration register drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 5ce6da62cc8e..e7150a8e34d2 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -99,6 +99,15 @@ #define ADIN1300_GE_SOFT_RESET_REG 0xff0c #define ADIN1300_GE_SOFT_RESET BIT(0) +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) +#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) +#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) +#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) +#define ADIN1300_GE_CLK_CFG_25 BIT(0) + #define ADIN1300_GE_RGMII_CFG_REG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -433,6 +442,37 @@ static int adin_set_tunable(struct phy_device *phydev, } } +static int adin_config_clk_out(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const char *val = 0; + u8 sel = 0; + + device_property_read_string(dev, "adi,phy-output-clock", &val); + if(!val) { + /* property not present, do not enable GP_CLK pin */ + } else if(strcmp(val, "25mhz-reference") == 0) { + sel |= ADIN1300_GE_CLK_CFG_25; + } else if(strcmp(val, "125mhz-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if(strcmp(val, "125mhz-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_RCVR_125; + } else if(strcmp(val, "adaptive-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; + } else if(strcmp(val, "adaptive-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_RCVR; + } else { + phydev_err(phydev, "invalid adi,phy-output-clock\n"); + return -EINVAL; + } + + if(device_property_read_bool(dev, "adi,phy-output-reference-clock")) + sel |= ADIN1300_GE_CLK_CFG_REF_EN; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK, sel); +} + static int adin_config_init(struct phy_device *phydev) { int rc; @@ -455,6 +495,10 @@ static int adin_config_init(struct phy_device *phydev) if (rc < 0) return rc; + rc = adin_config_clk_out(phydev); + if (rc < 0) + return rc; + phydev_dbg(phydev, "PHY is using mode '%s'\n", phy_modes(phydev->interface)); From patchwork Tue Apr 19 10:27:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12817732 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A9D7C433EF for ; Tue, 19 Apr 2022 10:27:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242238AbiDSKaX (ORCPT ); Tue, 19 Apr 2022 06:30:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242232AbiDSKaQ (ORCPT ); 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[82.81.222.124]) by smtp.gmail.com with ESMTPSA id m4-20020a7bcb84000000b00389efb7a5b4sm19036166wmi.17.2022.04.19.03.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 03:27:31 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Russell King , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Subject: [PATCH v2 3/3] ARM: dts: imx6qdl-sr-som: update phy configuration for som revision 1.9 Date: Tue, 19 Apr 2022 13:27:09 +0300 Message-Id: <20220419102709.26432-4-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220419102709.26432-1-josua@solid-run.com> References: <20220410104626.11517-1-josua@solid-run.com> <20220419102709.26432-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since SoM revision 1.9 the PHY has been replaced with an ADIN1300, add an entry for it next to the original. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- V1 -> V2: changed dts property name arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index f86efd0ccc40..d46182095d79 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -83,6 +83,12 @@ ethernet-phy@4 { qca,clk-out-frequency = <125000000>; qca,smarteee-tw-us-1g = <24>; }; + + /* ADIN1300 (som rev 1.9 or later) */ + ethernet-phy@1 { + reg = <1>; + adi,phy-output-clock = "125mhz-free-running"; + }; }; };