From patchwork Thu Apr 21 21:15:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Collingbourne X-Patchwork-Id: 12822432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AEC1C433EF for ; Thu, 21 Apr 2022 21:16:17 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id C2CE36B0072; Thu, 21 Apr 2022 17:16:16 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id BDA626B0073; Thu, 21 Apr 2022 17:16:16 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id A2E1F6B0074; Thu, 21 Apr 2022 17:16:16 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (relay.hostedemail.com [64.99.140.25]) by kanga.kvack.org (Postfix) with ESMTP id 8C9726B0072 for ; Thu, 21 Apr 2022 17:16:16 -0400 (EDT) Received: from smtpin08.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id BD709637BB for ; Thu, 21 Apr 2022 21:16:15 +0000 (UTC) X-FDA: 79382144310.08.4D22441 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) by imf05.hostedemail.com (Postfix) with ESMTP id 86674100023 for ; Thu, 21 Apr 2022 21:16:12 +0000 (UTC) Received: by mail-yb1-f202.google.com with SMTP id e4-20020a056902034400b00633691534d5so5433001ybs.7 for ; Thu, 21 Apr 2022 14:16:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:message-id:mime-version:subject:from:to:cc; bh=03Z+idmGJ7XYtJB1gQOW/umO4Zo4sumIH09aShWkJ9I=; b=LBvXnMLK349yjo1R4H/wwtNGKmobyGYcL9HPZBu/cXGY3WKeklqbL03V7SFi7SES4C JIO7i/BJUB8GTj7HSsw0VRvVLWgIwVh0goXXUL0tu3YIfClzNAxJ/rpdLjMctrBG1jy0 wmC08ZKFQlZwdvQKQX43pSHGDp3wXv5kWMNylRojhzIlHf6GNjk5YIoa0M3DY7QR6sOb 30qNpIWEOp/mbxDqAsEtILtSMFf7afz5IU0ib9aU51XZtPtelRG37SrJ6jBsAX4GKbWV OZvGIPqjT/4ef/dTyCtyxJStMXqcIFljYCAPtu5cU75GgU5pkPR5LbNguX546sqQFztv tHzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=03Z+idmGJ7XYtJB1gQOW/umO4Zo4sumIH09aShWkJ9I=; b=s+CEIkIjrlQ7TGwyihZ6dviUeS5j52REOQOXLYzr2rr9D+P+Jla6n0Uxqugqx8fU8n PsK8cQDguLpTua/dD8M4kOaKDra2M0h4FhUMC0e+kTdbJywrik1LCAD479Phk68JqGMZ XDi+R5f7ljxD8kRpkDdhpzAbJZeWTYgFNsg30KeEKmUsK4j88zqA2Ox2bssqD7x41nsf szmSGzMJF729WGyhIwp0bma4zEZdFt/841La5KJTPwp626C/qMjwYOgk3E4J/Zwzw5nu 3TwMJdpBplEZ2MsnzseEr4vR7uIF1JrkKy6UPed4g0CE7PFH2kCChJbOIbN1DkW0GjRx kAMQ== X-Gm-Message-State: AOAM532JCzwS+/77DN8OfyLDkj5g1islZhmERtu90Od/ZvDTXhaVgi8f WbLzeJpJa75e6yk+KIfZhhDKd/Y= X-Google-Smtp-Source: ABdhPJwic3t+v5vZKGRRxcksNDXzgfwL+19tUS7vpYz1ijbUbwL0ODiltD3WDPaWuxBihGJtA0Q9xl0= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:38c6:db53:1479:afb0]) (user=pcc job=sendgmr) by 2002:a81:650:0:b0:2f4:cc5b:c510 with SMTP id 77-20020a810650000000b002f4cc5bc510mr1747612ywg.113.1650575774393; Thu, 21 Apr 2022 14:16:14 -0700 (PDT) Date: Thu, 21 Apr 2022 14:15:48 -0700 Message-Id: <20220421211549.3884453-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.36.0.rc2.479.g8af0fa9b8e-goog Subject: [PATCH v2] mm: make minimum slab alignment a runtime property From: Peter Collingbourne To: Andrey Konovalov , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Andrew Morton , Catalin Marinas Cc: Peter Collingbourne , Linux ARM , Linux Memory Management List , Linux Kernel Mailing List , vbabka@suse.cz, penberg@kernel.org, roman.gushchin@linux.dev, iamjoonsoo.kim@lge.com, rientjes@google.com, Herbert Xu , Andrey Ryabinin , Alexander Potapenko , Dmitry Vyukov , kasan-dev , Eric Biederman , Kees Cook X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 86674100023 X-Rspam-User: Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=google.com header.s=20210112 header.b=LBvXnMLK; dmarc=pass (policy=reject) header.from=google.com; spf=pass (imf05.hostedemail.com: domain of 3nslhYgMKCNECzz3BB381.zB985AHK-997Ixz7.BE3@flex--pcc.bounces.google.com designates 209.85.219.202 as permitted sender) smtp.mailfrom=3nslhYgMKCNECzz3BB381.zB985AHK-997Ixz7.BE3@flex--pcc.bounces.google.com X-Stat-Signature: e5hcao7eeiiof4d1xgpr7jwx631irtfp X-HE-Tag: 1650575772-918327 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: When CONFIG_KASAN_HW_TAGS is enabled we currently increase the minimum slab alignment to 16. This happens even if MTE is not supported in hardware or disabled via kasan=off, which creates an unnecessary memory overhead in those cases. Eliminate this overhead by making the minimum slab alignment a runtime property and only aligning to 16 if KASAN is enabled at runtime. On a DragonBoard 845c (non-MTE hardware) with a kernel built with CONFIG_KASAN_HW_TAGS, waiting for quiescence after a full Android boot I see the following Slab measurements in /proc/meminfo (median of 3 reboots): Before: 169020 kB After: 167304 kB Link: https://linux-review.googlesource.com/id/I752e725179b43b144153f4b6f584ceb646473ead Signed-off-by: Peter Collingbourne Reviewed-by: Andrey Konovalov --- v2: - use max instead of max_t in flat_stack_align() arch/arc/include/asm/cache.h | 4 ++-- arch/arm/include/asm/cache.h | 2 +- arch/arm64/include/asm/cache.h | 19 +++++++++++++------ arch/microblaze/include/asm/page.h | 2 +- arch/riscv/include/asm/cache.h | 2 +- arch/sparc/include/asm/cache.h | 2 +- arch/xtensa/include/asm/processor.h | 2 +- fs/binfmt_flat.c | 9 ++++++--- include/crypto/hash.h | 2 +- include/linux/slab.h | 22 +++++++++++++++++----- mm/slab.c | 7 +++---- mm/slab_common.c | 3 +-- mm/slob.c | 6 +++--- 13 files changed, 51 insertions(+), 31 deletions(-) diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index f0f1fc5d62b6..b6a7763fd5d6 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -55,11 +55,11 @@ * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit * alignment for any atomic64_t embedded in buffer. - * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed + * Default ARCH_SLAB_MIN_MINALIGN is __alignof__(long long) which has a relaxed * value of 4 (and not 8) in ARC ABI. */ #if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC) -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_SLAB_MIN_MINALIGN 8 #endif extern int ioc_enable; diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index e3ea34558ada..3e1018bb9805 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -21,7 +21,7 @@ * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. */ #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_SLAB_MIN_MINALIGN 8 #endif #define __read_mostly __section(".data..read_mostly") diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index a074459f8f2f..38f171591c3f 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -6,6 +6,7 @@ #define __ASM_CACHE_H #include +#include #define CTR_L1IP_SHIFT 14 #define CTR_L1IP_MASK 3 @@ -49,15 +50,21 @@ */ #define ARCH_DMA_MINALIGN (128) -#ifdef CONFIG_KASAN_SW_TAGS -#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) -#elif defined(CONFIG_KASAN_HW_TAGS) -#define ARCH_SLAB_MINALIGN MTE_GRANULE_SIZE -#endif - #ifndef __ASSEMBLY__ #include +#include + +#ifdef CONFIG_KASAN_SW_TAGS +#define ARCH_SLAB_MIN_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) +#elif defined(CONFIG_KASAN_HW_TAGS) +static inline size_t arch_slab_minalign(void) +{ + return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE : + __alignof__(unsigned long long); +} +#define arch_slab_minalign() arch_slab_minalign() +#endif #define ICACHEF_ALIASING 0 #define ICACHEF_VPIPT 1 diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h index 4b8b2fa78fc5..ccdbc1da3c3e 100644 --- a/arch/microblaze/include/asm/page.h +++ b/arch/microblaze/include/asm/page.h @@ -33,7 +33,7 @@ /* MS be sure that SLAB allocates aligned objects */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES -#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MIN_MINALIGN L1_CACHE_BYTES /* * PAGE_OFFSET -- the first address of the first page of memory. With MMU diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b104559e..7beb3b5d27c7 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -16,7 +16,7 @@ * the flat loader aligns it accordingly. */ #ifndef CONFIG_MMU -#define ARCH_SLAB_MINALIGN 16 +#define ARCH_SLAB_MIN_MINALIGN 16 #endif #endif /* _ASM_RISCV_CACHE_H */ diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index e62fd0e72606..9d8cb4687b7e 100644 --- a/arch/sparc/include/asm/cache.h +++ b/arch/sparc/include/asm/cache.h @@ -8,7 +8,7 @@ #ifndef _SPARC_CACHE_H #define _SPARC_CACHE_H -#define ARCH_SLAB_MINALIGN __alignof__(unsigned long long) +#define ARCH_SLAB_MIN_MINALIGN __alignof__(unsigned long long) #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES 32 diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h index 4489a27d527a..e3ea278e3fcf 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -18,7 +18,7 @@ #include #include -#define ARCH_SLAB_MINALIGN XTENSA_STACK_ALIGNMENT +#define ARCH_SLAB_MIN_MINALIGN XTENSA_STACK_ALIGNMENT /* * User space process size: 1 GB. diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c index 626898150011..23ce3439eafa 100644 --- a/fs/binfmt_flat.c +++ b/fs/binfmt_flat.c @@ -64,7 +64,10 @@ * Here we can be a bit looser than the data sections since this * needs to only meet arch ABI requirements. */ -#define FLAT_STACK_ALIGN max_t(unsigned long, sizeof(void *), ARCH_SLAB_MINALIGN) +static size_t flat_stack_align(void) +{ + return max(sizeof(void *), arch_slab_minalign()); +} #define RELOC_FAILED 0xff00ff01 /* Relocation incorrect somewhere */ #define UNLOADED_LIB 0x7ff000ff /* Placeholder for unused library */ @@ -148,7 +151,7 @@ static int create_flat_tables(struct linux_binprm *bprm, unsigned long arg_start sp -= 2; /* argvp + envp */ sp -= 1; /* &argc */ - current->mm->start_stack = (unsigned long)sp & -FLAT_STACK_ALIGN; + current->mm->start_stack = (unsigned long)sp & -flat_stack_align(); sp = (unsigned long __user *)current->mm->start_stack; if (put_user(bprm->argc, sp++)) @@ -966,7 +969,7 @@ static int load_flat_binary(struct linux_binprm *bprm) #endif stack_len += (bprm->argc + 1) * sizeof(char *); /* the argv array */ stack_len += (bprm->envc + 1) * sizeof(char *); /* the envp array */ - stack_len = ALIGN(stack_len, FLAT_STACK_ALIGN); + stack_len = ALIGN(stack_len, flat_stack_align()); res = load_flat_file(bprm, &libinfo, 0, &stack_len); if (res < 0) diff --git a/include/crypto/hash.h b/include/crypto/hash.h index f140e4643949..442c290f458c 100644 --- a/include/crypto/hash.h +++ b/include/crypto/hash.h @@ -149,7 +149,7 @@ struct ahash_alg { struct shash_desc { struct crypto_shash *tfm; - void *__ctx[] __aligned(ARCH_SLAB_MINALIGN); + void *__ctx[] __aligned(ARCH_SLAB_MIN_MINALIGN); }; #define HASH_MAX_DIGESTSIZE 64 diff --git a/include/linux/slab.h b/include/linux/slab.h index 373b3ef99f4e..80e517593372 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -201,21 +201,33 @@ void kmem_dump_obj(void *object); #endif /* - * Setting ARCH_SLAB_MINALIGN in arch headers allows a different alignment. + * Setting ARCH_SLAB_MIN_MINALIGN in arch headers allows a different alignment. * Intended for arches that get misalignment faults even for 64 bit integer * aligned buffers. */ -#ifndef ARCH_SLAB_MINALIGN -#define ARCH_SLAB_MINALIGN __alignof__(unsigned long long) +#ifndef ARCH_SLAB_MIN_MINALIGN +#define ARCH_SLAB_MIN_MINALIGN __alignof__(unsigned long long) +#endif + +/* + * Arches can define this function if they want to decide the minimum slab + * alignment at runtime. The value returned by the function must be + * >= ARCH_SLAB_MIN_MINALIGN. + */ +#ifndef arch_slab_minalign +static inline size_t arch_slab_minalign(void) +{ + return ARCH_SLAB_MIN_MINALIGN; +} #endif /* * kmalloc and friends return ARCH_KMALLOC_MINALIGN aligned - * pointers. kmem_cache_alloc and friends return ARCH_SLAB_MINALIGN + * pointers. kmem_cache_alloc and friends return ARCH_SLAB_MIN_MINALIGN * aligned pointers. */ #define __assume_kmalloc_alignment __assume_aligned(ARCH_KMALLOC_MINALIGN) -#define __assume_slab_alignment __assume_aligned(ARCH_SLAB_MINALIGN) +#define __assume_slab_alignment __assume_aligned(ARCH_SLAB_MIN_MINALIGN) #define __assume_page_alignment __assume_aligned(PAGE_SIZE) /* diff --git a/mm/slab.c b/mm/slab.c index 0edb474edef1..97b756976c8b 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -3009,10 +3009,9 @@ static void *cache_alloc_debugcheck_after(struct kmem_cache *cachep, objp += obj_offset(cachep); if (cachep->ctor && cachep->flags & SLAB_POISON) cachep->ctor(objp); - if (ARCH_SLAB_MINALIGN && - ((unsigned long)objp & (ARCH_SLAB_MINALIGN-1))) { - pr_err("0x%px: not aligned to ARCH_SLAB_MINALIGN=%d\n", - objp, (int)ARCH_SLAB_MINALIGN); + if ((unsigned long)objp & (arch_slab_minalign() - 1)) { + pr_err("0x%px: not aligned to arch_slab_minalign()=%d\n", objp, + (int)arch_slab_minalign()); } return objp; } diff --git a/mm/slab_common.c b/mm/slab_common.c index 2b3206a2c3b5..33cc49810a54 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -154,8 +154,7 @@ static unsigned int calculate_alignment(slab_flags_t flags, align = max(align, ralign); } - if (align < ARCH_SLAB_MINALIGN) - align = ARCH_SLAB_MINALIGN; + align = max_t(size_t, align, arch_slab_minalign()); return ALIGN(align, sizeof(void *)); } diff --git a/mm/slob.c b/mm/slob.c index 40ea6e2d4ccd..3bd2669bd690 100644 --- a/mm/slob.c +++ b/mm/slob.c @@ -478,7 +478,7 @@ static __always_inline void * __do_kmalloc_node(size_t size, gfp_t gfp, int node, unsigned long caller) { unsigned int *m; - int minalign = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN); + int minalign = max_t(size_t, ARCH_KMALLOC_MINALIGN, arch_slab_minalign()); void *ret; gfp &= gfp_allowed_mask; @@ -555,7 +555,7 @@ void kfree(const void *block) sp = virt_to_folio(block); if (folio_test_slab(sp)) { - int align = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN); + int align = max_t(size_t, ARCH_KMALLOC_MINALIGN, arch_slab_minalign()); unsigned int *m = (unsigned int *)(block - align); slob_free(m, *m + align); } else { @@ -584,7 +584,7 @@ size_t __ksize(const void *block) if (unlikely(!folio_test_slab(folio))) return folio_size(folio); - align = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN); + align = max_t(size_t, ARCH_KMALLOC_MINALIGN, arch_slab_minalign()); m = (unsigned int *)(block - align); return SLOB_UNITS(*m) * SLOB_UNIT; }