From patchwork Mon Apr 25 09:52:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12825527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59AE6C433F5 for ; Mon, 25 Apr 2022 09:54:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uRLG7qtDtjQix5XDQBTuTeyJrpRM648oyA6gaESxk7c=; b=u4AVorgnDeADcE IIQ7gY6JQoCXlnt2cgnUc5wVat015yzZ0bdpvnSQR/LAdoOKZwTprVXck8bS5n1pP5Ul3+JR8zAdc wwadnjWNoYv/k6n+4xHugKyVov3JGh3CNU5kPj5UtYVtYZhcaeAS8hH7fuqwRoC9jPUKNu0pLNDiA x5aDsbWYTKtlx3B2sgLh52VAlmr+QAhnaI30yxq+UCylPF+RX0at8/EuJQOPTMmYQNyDL6lk/AKkE 5+ahAepkHh7ZxF4W9/S9ZBI8fM9QH2ffvovSlNQ6gaazxlEovpgnxQhZOIPx2HCi74DAE34/barep 9UR8JcjpMO8E0A5vNPtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nivPC-008zoH-Um; Mon, 25 Apr 2022 09:53:19 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nivP0-008zlM-Lm for linux-arm-kernel@lists.infradead.org; Mon, 25 Apr 2022 09:53:09 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nivOn-0008Mo-Ji; Mon, 25 Apr 2022 11:52:53 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nivOo-0057Ws-93; Mon, 25 Apr 2022 11:52:52 +0200 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nivOm-0015Vq-2S; Mon, 25 Apr 2022 11:52:52 +0200 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Stephen Boyd , Shawn Guo , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, David Jander , Sascha Hauer Subject: [PATCH 1/2] clk: imx8mp: Enable no longer handled gates Date: Mon, 25 Apr 2022 11:52:48 +0200 Message-Id: <20220425095249.259406-2-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220425095249.259406-1-s.hauer@pengutronix.de> References: <20220425095249.259406-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_025306_745364_5FE2E2F9 X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL was removed in d097cc045b649. We shouldn't assume these gates are at their reset-default enabled state. Enable them to let the kernel work when the bootloader has changed the values. Fixes: d097cc045b649 ("clk: imx8mp: remove SYS PLL 1/2 clock gates") Reported-by: David Jander Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx8mp.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 18f5b7c3ca9d8..10446a1b509e7 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -407,6 +407,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np; void __iomem *anatop_base, *ccm_base; + u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); anatop_base = of_iomap(np, 0); @@ -480,6 +481,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11); hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11); + /* + * The gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL are not handled by the + * driver, make sure they are all enabled. + */ + val = readl(anatop_base + 0x94); + val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) | + BIT(25) | BIT(27); + writel(val, anatop_base + 0x94); + hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); @@ -494,6 +504,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); + /* + * The gates in CCM_ANALOG_SYS_PLL2_GEN_CTRL are not handled by the + * driver, make sure they are all enabled. + */ + val = readl(anatop_base + 0x104); + val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) | + BIT(25) | BIT(27); + writel(val, anatop_base + 0x104); + hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); From patchwork Mon Apr 25 09:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12825528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C4BDC433F5 for ; Mon, 25 Apr 2022 09:54:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 25 Apr 2022 11:52:53 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nivOo-0057Wv-DZ; Mon, 25 Apr 2022 11:52:52 +0200 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nivOm-0015Vt-3C; Mon, 25 Apr 2022 11:52:52 +0200 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Stephen Boyd , Shawn Guo , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, David Jander , Sascha Hauer Subject: [PATCH 2/2] clk: imx8mq: Enable no longer handled gates Date: Mon, 25 Apr 2022 11:52:49 +0200 Message-Id: <20220425095249.259406-3-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220425095249.259406-1-s.hauer@pengutronix.de> References: <20220425095249.259406-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_025306_857854_48423B4F X-CRM114-Status: GOOD ( 13.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL was removed in c586f53ae159c. We shouldn't assume these gates are at their reset-default enabled state. Enable them to let the kernel work when the bootloader has changed the values. Fixes: c586f53ae159c ("clk: imx8mq: remove SYS PLL 1/2 clock gates") Reported-by: David Jander Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx8mq.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 83cc2b1c32947..55b72ff0c6a41 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -286,6 +286,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; void __iomem *base; + u32 val; int err; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, @@ -357,6 +358,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws[IMX8MQ_DRAM_PLL_OUT] = imx_clk_hw_sscg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); + /* + * The gates in CCM_ANALOG_SYS_PLL_CFG0 are not handled by the driver, + * make sure they are all enabled. + */ + val = readl(base + 0x30); + val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) | + BIT(21) | BIT(23) | BIT(25); + writel(val, base + 0x30); + /* SYS PLL1 fixed output */ hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20); hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10); @@ -368,6 +378,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2); hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1); + /* + * The gates in CCM_ANALOG_SYS_PLL2_CFG0 are not handled by the driver, + * make sure they are all enabled. + */ + val = readl(base + 0x3c); + val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) | + BIT(21) | BIT(23) | BIT(25); + writel(val, base + 0x3c); + /* SYS PLL2 fixed output */ hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20); hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);