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(dynamic-2a01-0c22-7b47-9400-3041-ad82-4e56-6dd5.c22.pool.telefonica.de. [2a01:c22:7b47:9400:3041:ad82:4e56:6dd5]) by smtp.googlemail.com with ESMTPSA id x19-20020a05640226d300b004228faf83desm5339141edd.12.2022.04.25.13.39.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Apr 2022 13:39:42 -0700 (PDT) Message-ID: Date: Mon, 25 Apr 2022 22:39:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Content-Language: en-US To: Neil Armstrong , Yu Tu Cc: "open list:ARM/Amlogic Meson..." From: Heiner Kallweit Subject: [PATCH RFC] tty: serial: meson: add new compatible for gxl uart X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_133944_802366_14ABA82B X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org My SC2 test system (ah212-based HK1 RBOX X4) uses an uboot console speed of 921600 bps. Being able to use the same speed in Linux requires using a 12MHz clock source. Ideally we'd set the new compatible to the first chip version supporting the AML_UART_BAUD_XTAL_DIV2 bit. Not having access to chip documentation I'd appreciate a hint on when this bit was introduced. If fine with you in general the final series would include a separate patch for the new compatible. Note: This patch doesn't consider "tty: serial: meson: Use DIV_ROUND_CLOSEST to calculate baud rates" yet and therefore won't apply cleanly on linux-next. I locally used the same DIV_ROUND_CLOSEST() changes before. ---------------------------------------------------------------- Newer SoC versions support using XTAL / 2 (12MHz) as clock source for the UART. This clock source allows to support 921600 bps as used by vendor uboot on certain systems like ah212 ref board. 12MHz / 13 = 923076 bps With the currently used 8MHz clock source only 888888bps or 1000000 bps are possible. Signed-off-by: Heiner Kallweit --- drivers/tty/serial/meson_uart.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 2bf1c57e0..0a0a0636f 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -68,6 +68,7 @@ #define AML_UART_BAUD_MASK 0x7fffff #define AML_UART_BAUD_USE BIT(23) #define AML_UART_BAUD_XTAL BIT(24) +#define AML_UART_BAUD_XTAL_DIV2 BIT(27) #define AML_UART_PORT_NUM 12 #define AML_UART_PORT_OFFSET 6 @@ -299,10 +300,15 @@ static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) cpu_relax(); if (port->uartclk == 24000000) { - val = ((port->uartclk / 3) / baud) - 1; - val |= AML_UART_BAUD_XTAL; + if (of_device_is_compatible(port->dev->of_node, "amlogic,meson-gxl-uart")) { + val = DIV_ROUND_CLOSEST(port->uartclk, 2 * baud) - 1; + val |= AML_UART_BAUD_XTAL | AML_UART_BAUD_XTAL_DIV2; + } else { + val = DIV_ROUND_CLOSEST(port->uartclk, 3 * baud) - 1; + val |= AML_UART_BAUD_XTAL; + } } else { - val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; + val = DIV_ROUND_CLOSEST(port->uartclk, 4 * baud) - 1; } val |= AML_UART_BAUD_USE; writel(val, port->membase + AML_UART_REG5); @@ -782,6 +788,7 @@ static const struct of_device_id meson_uart_dt_match[] = { { .compatible = "amlogic,meson8-uart" }, { .compatible = "amlogic,meson8b-uart" }, { .compatible = "amlogic,meson-gx-uart" }, + { .compatible = "amlogic,meson-gxl-uart" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, meson_uart_dt_match);