From patchwork Tue Apr 26 18:52:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12827799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 980C5C433FE for ; Tue, 26 Apr 2022 18:53:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=suff1Jpj1LXRIuVQmSO/caSz3KtYHjJ61b0JTyJ4h9c=; b=y/Pyts4kRR2ahI Tv14SvEyXE+No5bDy3WSD/c/zJryERcEzQha+CwZjNtADMFKACdCxtiXkujDhtgN4SpV781X1CUep 1QvU5uUaMWBWvI6mD1/qM64JCpOGNUSGWDJdpKWaFPGc60JPhCi8HU8uX13yvbVhhlE0Cq4LcqXym SRUj4QWboapXrluSrTmtWLqCK0+hHJIDPpIfxXbiEfEN+jQD/eDmUBt05vfzD+2loRc0hWfEgGi7X Rp7DZiwtiDHaRhkjgzhAD798j5Fs9/yqeh6lISVfxTvUASM1GQs/S5x6LgMSRYSjGcjU6avseeesR 7dxJ4DSxga5NsritKPlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJQ-00FrFE-9U; Tue, 26 Apr 2022 18:53:24 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJB-00Fr7R-QP for linux-riscv@lists.infradead.org; Tue, 26 Apr 2022 18:53:11 +0000 Received: by mail-pj1-x102d.google.com with SMTP id e24so2372716pjt.2 for ; Tue, 26 Apr 2022 11:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Abl0bfYYrLlQ27vYh6a3IKNxFiISaIZQZeWkMU0B+HY=; b=vBrOC+clk/14uoGOtUn6c44gW3HFg6+QeB4YEt2tbdI3Rg4yeq77I+oddnQCUvlydX iqg0VvE+xjRD4sWxZ1mmoMfRyrVxDPrUtXKkDrNRWGiibUU5SffVNYDCOpqXJjxDdfm+ /rqFvZzeeyDfpQ76ca7H7LzTLOeXPvHCD/pCuz5pOO8kXPjiAwdv46d+k1hN/PFWNd+S LE/PYTA7+dKF64/xYYMYdLWJgicaGpcdpGKTGGfp30OgMWLTSJq6OCxzp2iLWkNNeiSk DE2Xcjq/QTbTVXOE/59QHyVR17aRUr04hI760rCpzv0eJ487aQJHQthEkwcuJ3xj55vm C22Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Abl0bfYYrLlQ27vYh6a3IKNxFiISaIZQZeWkMU0B+HY=; b=F1gPrpMHfwLG+8mQ2bNT9YpV2ta7rArqEWyvFr7cYvzsR3XAINfEi4Mq4t0tutXV8Y Gcq5MB37rKNXu5m+cCAdCK/rc7moalWcf90h7cgrQdiJ9b36LG3qjb2smsr46wxV9Nkv uWohJxPn7FvDnOeixHGL1OfcS9TESAsqcgPcfDkIzmHXe9BpSM4o8PbZSg2JEIQDFkKA +iqQd/HeFQAE+aSLaL8ZRA01/hLPpTdQcpexGt1FNI0Gs5+K/D1TfNE8aOC45R0NMuYq qvJJ1ZVCwjNxe0KH4D6zEXnPGP2Ap1ieSnY/gJiDeNoEApEVVAQHmQNBjDqh4Y02ftIA 8Dmw== X-Gm-Message-State: AOAM530awEyHC8Kp/MJk8UVqGOt1FNDl6xFQEd2pRylfS/j0x3uqhOZL ywPM2EmhH+yhaukaPMAfmIuxOw== X-Google-Smtp-Source: ABdhPJx/bBDnaGbhRf26Abl87DpdzPlrl9/ustlrU9hsLHOANPcCs60CUmoMIuPL0ZgfMH86wSd+tw== X-Received: by 2002:a17:90a:884:b0:1d9:531c:9cd6 with SMTP id v4-20020a17090a088400b001d9531c9cd6mr16498367pjc.211.1650999188661; Tue, 26 Apr 2022 11:53:08 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id cl18-20020a17090af69200b001cd4989ff5asm3839664pjb.33.2022.04.26.11.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 11:53:08 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 1/4] RISC-V: Add SSTC extension CSR details Date: Tue, 26 Apr 2022 11:52:42 -0700 Message-Id: <20220426185245.281182-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426185245.281182-1-atishp@rivosinc.com> References: <20220426185245.281182-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_115309_906432_3706B3B6 X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch just introduces the required CSR fields related to the SSTC extension. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/csr.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index e935f27b10fd..10f4e1c36908 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -227,6 +227,9 @@ #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 #define CSR_VSTVEC 0x205 @@ -236,6 +239,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -251,6 +256,8 @@ #define CSR_HTINST 0x64a #define CSR_HGATP 0x680 #define CSR_HGEIP 0xe12 +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 @@ -312,6 +319,10 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) +/* ENVCFG related bits */ +#define HENVCFG_STCE 63 +#define HENVCFGH_STCE 31 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ From patchwork Tue Apr 26 18:52:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12827800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB937C433F5 for ; Tue, 26 Apr 2022 18:53:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8wpvFwn7jZeab3FqSP/53O7w3KCzk/pNVwC2cABgVaI=; b=EHasqMb7FPUOze 1FhVbS+f441lzIYFRI67Ai47ExNC/yVUbtS6HtnD20TkbPeENdr5gEKiapx1OAUhlm1ZQFtxQbHHB OFPWjysV1O8zicdASFXfxsS4T+2QlI3Ruo3QEvgdZ47qDcqpb7Bee6SIADMAgUZ/mxRt0MLGEJqv1 67ITwj6wj7w5vznXNktvFMdGQizr0DeODZtQ7fVxbQZFUVxzJcGN0lYUvZsHtXekKtfwMSgLbSyY1 XfHOejA/m8xrYGqL0s8K3/aXWhRPomYPK9MYmkuBLvzBDpHyMtu5N5fkpfumeIBx56c9oGnc551Sx vYtuk9JmntsptVZKgv2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJS-00FrGf-FF; Tue, 26 Apr 2022 18:53:26 +0000 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJD-00Fr8H-B3 for linux-riscv@lists.infradead.org; Tue, 26 Apr 2022 18:53:13 +0000 Received: by mail-pl1-x62a.google.com with SMTP id d15so16635737plh.2 for ; Tue, 26 Apr 2022 11:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KslgnjbYCZy+RC57ZlL0pYo5UT2utIjDNcmnyodLbb4=; b=mlb9fCc5rb7zG7mTZaJ0VEWPjisdXFLSvYf5s+ONK4bMBESNNjkC9LspUvLeDIH7qg KJWqNCNtmrDhGwSK8WWziE2vvMlKPHdrhOkxTNKqVrH4bzYAGPS3JOAcgn9uJq2U7GIc rqsSRnlpOfMuOq6EQMF6XQB3zL1qkroK77mrAmkPgolCGxAEvrggowjCIMTKALEz7O5L T0apibn7Lov23G7OW7GMaHKpIMQhO9kHaeUhCdh6NwztivMdV78PW8DemC/NYlrXYNCa Tbvw8tsT61VlPxpax/4JEuuCl543oeV9N3N8bh+s/UR7NZ4AcjNRTV5pmDrO2xmEU0Yu 0vVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KslgnjbYCZy+RC57ZlL0pYo5UT2utIjDNcmnyodLbb4=; b=BlwYVEq8l/94vAmdYVt/hD5/Bt4ikZoFo/IYyiUY+a/dE1ipEiQ3kwVuRHkROOk/fk 7LKRl+WsHtblDeIXyFCvbSGHlZB79g9xvjAsO24WUF0plV/QZYO6rJfMgtjChfdP0ZA+ inOA7iFsFTR8bYaHfbNA6aLz6/uF3/zJ5tVxd7SqMUBGpPDXwGzo0I37ZFo7JGesD7/Z qDJdwSrJQOyUG7KNm3n67uRKx8nMS12o5k+ZRX8M2n7nN+H/+6bl/PFizBepaW+p9Yix O1UwTeA90aPugrOX1KQIWktAdjqxLqavj9U3JwJBZ2x1emkeYgbS0AqwVGW6ZMMBiB8W wAwA== X-Gm-Message-State: AOAM530LIFEl2YI7z/rPsmfgmac00S0jmLbIdfHXlknojeGAdraw5tEe OPwbSuBudUkTD9IzNJD0U4aRcg== X-Google-Smtp-Source: ABdhPJydAWW3DEffEILPWDD4OW996Ze0tqBY9UvoB/z8q/qtxrBuRCzG4CK+M8gIY/YrqzWEtsn8HQ== X-Received: by 2002:a17:902:d645:b0:158:f267:83b1 with SMTP id y5-20020a170902d64500b00158f26783b1mr25064870plh.11.1650999190315; Tue, 26 Apr 2022 11:53:10 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id cl18-20020a17090af69200b001cd4989ff5asm3839664pjb.33.2022.04.26.11.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 11:53:09 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 2/4] RISC-V: Enable sstc extension parsing from DT Date: Tue, 26 Apr 2022 11:52:43 -0700 Message-Id: <20220426185245.281182-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426185245.281182-1-atishp@rivosinc.com> References: <20220426185245.281182-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_115311_398137_3B6EC648 X-CRM114-Status: GOOD ( 10.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The ISA extension framework now allows parsing any multi-letter ISA extension. Enable that for sstc extension. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0734e42f74f2..25915eb60d61 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; */ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..ca0e4c0db17e 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) */ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..a214537c22f1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void) set_bit(*ext - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); } #undef SET_ISA_EXT_MAP } From patchwork Tue Apr 26 18:52:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12827802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 092F4C433EF for ; Tue, 26 Apr 2022 18:53:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=G3QlARXyZRaGf9fUMzROUyUaioiVg+RGRGZ8gpFvQY8=; b=eezunzXv9fHaIS eY20MxFsLcyr6FLEXaZXeTW2hLymFlED7bqR9CbtXds3MeQ2twrw7r/WJyIEp/JWe9fInBQd2tERx rl+N39xGy0zYRTcVhhJvrT5EGmi1u03XlCQ2SA9lFTOJnrbKstZnuh5IGoQCCEY8wdq5SIyMcwzQa wJ8nf2wxYkprgk/t0mHSP26/NgEcQXFvo/7vP2MzIVrzlbwnnuZ228ajLU+8SKRgdLoVkeOu5bXIc i5vAOWfcvl0FElKWJ/r1sNCw3izToh6KkjCwIT5TrYbRisoZ9y5O+xVv5vpAHwmz0d8iYT9EfOePy 2I0Zv3ioqGHZ2EpqcJaw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJV-00FrIs-6j; Tue, 26 Apr 2022 18:53:29 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJF-00Fr9g-JR for linux-riscv@lists.infradead.org; Tue, 26 Apr 2022 18:53:15 +0000 Received: by mail-pj1-x102b.google.com with SMTP id t11-20020a17090ad50b00b001d95bf21996so2953741pju.2 for ; Tue, 26 Apr 2022 11:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D+SXwT/SJ1BJbq87GGWyit7MKCT0yhEbjDVEHkS9JaY=; b=Z9GOxXKVlrR5xV0gHPbY+4kKmmF1WY+8H+M9B0psxISWmGz2FVgBqU9huy3KkQTC3V 6bFgG7obRq96JTn8NkAYyml28WP2VHD9d/+A+rqpT96V3DLLPpHwRV7XeeOkj+s25kx6 TJ4Holc+whFhjUX0Gsmza/Wzb7jz00dboknTTWY0oha7C2dcZuPhkqMuEnqlYWWH1lIX Juuy8ObgdDHPqRAFmGp5wCC1zlYuYDF+W2W+m+2TcowHRc+yRIheJtG0+PlOyAy8aJpY JXrUdgOc6WjB5VwDUBExmoEkoLEcmbh79m5h5PksiZ62NmruVMZRl2dokqfkj2USAktx mZkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D+SXwT/SJ1BJbq87GGWyit7MKCT0yhEbjDVEHkS9JaY=; b=P2Vyk8nsHlj0zx4r0vUOu2NqphHem5yM+FPpZLOKakjKZp7xRcu76fw6R65OCrkj1L x5XbjAP5dKkOLd9ntjVBX+vO/6U/5dp8rC7US1AnBG/ioiEzRKLEdJWAHAVWoXf1D5Td zSUBZcU3o+VVr0YV8MQnrbGPLaeyf14u8dA+fev6Lb9ekdxAoM/uYqGJsQIm+35Rf8/+ nryPXu6ASRqsvIClzqr4HoQt001+oNE+dpo0oFE++kbeEK5YCXhpzuCij9LCq4+8vAuT J5v+tvVy9nOtGFUSAf2XA8N7thQ++izsqqjTYCt0B2qlpUGER10jx/ciWSjDLNlN3OIF D71g== X-Gm-Message-State: AOAM532Bgidkv1rNjUs2mdhR5E/fymYEUwMNEEacnIDXNEqFZ8tNqiV3 SA+dKRoce/trlNt8uOIKGbBe+Q== X-Google-Smtp-Source: ABdhPJzuRCCRkiCXmkQ4uct0ET1s6jpxuw4eppcALK9l9iv3G2BJT4A0mDWv47ZfhzCx8cMo3QuMAQ== X-Received: by 2002:a17:90a:f3c7:b0:1d9:6832:7be0 with SMTP id ha7-20020a17090af3c700b001d968327be0mr14406860pjb.209.1650999192070; Tue, 26 Apr 2022 11:53:12 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id cl18-20020a17090af69200b001cd4989ff5asm3839664pjb.33.2022.04.26.11.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 11:53:11 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 3/4] RISC-V: Prefer sstc extension if available Date: Tue, 26 Apr 2022 11:52:44 -0700 Message-Id: <20220426185245.281182-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426185245.281182-1-atishp@rivosinc.com> References: <20220426185245.281182-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_115313_711966_7066E7E3 X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V ISA has sstc extension which allows updating the next clock event via a CSR (stimecmp) instead of an SBI call. This should happen dynamically if sstc extension is available. Otherwise, it will fallback to SBI call to maintain backward compatibility. Signed-off-by: Atish Patra --- drivers/clocksource/timer-riscv.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 1767f8bf2013..d9398ae84a20 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -23,11 +23,24 @@ #include #include +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); + static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { + uint64_t next_tval = get_cycles64() + delta; + csr_set(CSR_IE, IE_TIE); - sbi_set_timer(get_cycles64() + delta); + if (static_branch_likely(&riscv_sstc_available)) { +#if __riscv_xlen == 32 + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); + csr_write(CSR_STIMECMPH, next_tval >> 32); +#else + csr_write(CSR_STIMECMP, next_tval); +#endif + } else + sbi_set_timer(next_tval); + return 0; } @@ -165,6 +178,12 @@ static int __init riscv_timer_init_dt(struct device_node *n) if (error) pr_err("cpu hp setup state failed for RISCV timer [%d]\n", error); + + if (riscv_isa_extension_available(NULL, SSTC)) { + pr_info("Timer interrupt in S-mode is available via sstc extension\n"); + static_branch_enable(&riscv_sstc_available); + } + return error; } From patchwork Tue Apr 26 18:52:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12827803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72133C433EF for ; Tue, 26 Apr 2022 18:53:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/x7rV2WEnBynb/HDxsCHwENtuTt5TFWgCHDfEOg+Udw=; b=Nl7bu78A8qQVOt gPpttpUlTfCmPdWFam2ecm+q7SRfutOo5KGrYUyUpUS6l1JCR6YNWOGMH4i9JZrRAvmYChu6MHdHX lPJplrEH6/9Dal529SICPZTqTLEZAu0a0uxSubFao9o7ScFKqUrjnMxmhzNr6zVUInZ1H0CTpbZGS zo6vsFLCvDQEi2SqsGGdJrHNx98Ol1BSq9W82az5VVId/AdPsxQW3yfZmgTy1amCFc5vLHVsEoFuB 7uQF9DaPAZioMjkzdhfCmQ7LrIy0PyjlptYnUDtxWQm62dfx+izguPFiShj2g6cvvYeM0kiIcwGbM YyW8J/GMs0U0bU9ZfMwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJX-00FrKq-DS; Tue, 26 Apr 2022 18:53:31 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njQJG-00FrAm-RU for linux-riscv@lists.infradead.org; Tue, 26 Apr 2022 18:53:17 +0000 Received: by mail-pj1-x102f.google.com with SMTP id t11-20020a17090ad50b00b001d95bf21996so2953816pju.2 for ; Tue, 26 Apr 2022 11:53:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6cFlsnzmTTm5Xa66rH6KwzB/ux+mVCgL41wPwnI7Qx8=; b=OWjJIkZ/YgZx4Cpr0ozr69PHay6bOYKiY/0i/E2coBccOMx1uBjGyoJtX+VR73iOWp 9r1QjEqgaWhY8NCosjfqE8/13Lz582Otu1u7HLFxm3YZAqRWjA4i4vb8U1M7GYYBzVaU 2rEsSyYKsvEIzclvKcG6GdhUOckM+al/RwOR3D/fKNT7haiaWOHjNne7Ut+o8Un1ZT3J zk6oJG/dAxiRyRiX7G1Z3i5f9clL/mHPWYt4ULe6r44mtc/3woeRHn7+CY3pDTj3oabQ K/ifyZ06XHxQDXpgFfOwpO5ZNLYt36ozOWMuXNOXJ/7GCxGNxHi5aKV4E8GJta9838F4 f0oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6cFlsnzmTTm5Xa66rH6KwzB/ux+mVCgL41wPwnI7Qx8=; b=mJb5nAXtxeoYQ5xxx6WUN5GHvVDNchZVrNIxJV1jdSp9LzLnb0jBwWFLbkLfmuteQa nI1XCTKUkTXPOXCfmYLVUm4Lq8nwiYwkdsTRsoU1A/yF8SMcUI8qK2dJwUTTWV1Yxo+e kyGblJOuPBg+w1pbGvaqNjUixlmar6XWvKDkttUzusNI7zELbw7ZWcxx0Ae2NAntlTDo BsQhxeyv0NCVUKd+bsXA4gj0HlvEkkeDcYjYWAIbyOmqZNjbMAQ9iZDVvr2Kb2Gfu8e9 BR4ODvvFZ7ypNXy8FC6xlApUzo5TK2TfaKIkJoEHsuMUWWXGTxRBOxNFItfcarAtHlKd XQaQ== X-Gm-Message-State: AOAM532ff+9ZVrgBvogVlo6HlhEB8AwT5MJ9fcFKndDziu4ISBDi5Bfa jD4LUEQ873THWlutI1KYdHjrMQ== X-Google-Smtp-Source: ABdhPJxMXG7bgj2sBNfkDEkhV8AwVjIZNQ2rPJw1G8XIQJ8Gs0AqWxXktxNSheZlvq160WrOXvWZwQ== X-Received: by 2002:a17:90a:d0c5:b0:1c9:ec78:18e5 with SMTP id y5-20020a17090ad0c500b001c9ec7818e5mr39005065pjw.53.1650999193879; Tue, 26 Apr 2022 11:53:13 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id cl18-20020a17090af69200b001cd4989ff5asm3839664pjb.33.2022.04.26.11.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 11:53:13 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 4/4] RISC-V: KVM: Support sstc extension Date: Tue, 26 Apr 2022 11:52:45 -0700 Message-Id: <20220426185245.281182-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426185245.281182-1-atishp@rivosinc.com> References: <20220426185245.281182-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_115314_977656_A4C94AAA X-CRM114-Status: GOOD ( 19.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/main.c | 12 ++- arch/riscv/kvm/vcpu.c | 5 +- arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++- 6 files changed, 159 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 78da839657e5..50a97c821f83 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -135,6 +135,7 @@ struct kvm_vcpu_csr { unsigned long hvip; unsigned long vsatp; unsigned long scounteren; + u64 vstimecmp; }; struct kvm_vcpu_arch { diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 375281eb49e0..a24a265f3ccb 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -28,6 +28,11 @@ struct kvm_vcpu_timer { u64 next_cycles; /* Underlying hrtimer instance */ struct hrtimer hrt; + + /* Flag to check if sstc is enabled or not */ + bool sstc_enabled; + /* A function pointer to switch between stimecmp or hrtimer at runtime */ + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles); }; int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles); @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); int kvm_riscv_guest_timer_init(struct kvm *kvm); - +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); #endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92bd469e2ba6..d2f02ba1947a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_H, KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 2e5ca43c8c49..83c4db7fc35f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque) int kvm_arch_hardware_enable(void) { - unsigned long hideleg, hedeleg; + unsigned long hideleg, hedeleg, henvcfg; hedeleg = 0; hedeleg |= (1UL << EXC_INST_MISALIGNED); @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void) csr_write(CSR_HCOUNTEREN, -1UL); + if (riscv_isa_extension_available(NULL, SSTC)) { +#ifdef CONFIG_64BIT + henvcfg = csr_read(CSR_HENVCFG); + csr_write(CSR_HENVCFG, henvcfg | 1UL<arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); + kvm_riscv_vcpu_timer_save(vcpu); + csr->vsstatus = csr_read(CSR_VSSTATUS); csr->vsie = csr_read(CSR_VSIE); csr->vstvec = csr_read(CSR_VSTVEC); diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 5c4c37ff2d48..d226a931de92 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) return 0; } -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles) +{ +#if __riscv_xlen == 32 + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); + csr_write(CSR_VSTIMECMPH, ncycles >> 32); +#else + csr_write(CSR_VSTIMECMP, ncycles); +#endif + return 0; +} + +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) return 0; } +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + return t->timer_next_event(vcpu, ncycles); +} + +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h) +{ + u64 delta_ns; + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + + if (kvm_riscv_current_cycles(gt) < t->next_cycles) { + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns)); + return HRTIMER_RESTART; + } + + t->next_set = false; + kvm_vcpu_kick(vcpu); + + return HRTIMER_NORESTART; +} + +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) || + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER)) + return true; + else + return false; +} + +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 delta_ns; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!t->init_done) + return; + + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t); + if (delta_ns) { + t->next_cycles = vstimecmp_val; + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL); + t->next_set = true; + } +} + +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} + int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) return -EINVAL; hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; t->init_done = true; t->next_set = false; + /* Enable sstc for every vcpu if available in hardware */ + if (riscv_isa_extension_available(NULL, SSTC)) { + t->sstc_enabled = true; + t->hrt.function = kvm_riscv_vcpu_vstimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp; + } else { + t->sstc_enabled = false; + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer; + } + return 0; } @@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); } -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) { struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) #endif } +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + kvm_riscv_vcpu_update_timedelta(vcpu); + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; +#ifdef CONFIG_64BIT + csr_write(CSR_VSTIMECMP, csr->vstimecmp); +#else + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp); + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32)); +#endif + + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + kvm_riscv_vcpu_timer_unblocking(vcpu); +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; + t = &vcpu->arch.timer; +#ifdef CONFIG_64BIT + csr->vstimecmp = csr_read(CSR_VSTIMECMP); +#else + csr->vstimecmp = csr_read(CSR_VSTIMECMP); + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32; +#endif + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + if (kvm_vcpu_is_blocking(vcpu)) + kvm_riscv_vcpu_timer_blocking(vcpu); +} + int kvm_riscv_guest_timer_init(struct kvm *kvm) { struct kvm_guest_timer *gt = &kvm->arch.timer;