From patchwork Thu Apr 28 15:16:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830887 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33EBAC433EF for ; Thu, 28 Apr 2022 15:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348973AbiD1PUB (ORCPT ); Thu, 28 Apr 2022 11:20:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348948AbiD1PT5 (ORCPT ); Thu, 28 Apr 2022 11:19:57 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 290F1AFAE8; Thu, 28 Apr 2022 08:16:40 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 819CEE000C; Thu, 28 Apr 2022 15:16:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651158999; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UkENKga2piTorYviraVnH7jRSnL6Crtq1ti3k91LTnI=; b=Pt89lRzlTyTJGDo+1zFmBKbJ1EtRkl1dHEkyvYAvO3oJ0cRbsrYrw12J/Gp9hxnEIoHG39 E2p3zWPPDTLSe4elEogppb7x+I0iwaME9Xwz9GrDpm2XE/K0nImIRyRjCJsrxo9B3rNHxN Ljk55w9f0FCuEzj4OwCQP9PxWLKAB04lYrBup06URKZXz3T6O4LOkT3ODfBAUNetoUnjyC NLvFbM9rHiB3gXlTQd9y7fMJ1Hbf8uLIWl/ZIfqh0idKZIoUwW8gKIdRJTID88+P/aSRLK jh72r1iDC8HkEUqX7S1YDVtQn55K3xDRRcMVEnYF8m2bb5bZlU358OyYMjbe/g== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Date: Thu, 28 Apr 2022 17:16:25 +0200 Message-Id: <20220428151630.586009-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Convert Renesas PCI bridge bindings documentation to json-schema. Signed-off-by: Herve Codina Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ---------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++ 2 files changed, 156 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt deleted file mode 100644 index aeba38f0a387..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Renesas AHB to PCI bridge -------------------------- - -This is the bridge used internally to connect the USB controllers to the -AHB. There is one bridge instance per USB port connected to the internal -OHCI and EHCI controllers. - -Required properties: -- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; - "renesas,pci-r8a7743" for the R8A7743 SoC; - "renesas,pci-r8a7744" for the R8A7744 SoC; - "renesas,pci-r8a7745" for the R8A7745 SoC; - "renesas,pci-r8a7790" for the R8A7790 SoC; - "renesas,pci-r8a7791" for the R8A7791 SoC; - "renesas,pci-r8a7793" for the R8A7793 SoC; - "renesas,pci-r8a7794" for the R8A7794 SoC; - "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: A list of physical regions to access the device: the first is - the operational registers for the OHCI/EHCI controllers and the - second is for the bridge configuration and control registers. -- interrupts: interrupt for the device. -- clocks: The reference to the device clock. -- bus-range: The PCI bus number range; as this is a single bus, the range - should be specified as the same value twice. -- #address-cells: must be 3. -- #size-cells: must be 2. -- #interrupt-cells: must be 1. -- interrupt-map: standard property used to define the mapping of the PCI - interrupts to the GIC interrupts. -- interrupt-map-mask: standard property that helps to define the interrupt - mapping. - -Optional properties: -- dma-ranges: a single range for the inbound memory region. If not supplied, - defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the - allowed combinations of address and size. - -Example SoC configuration: - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - reg = <0x0 0xee090000 0x0 0xc00>, - <0x0 0xee080000 0x0 0x1100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - -Example board setup: - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file mode 100644 index 000000000000..494eb975c146 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas AHB to PCI bridge + +maintainers: + - Marek Vasut + - Yoshihiro Shimoda + +description: | + This is the bridge used internally to connect the USB controllers to the + AHB. There is one bridge instance per USB port connected to the internal + OHCI and EHCI controllers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,pci-r8a7742 # RZ/G1H + - renesas,pci-r8a7743 # RZ/G1M + - renesas,pci-r8a7744 # RZ/G1N + - renesas,pci-r8a7745 # RZ/G1E + - renesas,pci-r8a7790 # R-Car H2 + - renesas,pci-r8a7791 # R-Car M2-W + - renesas,pci-r8a7793 # R-Car M2-N + - renesas,pci-r8a7794 # R-Car E2 + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + + reg: + items: + - description: Operational registers for the OHCI/EHCI controllers. + - description: Bridge configuration and control registers. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Device clock + + clock-names: + items: + - const: pclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + bus-range: + description: | + The PCI bus number range; as this is a single bus, the range + should be specified as the same value twice. + + dma-ranges: + description: | + A single range for the inbound memory region. If not supplied, + defaults to 1GiB at 0x40000000. Note there are hardware restrictions on + the allowed combinations of address and size. + maxItems: 1 + +patternProperties: + 'usb@[0-1],0': + type: object + + description: + This a USB controller PCI device + + properties: + reg: + description: + Identify the correct bus, device and function number in the + form . + + items: + minItems: 5 + maxItems: 5 + + phys: + description: + Reference to the USB phy + maxItems: 1 + + phy-names: + maxItems: 1 + + required: + - reg + - phys + - phy-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-map + - interrupt-map-mask + - clocks + - resets + - power-domains + - bus-range + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pci@ee090000 { + compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0xee090000 0xc00>, + <0xee080000 0x1100>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + interrupts = ; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>; + dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; From patchwork Thu Apr 28 15:16:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830888 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59CE2C4167E for ; Thu, 28 Apr 2022 15:16:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348984AbiD1PUB (ORCPT ); Thu, 28 Apr 2022 11:20:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348943AbiD1PUA (ORCPT ); Thu, 28 Apr 2022 11:20:00 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30A3BAFB12; Thu, 28 Apr 2022 08:16:43 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id CFBF5E000E; Thu, 28 Apr 2022 15:16:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651159002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=06TMdTJYHqBbnJ4uCL9uIfbfmJMh8P3o+sNzkdRLVYU=; b=VaJz3r5dZprrzxiGSNZRwiDaUqn6tx0m3l9IZx8hsDEg9aB1QkSj5lu6ZAjyrYaT09RtfU W/826eRcGh+HuObgGsAnvAEcAOhNCKBa9M5CsVlkp1LL2xhJcXnHBqyvg9DPe9R+gR5ukf 984g/4Qty8bQNNDUG8jOWkRr+hpGfZeg7vLZ+vawIzuXT+yfI2YQFsU21HFiDBDWrOVQA9 IRdjy75J6A6wt8n0C4HLhGhCGRFHsJbq55x07UaSSoMy2zPmGbimmXjo0hdBGagj7FvpuF 5ydJ5M03uK/V+46sPXKrJ9R6CKzYGhB8YhoRGCAlNyBr3Yik9VCzzNq9Somb2A== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Date: Thu, 28 Apr 2022 17:16:26 +0200 Message-Id: <20220428151630.586009-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family. Compared to the R-Car Gen2 family, it needs three clocks instead of one. The 'resets' property for the RZ/N1 family is not required since there is no reset-controller support yet for the RZ/N1 family. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 46 ++++++++++++++++--- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 494eb975c146..90b42d44c582 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -32,6 +32,10 @@ properties: - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pci-r9a06g032 # RZ/N1D + - const: renesas,pci-rzn1 # RZ/N1 reg: items: @@ -41,13 +45,9 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: Device clock + clocks: true - clock-names: - items: - - const: pclk + clock-names: true resets: maxItems: 1 @@ -106,13 +106,45 @@ required: - interrupt-map - interrupt-map-mask - clocks - - resets - power-domains - bus-range - "#address-cells" - "#size-cells" - "#interrupt-cells" +if: + properties: + compatible: + contains: + enum: + - renesas,pci-rzn1 + +then: + properties: + clocks: + items: + - description: Internal bus clock (AHB) for HOST + - description: Internal bus clock (AHB) Power Management + - description: PCI clock for USB subsystem + clock-names: + items: + - const: usb_hclkh + - const: usb_hclkpm + - const: usb_pciclk + required: + - clock-names + +else: + properties: + clocks: + items: + - description: Device clock + clock-names: + items: + - const: pclk + required: + - resets + unevaluatedProperties: false examples: From patchwork Thu Apr 28 15:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830889 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0329C35275 for ; Thu, 28 Apr 2022 15:16:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348954AbiD1PUD (ORCPT ); Thu, 28 Apr 2022 11:20:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348985AbiD1PUB (ORCPT ); Thu, 28 Apr 2022 11:20:01 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC6B3AFAE8; Thu, 28 Apr 2022 08:16:46 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id B4B30E0015; Thu, 28 Apr 2022 15:16:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651159005; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rjMeOqT8ckJ1eXw+bfbfwC2c+Yq4ThpPuZa9Zo7yK8U=; b=je9uKP3oAuzqhXRoB8bOqzQe6pF/53qYe0Mtpx6xOwZhStOWNNGMHw/SMCy0jyw0kcKoV2 AZioG16T8tuF8gU9utfETbOceeltBIs4V2hXo8gRH8pig5v07jwf1cxI07XqOLejbX+OR+ mOnL7RDcDDOmno+twpmMCG4foNVDNVwn8FE2v8rkKkt7aoEVD4Z3ZTUHStfxZs7wt/zZxJ uzD6/Xvj7bF+dWmr9pIxLnnVCCKvVcRoHi0/L9pdB5jV2Iwh7MnKvAg5yXZ3t8ENYoVlyD qe52C8xfS0bjJQV7vJdqOggk5LnzxNXcBUTIlAXeLM1QboB/UC8ukCn7rtTXGA== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Date: Thu, 28 Apr 2022 17:16:27 +0200 Message-Id: <20220428151630.586009-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2 PCI bridge driver. The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one available in the R-Car Gen2 family. Tested with the RZ/N1D (R9A06G032) SOC. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- drivers/pci/controller/pci-rcar-gen2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c index 35804ea394fd..839695791757 100644 --- a/drivers/pci/controller/pci-rcar-gen2.c +++ b/drivers/pci/controller/pci-rcar-gen2.c @@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = { { .compatible = "renesas,pci-r8a7791", }, { .compatible = "renesas,pci-r8a7794", }, { .compatible = "renesas,pci-rcar-gen2", }, + { .compatible = "renesas,pci-rzn1", }, { }, }; From patchwork Thu Apr 28 15:16:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830890 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 422DAC433F5 for ; Thu, 28 Apr 2022 15:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348985AbiD1PUS (ORCPT ); Thu, 28 Apr 2022 11:20:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349000AbiD1PUQ (ORCPT ); Thu, 28 Apr 2022 11:20:16 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFD3FAFB1C; Thu, 28 Apr 2022 08:16:50 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 7640CE0002; Thu, 28 Apr 2022 15:16:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651159009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d9l6NQQrahvpT9nXUxyuFVP26OC7kXj+zx7LJhpUN3Q=; b=eNHlQn8CqcpNqId+Y70BJRaVQ9Ez+JIQJTSD1jOm9HDq5O+tYejoW8IbkzbGbZ5aZN1XnW JMk6HqSwWLGKMqdVJJ/2Db0eLkcBV0d/Edlprg66Rlgll1LUzFd8bWbBZ5oUGUaTQvtvqW ebp+YbYaNpiABYKmT9xa3KLCTEA5K2KiBtx1rVoiXjYwsGeelosARrwa/+IAtYoDP9gQKj 2O0JE86VL7EoJzHVKpL9iJUpMf0p7JB3dcC6Zq16Ad2yxMTqmZoW3WG1zA/EJ+E5L6s8XC Fw+WTiFqzz4cHoMgn49LABI9737QH38dlZPOHmH9CqnPE31WU41MGvG3zOMG5Q== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Date: Thu, 28 Apr 2022 17:16:28 +0200 Message-Id: <20220428151630.586009-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 636a6ab31c58..a11a50426a8e 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -93,6 +93,35 @@ sysctrl: system-controller@4000c000 { clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; }; + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "usb_hclkh", "usb_hclkpm", "usb_pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>; From patchwork Thu Apr 28 15:16:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830891 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8F4C433FE for ; Thu, 28 Apr 2022 15:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349078AbiD1PUW (ORCPT ); Thu, 28 Apr 2022 11:20:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349005AbiD1PUT (ORCPT ); Thu, 28 Apr 2022 11:20:19 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A4C9AFB13; Thu, 28 Apr 2022 08:16:54 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id BF0BAE000D; Thu, 28 Apr 2022 15:16:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651159012; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qoVK2OcU/IoZYytg8+7HSK2Cr51JN2s8RcRBAMAc19Y=; b=BlWZs42gHsOS+gip1CTAmV+azC8Kc5c4h18vywZT60sk1glaFno5S5H8csTGxFXFNTkXPQ xH/m3253HIkI0AtbDNrWuTuw89l+pN0vCfgOc1bgGY6js08lgUPnOBfSRwBp96OnCbSG+t AkGHOeZnwbSrKCyd3+wkRNCjy+vfxA6izxxygG6Ecij7Rbe1pC0uU1NaNsu79s0rk/1A1q HBOQe13Meyq66D9ks6n2Kl8cRVrMQhO9Kun/YgtDOA03gBNzMCsEyUGAYRm11ZeJuYej2N DVOeScJQxlM9AGpfWGesQreu4mQCVga1T0lL4bdlsWverP3OpAPc9auVzTr4ZA== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Date: Thu, 28 Apr 2022 17:16:29 +0200 Message-Id: <20220428151630.586009-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index a11a50426a8e..dd4b1ddd3601 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -254,4 +254,10 @@ timer { , ; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; }; From patchwork Thu Apr 28 15:16:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12830892 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DC09C43219 for ; Thu, 28 Apr 2022 15:17:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349054AbiD1PU2 (ORCPT ); Thu, 28 Apr 2022 11:20:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349053AbiD1PUT (ORCPT ); Thu, 28 Apr 2022 11:20:19 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E19F2AFB14; Thu, 28 Apr 2022 08:16:57 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 93BDBE000C; Thu, 28 Apr 2022 15:16:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651159015; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w3pZXXCT/j4+InWfaqZPrceul+QrUJYTf2Df3YfgcaE=; b=hwVY5M8wOr6LJCQF2rxtRmcJgj5iKEMK+6h17lKN1X6DCJI0SIk/Np22kT2dBylap/oShf hv94r/4QyLkPrIylFhFEaYtZKE7tsSYeXNe2QZMKKX2Gfdb2EMXe4hPtvxriu2x2UZuTXR q1X8ovKeFuqb2h2F+Pz6eX+zgQO50uNe/Sg4ipjsmsuRaE/bKRE+lKeK6jePQafbEWHugt KpW8VoFQ2TSyVeJaz9JqcFx4KZNKpXClcaJ69vk/isZbNipulUSy3Y9wfG/MqXVzMW8eeU kf0CTEC+XN3IGXDBA+ezszKj9w4W7PlVDXqXmj8w84X8PAtxJEoGbDxBORHeQA== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v4 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Date: Thu, 28 Apr 2022 17:16:30 +0200 Message-Id: <20220428151630.586009-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428151630.586009-1-herve.codina@bootlin.com> References: <20220428151630.586009-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index dd4b1ddd3601..ad04093b01f4 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -120,6 +120,18 @@ pci_usb: pci@40030000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 {