From patchwork Fri Apr 29 12:31:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Brugger X-Patchwork-Id: 12831956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA2CC433F5 for ; Fri, 29 Apr 2022 12:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359204AbiD2MfF (ORCPT ); Fri, 29 Apr 2022 08:35:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359153AbiD2MfE (ORCPT ); Fri, 29 Apr 2022 08:35:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83AB2B9F26; Fri, 29 Apr 2022 05:31:46 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 298D1621D0; Fri, 29 Apr 2022 12:31:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 37FDAC385B2; Fri, 29 Apr 2022 12:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651235505; bh=U1fnlH5OyGJ5UIzfEScyxiBRXPgHxk+UHE3ZSX1gPvY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ISPMvNcSQFkMZIWSHYxdg5JmBcRxJsqOeGCndtVUOHzFSep/BT5TXtbexxYIN9Zzv +D9a9cf63EfihTrNLiCSYnSITsZ858oBCjHM9OAyLTHtFm/haWeZ6ioTJtFEM4508X W4q4abspHfamRw89c8Qu/vBggzpAMPr5smLkEFCN3X2QRJXSA8oQRWQzbjenxJVFU4 vVvWes7+RoHQf0M2d4ygN8Fj6V6mJAIK2a401iKT6MLqVWYU6t/sX2ZbKs9zsTqPq2 9k3JTkOU1u4t9YWJ/E3OWsvCRpUR6bsW1GSxvr48e115hufTW00WQFhXx6qalzVU6F IOrrneGjSjqHA== From: matthias.bgg@kernel.org To: mturquette@baylibre.com, sboyd@kernel.org Cc: allen-kh.cheng@mediatek.com, weiyi.lu@mediatek.com, chun-jie.chen@mediatek.com, linux-kernel@vger.kernel.org, ikjn@chromium.org, miles.chen@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, Matthias Brugger , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock Date: Fri, 29 Apr 2022 14:31:31 +0200 Message-Id: <20220429123133.28869-2-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220429123133.28869-1-matthias.bgg@kernel.org> References: <20220429123133.28869-1-matthias.bgg@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Matthias Brugger The msdc gate is part of the MMC driver. Delete the binding description of this node. Signed-off-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- Changes in v2: - Delete compatible in binding descprition as well .../bindings/arm/mediatek/mediatek,mt8192-clock.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml index c8c67c033f8c..b57cc2e69efb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -24,7 +24,6 @@ properties: - mediatek,mt8192-imp_iic_wrap_w - mediatek,mt8192-imp_iic_wrap_n - mediatek,mt8192-msdc_top - - mediatek,mt8192-msdc - mediatek,mt8192-mfgcfg - mediatek,mt8192-imgsys - mediatek,mt8192-imgsys2 @@ -107,13 +106,6 @@ examples: #clock-cells = <1>; }; - - | - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0x11f60000 0x1000>; - #clock-cells = <1>; - }; - - | mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; From patchwork Fri Apr 29 12:31:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Brugger X-Patchwork-Id: 12831957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23ECEC433F5 for ; Fri, 29 Apr 2022 12:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347624AbiD2MfJ (ORCPT ); Fri, 29 Apr 2022 08:35:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359220AbiD2MfI (ORCPT ); Fri, 29 Apr 2022 08:35:08 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00986C90CA; Fri, 29 Apr 2022 05:31:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 92897621B7; Fri, 29 Apr 2022 12:31:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0EE14C385B4; Fri, 29 Apr 2022 12:31:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651235509; bh=SR30SRUGpIrkdXGfxFhbhtwcmEyED8PObTGdvWsRM14=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y3ixgwhgWJLEfARoa3da3astT6U/FbRks8z3kgcvOsg79q+rLvyJ2qKg2H5JdxeE+ gYDIMnLGHHZEx3y4taU3uC8mQSMtrItRW5MlajvOvP4ts/bsdxGqnksVcGEQxKgQ4K Qg7Xiwr9/Ajh5PA3IZZQEVDoV1oqbS8W2KnMOAnOIa2hfycJ6qzAAkN01oCCOYMzeD xH3LSsaTufCVdkEDblV1LZyWTDNkCcOnT3rXGylReSPEutZjHgVavYiDgkRKRZSv2y NSiLA1QuyxJ/naJb/PWVs284Rr0GzvCPJHIrunzxbPQtGwtPP7cUBBCh/GBowaiszc 741KnnTeixmgw== From: matthias.bgg@kernel.org To: mturquette@baylibre.com, sboyd@kernel.org Cc: allen-kh.cheng@mediatek.com, weiyi.lu@mediatek.com, chun-jie.chen@mediatek.com, linux-kernel@vger.kernel.org, ikjn@chromium.org, miles.chen@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, Matthias Brugger Subject: [PATCH v2 2/2] clk: mediatek: Delete MT8192 msdc gate Date: Fri, 29 Apr 2022 14:31:32 +0200 Message-Id: <20220429123133.28869-3-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220429123133.28869-1-matthias.bgg@kernel.org> References: <20220429123133.28869-1-matthias.bgg@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Matthias Brugger The msdc gate is part of the MMC driver. Delete the not used code. Signed-off-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- Changes in v2: - add Reviewed-by tag drivers/clk/mediatek/clk-mt8192-msdc.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c index 87c3b79b79cf..635f7a0b629a 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -12,28 +12,15 @@ #include -static const struct mtk_gate_regs msdc_cg_regs = { - .set_ofs = 0xb4, - .clr_ofs = 0xb4, - .sta_ofs = 0xb4, -}; - static const struct mtk_gate_regs msdc_top_cg_regs = { .set_ofs = 0x0, .clr_ofs = 0x0, .sta_ofs = 0x0, }; -#define GATE_MSDC(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - #define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -static const struct mtk_gate msdc_clks[] = { - GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22), -}; - static const struct mtk_gate msdc_top_clks[] = { GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), @@ -52,11 +39,6 @@ static const struct mtk_gate msdc_top_clks[] = { GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), }; -static const struct mtk_clk_desc msdc_desc = { - .clks = msdc_clks, - .num_clks = ARRAY_SIZE(msdc_clks), -}; - static const struct mtk_clk_desc msdc_top_desc = { .clks = msdc_top_clks, .num_clks = ARRAY_SIZE(msdc_top_clks), @@ -64,9 +46,6 @@ static const struct mtk_clk_desc msdc_top_desc = { static const struct of_device_id of_match_clk_mt8192_msdc[] = { { - .compatible = "mediatek,mt8192-msdc", - .data = &msdc_desc, - }, { .compatible = "mediatek,mt8192-msdc_top", .data = &msdc_top_desc, }, {