From patchwork Fri Apr 29 13:41:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832025 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DCEFC433FE for ; Fri, 29 Apr 2022 13:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354638AbiD2NpS (ORCPT ); Fri, 29 Apr 2022 09:45:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376314AbiD2NpQ (ORCPT ); Fri, 29 Apr 2022 09:45:16 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3D89CB009; Fri, 29 Apr 2022 06:41:56 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 35E8C1BF20C; Fri, 29 Apr 2022 13:41:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239715; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UkENKga2piTorYviraVnH7jRSnL6Crtq1ti3k91LTnI=; b=GuVQVKnNv3F74Y4Dg3xB2v3YRQf4QOhZ5Jtn8f46qVZUHNNd9zzJIW1p99uBWd7d3DdQM5 8VQuENdepEN0gWXo46gaTq+ju3XgV7f0/p5ymhlWowYJ1u0UoqjmQkC2G9rTYLG5P+Jnm+ WRKX1673XSsZGcoyXZmcEj1jf7vrkYScfQK1ALicCbUaCVV3b8lSLU7hUoiehoeDHsm1Lm xbKIRyObMqrhAtzu98q9iMdJHY5hcTtKPOEi1fYHzlGiaykfe0MlXvMivSKuBuLguGB6gQ jqLSEIRHmm/T2MryBk8YWrKOhZmctl0b3jrZKraoB5kcn7So2Sz90dJWONLjUQ== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Date: Fri, 29 Apr 2022 15:41:38 +0200 Message-Id: <20220429134143.628428-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Convert Renesas PCI bridge bindings documentation to json-schema. Signed-off-by: Herve Codina Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ---------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++ 2 files changed, 156 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt deleted file mode 100644 index aeba38f0a387..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Renesas AHB to PCI bridge -------------------------- - -This is the bridge used internally to connect the USB controllers to the -AHB. There is one bridge instance per USB port connected to the internal -OHCI and EHCI controllers. - -Required properties: -- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; - "renesas,pci-r8a7743" for the R8A7743 SoC; - "renesas,pci-r8a7744" for the R8A7744 SoC; - "renesas,pci-r8a7745" for the R8A7745 SoC; - "renesas,pci-r8a7790" for the R8A7790 SoC; - "renesas,pci-r8a7791" for the R8A7791 SoC; - "renesas,pci-r8a7793" for the R8A7793 SoC; - "renesas,pci-r8a7794" for the R8A7794 SoC; - "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: A list of physical regions to access the device: the first is - the operational registers for the OHCI/EHCI controllers and the - second is for the bridge configuration and control registers. -- interrupts: interrupt for the device. -- clocks: The reference to the device clock. -- bus-range: The PCI bus number range; as this is a single bus, the range - should be specified as the same value twice. -- #address-cells: must be 3. -- #size-cells: must be 2. -- #interrupt-cells: must be 1. -- interrupt-map: standard property used to define the mapping of the PCI - interrupts to the GIC interrupts. -- interrupt-map-mask: standard property that helps to define the interrupt - mapping. - -Optional properties: -- dma-ranges: a single range for the inbound memory region. If not supplied, - defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the - allowed combinations of address and size. - -Example SoC configuration: - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - reg = <0x0 0xee090000 0x0 0xc00>, - <0x0 0xee080000 0x0 0x1100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - -Example board setup: - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file mode 100644 index 000000000000..494eb975c146 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas AHB to PCI bridge + +maintainers: + - Marek Vasut + - Yoshihiro Shimoda + +description: | + This is the bridge used internally to connect the USB controllers to the + AHB. There is one bridge instance per USB port connected to the internal + OHCI and EHCI controllers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,pci-r8a7742 # RZ/G1H + - renesas,pci-r8a7743 # RZ/G1M + - renesas,pci-r8a7744 # RZ/G1N + - renesas,pci-r8a7745 # RZ/G1E + - renesas,pci-r8a7790 # R-Car H2 + - renesas,pci-r8a7791 # R-Car M2-W + - renesas,pci-r8a7793 # R-Car M2-N + - renesas,pci-r8a7794 # R-Car E2 + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + + reg: + items: + - description: Operational registers for the OHCI/EHCI controllers. + - description: Bridge configuration and control registers. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Device clock + + clock-names: + items: + - const: pclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + bus-range: + description: | + The PCI bus number range; as this is a single bus, the range + should be specified as the same value twice. + + dma-ranges: + description: | + A single range for the inbound memory region. If not supplied, + defaults to 1GiB at 0x40000000. Note there are hardware restrictions on + the allowed combinations of address and size. + maxItems: 1 + +patternProperties: + 'usb@[0-1],0': + type: object + + description: + This a USB controller PCI device + + properties: + reg: + description: + Identify the correct bus, device and function number in the + form . + + items: + minItems: 5 + maxItems: 5 + + phys: + description: + Reference to the USB phy + maxItems: 1 + + phy-names: + maxItems: 1 + + required: + - reg + - phys + - phy-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-map + - interrupt-map-mask + - clocks + - resets + - power-domains + - bus-range + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pci@ee090000 { + compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0xee090000 0xc00>, + <0xee080000 0x1100>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + interrupts = ; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>; + dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; From patchwork Fri Apr 29 13:41:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832026 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F2A9C433FE for ; Fri, 29 Apr 2022 13:42:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376324AbiD2NpX (ORCPT ); Fri, 29 Apr 2022 09:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376336AbiD2NpW (ORCPT ); Fri, 29 Apr 2022 09:45:22 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C814C8BD9; Fri, 29 Apr 2022 06:41:59 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 8F9B31BF203; Fri, 29 Apr 2022 13:41:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239718; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZvWaj7kw5MGb8QyOny/MnqwKXJHfwAIyTe4kVHOxwB8=; b=PgHKF5zj6j6859PuLYJADYu1bqsXQdL2qjUfEcjX6W1fON/MijLx5/eqhmoq1wb11gYcOk TtJjlP+9H4jFnqJ6fR4yyWvGWfwnLYUEp4gvSWnhlucs1JAQJjs91kPFuu9sVcUts/GeT2 A0xEYNlaRQEMp1QiIyY0eotEiZ4re9HTnDC2QY0UexiDQrdsj9D14SVhOA8gKbmfWeJ9Sk yN4YY5Pg+CyiGLUcOc9MHp/esWO9/Ha75iMcR5tzAeTcqq+kWRyRnDSOOt00Hi/aatyPLf fU/A5s+Osg6LEtbkGiOXXgzjR8n8I6x1R2IiKagjm51m0un84yP3twsBdjl5cQ== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Date: Fri, 29 Apr 2022 15:41:39 +0200 Message-Id: <20220429134143.628428-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family. Compared to the R-Car Gen2 family, it needs three clocks instead of one. The 'resets' property for the RZ/N1 family is not required since there is no reset-controller support yet for the RZ/N1 family. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 46 ++++++++++++++++--- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 494eb975c146..a9f806794f12 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -32,6 +32,10 @@ properties: - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pci-r9a06g032 # RZ/N1D + - const: renesas,pci-rzn1 # RZ/N1 reg: items: @@ -41,13 +45,9 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: Device clock + clocks: true - clock-names: - items: - - const: pclk + clock-names: true resets: maxItems: 1 @@ -106,13 +106,45 @@ required: - interrupt-map - interrupt-map-mask - clocks - - resets - power-domains - bus-range - "#address-cells" - "#size-cells" - "#interrupt-cells" +if: + properties: + compatible: + contains: + enum: + - renesas,pci-rzn1 + +then: + properties: + clocks: + items: + - description: Internal bus clock (AHB) for HOST + - description: Internal bus clock (AHB) Power Management + - description: PCI clock for USB subsystem + clock-names: + items: + - const: hclkh + - const: hclkpm + - const: pciclk + required: + - clock-names + +else: + properties: + clocks: + items: + - description: Device clock + clock-names: + items: + - const: pclk + required: + - resets + unevaluatedProperties: false examples: From patchwork Fri Apr 29 13:41:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832027 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95016C433F5 for ; Fri, 29 Apr 2022 13:42:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376319AbiD2Np0 (ORCPT ); Fri, 29 Apr 2022 09:45:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376366AbiD2NpZ (ORCPT ); Fri, 29 Apr 2022 09:45:25 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83F9ACC538; Fri, 29 Apr 2022 06:42:04 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 36F8B1BF20D; Fri, 29 Apr 2022 13:42:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oAMsDVvTiaLCVhxn/JVH0pxqslPhba8QbfwBEnkBzCU=; b=mm8zVs6fozVCDteJG9lIAHWzwa/IUBMr+6Ujl9DfDbHOxAfwJzsvJeF+WciKYmvUldh5Sz rCzOSi279kgfcnK52zFSLUWW1JHzIF5NLaFuk2c3A3X94lTjr/agFMNS3mEMgg6yzpHzUW TJa95WCaQnmewjKemtyBSiuwBe85+cYIVtkciPQ7TJmLtpdDJY7xeq0DyzgDHzXT7dXkEE ytiaXQW1qLpjWL39ymZtqEZsSkEP6aq/BZjo+AJM6g0pbomOQR8c6y8sRHO/bAvbOFgSBh dUwZx/6FHwB7xB4B1MJB0M+JLFwHawqWbqRz7+g0h3sBneVWW2+bJMaaklvwtg== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Date: Fri, 29 Apr 2022 15:41:40 +0200 Message-Id: <20220429134143.628428-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2 PCI bridge driver. The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one available in the R-Car Gen2 family. Tested with the RZ/N1D (R9A06G032) SOC. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven Acked-by: Lorenzo Pieralisi --- drivers/pci/controller/pci-rcar-gen2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c index 35804ea394fd..839695791757 100644 --- a/drivers/pci/controller/pci-rcar-gen2.c +++ b/drivers/pci/controller/pci-rcar-gen2.c @@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = { { .compatible = "renesas,pci-r8a7791", }, { .compatible = "renesas,pci-r8a7794", }, { .compatible = "renesas,pci-rcar-gen2", }, + { .compatible = "renesas,pci-rzn1", }, { }, }; From patchwork Fri Apr 29 13:41:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832028 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C4CAC433EF for ; Fri, 29 Apr 2022 13:42:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376389AbiD2Npk (ORCPT ); Fri, 29 Apr 2022 09:45:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376314AbiD2Npb (ORCPT ); Fri, 29 Apr 2022 09:45:31 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3BA7C8BD9; Fri, 29 Apr 2022 06:42:10 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id C36B11BF20A; Fri, 29 Apr 2022 13:42:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239729; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m2syZDhXMNfFFdbui/0S6GoKTUC26/S1VVnx+DdDmc4=; b=T3jCq6eRosujw4XJEcBPAwB1q0B329upoBfSs/97YpUdhPO0ezTT83fS3dcXRo7Sn669rL KAqSMeuJPGVSYuVehhUxE5xGeA1YcxlpWQAt0UNmbaRgH6hw9UGdfeFIZX1aaeUkFR/9a9 ia9VqTbgNeYBu5bXld5e5EY/I0EQUp+dhXq0bQnsJJkyW8APdI5aFVpPxUfjCY/2tis4RT dUB8mNM0HkQJbYQVleRXY3DM6Mxn80bGaNTms714N8HizEqSIh5heP8LMEx/wvhc/gmVfr X9NS+1tRzmzXxyn1o11+XaxLfIuqlF4LOlauOPN2PaJWKXIrxx8tP1GAuZIFbA== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Date: Fri, 29 Apr 2022 15:41:41 +0200 Message-Id: <20220429134143.628428-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 20286433d3c6..45944f849190 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -94,6 +94,35 @@ sysctrl: system-controller@4000c000 { clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; }; + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>; From patchwork Fri Apr 29 13:41:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832029 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 503E9C433EF for ; Fri, 29 Apr 2022 13:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376379AbiD2Npo (ORCPT ); Fri, 29 Apr 2022 09:45:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351187AbiD2Npj (ORCPT ); Fri, 29 Apr 2022 09:45:39 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E8DFCB037; Fri, 29 Apr 2022 06:42:13 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 1BA5F1BF209; Fri, 29 Apr 2022 13:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239732; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Psg+kgsloOBducf16xRoRX/ej6BEYer73yn3GaQ0wJU=; b=JPKfWr6bfwgIr3M/1nRLnsG3ZSNR/M4YSjWQG4DJprUt5VCinBiBaW6lj7y/HS97NizxNR ReoRSD4dwVovrMlrmnmoKh/rnrc+otPmnnK8BGfVAbxXZwUnXJP+rl3dpcOJ8xo9fD0/wi 0uDqvEiCm6jUfo0LAteUzvxi+MsaPDbdG5V6wbViMOKRjaGU19wXjy9iTt2yphyNu+yUh8 uVZRhzNUwHMubvz+Bl+IaNTw4MNmrFfzuBymR9MBT0tleUUn4yzUby+PYiT3gjU9NMelJK GtbtjV0B7UVkFn6YdgiUiDAARX62cFaEPImP7+lOFuTpNFXzeMED4CfFrj+brw== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Date: Fri, 29 Apr 2022 15:41:42 +0200 Message-Id: <20220429134143.628428-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 45944f849190..8cedc08ba3b9 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -255,4 +255,10 @@ timer { , ; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; }; From patchwork Fri Apr 29 13:41:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12832030 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 150B7C4332F for ; Fri, 29 Apr 2022 13:42:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376378AbiD2Np7 (ORCPT ); Fri, 29 Apr 2022 09:45:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376406AbiD2Npl (ORCPT ); Fri, 29 Apr 2022 09:45:41 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7420DCD32B; Fri, 29 Apr 2022 06:42:17 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id BDF3E1BF214; Fri, 29 Apr 2022 13:42:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651239736; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3sbzBzsCcC7x9s3vXEvDzSjrA2nDIAK9IYFPPKABIDw=; b=VgmmLpFKEBOrCWjhyHy1u93i2hwuJ9+LJaKQYruUNJ68ZywpJL3NzYzwR8c/vK1ug69DyA +cYiBTNzMOsBkjxiLEHs5dYd8A6B3j8+s8RaZTRHYOZYsPfo6lAPnPhE/LNt8wI7ZzPyiD nZEVzwb/0ULVSiY7mp+LbA9QH75aoiDC6aH+GE8urnSufnCi1O8izetwLt/nWdnvoV9me1 JsU2hi6Jj/plNBijhZoD/E41HK8RGpVTU+JaQoyAqepmYQnYfvuH/cm8O9UFqgBG1jOTRH RnI42ewV4JIwdMFp2bg/0FqDLz8swiIHWw4JK2kl0XTqcuCqpmyj6xHvOjI17A== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v5 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Date: Fri, 29 Apr 2022 15:41:43 +0200 Message-Id: <20220429134143.628428-8-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com> References: <20220429134143.628428-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 8cedc08ba3b9..db1e35381d9b 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -121,6 +121,18 @@ pci_usb: pci@40030000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 {