From patchwork Mon May 2 06:06:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833873 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A463CC433F5 for ; Mon, 2 May 2022 06:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357858AbiEBGKD (ORCPT ); Mon, 2 May 2022 02:10:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357945AbiEBGJy (ORCPT ); Mon, 2 May 2022 02:09:54 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66D7B4E3A5 for ; Sun, 1 May 2022 23:06:26 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id cq17-20020a17090af99100b001dc0386cd8fso6582375pjb.5 for ; Sun, 01 May 2022 23:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mhwiSz4nUEKxyVPxPgnud7ZLMUjJ9Xi44F8SQGqayAg=; b=iLxrj/+HHvqwp534r7ex2+ODCsXS4sjzqe6oSlMHEPI5j7BJ0SgUCZ2YqSjT8+Y6LL dGy71rI2xipA03Dgt7LqaR0sxzqCq+Ld/k7q1aX7AoCA2zY/kFr0iBjXGyfnlJ7BhHPy kmbHhCkFOiFkpVa/sjLPi1RyKF9uFwrrltT4nonpOXnYyqXuxj+e0R+SD8SglSoE72bJ kGalj/TjjopC0cL0UXLfZ+6nedHm4Z7jKHk4yWMXxqHQfjxZ0GDToprso+80r3mN8ZNA GSf+qKjsr72rDkWOeTQhQFx/pDSITjbIuPi0q7C5LV7SuCF7rqO7xg1KNgAQxrdL4Yi/ rhAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mhwiSz4nUEKxyVPxPgnud7ZLMUjJ9Xi44F8SQGqayAg=; b=RXPD+GP8sSlMj/8OYFJYUvBFe51Las8P8GpD4rdoVPN6NhyPqQBNpE/WKEolt+gJdk aH2t9oQe7gDxpXneeX1EndH5XZiEenlYnSyvn4Ph+5NNLnU57amJYkgH9RY3XVzs8yBe tCYVkldEgAmwl3MMhK43UIYvd3J2ngZKMu0k8qxUxwrGQ7OqkVS7gZx+J86cDom9rY5F WgpPzZQk+qKwaDLmJ2ncLV9/g8o3v3lAK4HCGQTBhmL2PbVjkI+kl9puCcdgC5DE7zWF EJNeM9VXW8QTUYCPdnWe/MIyotEf1RNDQUvIGgRTh74QY52phVKfPrYDkkA6BN0izetF LAGg== X-Gm-Message-State: AOAM532QQIF0hHr3S1FcKArum+mWi6F7Wf4hO6BlOuDbLY0RKNIsbbST udTf3NESrlW789unHD0SM3m6QooC3KmF X-Google-Smtp-Source: ABdhPJxG6HMx0DWdiaCr+PhNjaS2SLQj3j4gb1NoZlCahr2ddBju081kXD1bYo3hD052lZVaZwue5Q== X-Received: by 2002:a17:90b:4a02:b0:1dc:4710:c1fe with SMTP id kk2-20020a17090b4a0200b001dc4710c1femr6729696pjb.208.1651471585900; Sun, 01 May 2022 23:06:25 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:25 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/8] PCI: endpoint: Pass EPF device ID to the probe function Date: Mon, 2 May 2022 11:36:04 +0530 Message-Id: <20220502060611.58987-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently, the EPF probe function doesn't get the device ID argument needed to correctly identify the device table ID of the EPF device. When multiple entries are added to the "struct pci_epf_device_id" table, the probe function needs to identify the correct one. And the only way to do so is by storing the correct device ID in "struct pci_epf" during "pci_epf_match_id()" and passing that to probe(). Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-ntb.c | 3 ++- drivers/pci/endpoint/functions/pci-epf-test.c | 2 +- drivers/pci/endpoint/pci-epf-core.c | 8 +++++--- include/linux/pci-epf.h | 4 +++- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c index 9a00448c7e61..980b4ecf19a2 100644 --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c @@ -2075,11 +2075,12 @@ static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf, /** * epf_ntb_probe() - Probe NTB function driver * @epf: NTB endpoint function device + * @id: NTB endpoint function device ID * * Probe NTB function driver when endpoint function bus detects a NTB * endpoint function. */ -static int epf_ntb_probe(struct pci_epf *epf) +static int epf_ntb_probe(struct pci_epf *epf, const struct pci_epf_device_id *id) { struct epf_ntb *ntb; struct device *dev; diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 5b833f00e980..f82b52e07621 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -901,7 +901,7 @@ static const struct pci_epf_device_id pci_epf_test_ids[] = { {}, }; -static int pci_epf_test_probe(struct pci_epf *epf) +static int pci_epf_test_probe(struct pci_epf *epf, const struct pci_epf_device_id *id) { struct pci_epf_test *epf_test; struct device *dev = &epf->dev; diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 9ed556936f48..0882ac829e95 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -494,11 +494,13 @@ static const struct device_type pci_epf_type = { }; static int -pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf *epf) +pci_epf_match_id(const struct pci_epf_device_id *id, struct pci_epf *epf) { while (id->name[0]) { - if (strcmp(epf->name, id->name) == 0) + if (strcmp(epf->name, id->name) == 0) { + epf->id = id; return true; + } id++; } @@ -526,7 +528,7 @@ static int pci_epf_device_probe(struct device *dev) epf->driver = driver; - return driver->probe(epf); + return driver->probe(epf, epf->id); } static void pci_epf_device_remove(struct device *dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 009a07147c61..0c94cc1513bc 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -84,7 +84,7 @@ struct pci_epf_ops { * @id_table: identifies EPF devices for probing */ struct pci_epf_driver { - int (*probe)(struct pci_epf *epf); + int (*probe)(struct pci_epf *epf, const struct pci_epf_device_id *id); void (*remove)(struct pci_epf *epf); struct device_driver driver; @@ -126,6 +126,7 @@ struct pci_epf_bar { * @epc: the EPC device to which this EPF device is bound * @epf_pf: the physical EPF device to which this virtual EPF device is bound * @driver: the EPF driver to which this EPF device is bound + * @id: Pointer to the EPF device ID * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc * @nb: notifier block to notify EPF of any EPC events (like linkup) * @lock: mutex to protect pci_epf_ops @@ -153,6 +154,7 @@ struct pci_epf { struct pci_epc *epc; struct pci_epf *epf_pf; struct pci_epf_driver *driver; + const struct pci_epf_device_id *id; struct list_head list; struct notifier_block nb; /* mutex to protect against concurrent access of pci_epf_ops */ From patchwork Mon May 2 06:06:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833874 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17AABC433FE for ; Mon, 2 May 2022 06:06:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383430AbiEBGKF (ORCPT ); Mon, 2 May 2022 02:10:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357978AbiEBGJ6 (ORCPT ); Mon, 2 May 2022 02:09:58 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BB654ECC3 for ; Sun, 1 May 2022 23:06:29 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id cx11-20020a17090afd8b00b001d9fe5965b3so13364141pjb.3 for ; Sun, 01 May 2022 23:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=93jtjgesAZgKkt2MEbIMRdAbnBRLq9BXrD5v1vHX1gQ=; b=JbBvB6dQd/mSuV8LOxRZPK1pa9SnW1PgfZO16mPnV8by3pq26M1sQuuI1YvqzJhQqI 8p+Hc/cDWK8n9GLfBHaAetj7mRawHbLvmfbtJ1yG173rUxmJm4yorK2fsA7jINDAbtaA M3CzWsjHNW2a6cI5kI2iIN2EvB5zeaCGxQkP9+ochaWD4VNxoFMg8LAwA01pw0cZKXcH KYgf/R7XJgWiPCZxKwQjl2/qxYc0rplEIc7Zhlb5sMgQQ2w6Vc8/CqQDL+TQr01Gdk08 qOoCVHmr7ISE3JQdlLBzLRAx+C619KNncKKpKhnhs/CbsFt79X/LY6Wb6omhAyO7Fogs wetw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=93jtjgesAZgKkt2MEbIMRdAbnBRLq9BXrD5v1vHX1gQ=; b=NB9N3c0sRiPOZCG83m5j52vDNm3mLWVvDLS1F8S0cQuI+Kp3UNnbW2t3Ed38H1hncP eCRKP/6ZK9Tot8b0CCJR4ymghuL8mEHbrI7V9IzEFaf78Db0EvJq6DqlLv9McHWVNjyM 3ZXlb7O78iRHYK/HXM9g5b4lzAi/QzjNW+005qKkO1LkPqGqaKiCHGWoYNs4mCdJr8Lt swQnxMHQjyzuRZPqSCOt0leKiQ4sO92P2puJDamB6j4Y0NpESTfAlMYGflRMAmHkUa/r 9rH/qOXomLV5Bv/vUpNoRQdoTX8hrTAxIlr2dHkSUecb591v6qL3uUprVRJP6qCa2IpP nAIg== X-Gm-Message-State: AOAM532uJ+1/aC+kcxvc4YWfU+aX1f3oaJ01foxar1IEVyPqh1OBJzdu 54rsfL0GoIcPPq3fTs4YKzqx X-Google-Smtp-Source: ABdhPJzmLobDpJ2EzONy0DMl6qqRS3HJXR8j8ZCsc4CrtTvqTxUcHcdEKoWzu++DW5cmRxtzLONgyA== X-Received: by 2002:a17:903:41cb:b0:15e:ab0c:5172 with SMTP id u11-20020a17090341cb00b0015eab0c5172mr1604917ple.170.1651471589075; Sun, 01 May 2022 23:06:29 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:28 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/8] PCI: endpoint: Warn and return if EPC is started/stopped multiple times Date: Mon, 2 May 2022 11:36:05 +0530 Message-Id: <20220502060611.58987-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When the EPC is started or stopped multiple times from configfs, just emit a once time warning and return. There is no need to call the EPC start/stop functions in those cases. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-ep-cfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index d4850bdd837f..2cfd5fd2794c 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -178,6 +178,9 @@ static ssize_t pci_epc_start_store(struct config_item *item, const char *page, if (kstrtobool(page, &start) < 0) return -EINVAL; + if (WARN_ON_ONCE(start == epc_group->start)) + return 0; + if (!start) { pci_epc_stop(epc); epc_group->start = 0; From patchwork Mon May 2 06:06:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833875 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F185C43217 for ; Mon, 2 May 2022 06:06:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383433AbiEBGKG (ORCPT ); Mon, 2 May 2022 02:10:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383424AbiEBGKD (ORCPT ); Mon, 2 May 2022 02:10:03 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0FA4EDE0 for ; Sun, 1 May 2022 23:06:34 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id cu23-20020a17090afa9700b001d98d8e53b7so11962581pjb.0 for ; Sun, 01 May 2022 23:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2LFzmNO7TCPQPtgoHwZk5k2/uRSVZZGRTm5zpsoWJbc=; b=d9NwqnU/0ESwjiYm54qTQDSlOQVbQkLaT/oxMr01WT1sLQSn/nIsYnfDVUIJGmHQFc uDLyfb/6sbStsBgP++Bzpcd/uRNJ0Ek5MCO3JAd0BEvmVNkUN9XbglURygJo93dTIFJ4 D32OsAIgBvYgtFqbMBKZ4ZeAMFmCSjpOvZ8VBxf4PFUOz942bR1c5frVwFcZS0o4uexz 1IDhD8bmckcDWTiDnGJa6yNaThbzees8/IMhpavLgoMecGPPkYNJX6IfiIz9AGSGN8jG ZxpzCb5OmLRR6SMVXtQ5Es8sbIDKAk5vb8qZnjTFKHXlxu20vmw0FY5kdwjLlju9ykH8 WKuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2LFzmNO7TCPQPtgoHwZk5k2/uRSVZZGRTm5zpsoWJbc=; b=66udNVOme5kZFvRqRn2B3GcPcyeNKl2hovanWqSDhBi8hMv23ofAUMdufhxTRXCbTm HvvHrKCyKknSpCJnW5pB+ecPWUDzQKxH2k09UKTPozlql/KsDribCTZJbh8F0hZt4ZBl 0saf0Psf647HYCdwix8Cus8IPFc2XUi3r/4Kon23RmekeL08AVGmgvwx6lu0G3IirPv1 HYzajtPVAaMt+ALU1pCSh+XIUy7Ky++9KXWh/UvdbjkvZ3ktz6xplvp6//9unEixJ9nE IQM0FJLEHfHRag8tH+QryOGsJIa0IZbG5wSAcKpzB2El/90Hh3uKMt94Hzo6L8UudG7c boCQ== X-Gm-Message-State: AOAM531Mk2nE+X2aBbqRs91a26AgvniNmxv3eB4JPiNnLb8q7wxiu38/ w7D+25TzTntoE3jH0cQXTi9c X-Google-Smtp-Source: ABdhPJx8v44BYBTieqJIya4Js5QwL5B5LYV+aXWIrs6lmDjOrWlDALn06JJenvBb1Bv7Ni9twVRZMw== X-Received: by 2002:a17:902:d508:b0:15e:a12e:8089 with SMTP id b8-20020a170902d50800b0015ea12e8089mr4637149plg.137.1651471593731; Sun, 01 May 2022 23:06:33 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:33 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/8] PCI: endpoint: Add an API for unregistering the EPF notifier Date: Mon, 2 May 2022 11:36:06 +0530 Message-Id: <20220502060611.58987-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add "pci_epc_unregister_notifier()" to unregister the notifier added between EPC and EPF. Signed-off-by: Manivannan Sadhasivam --- include/linux/pci-epc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index a48778e1a4ee..c414a08bfd67 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -198,6 +198,12 @@ pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb) return atomic_notifier_chain_register(&epc->notifier, nb); } +static inline int +pci_epc_unregister_notifier(struct pci_epc *epc, struct notifier_block *nb) +{ + return atomic_notifier_chain_unregister(&epc->notifier, nb); +} + struct pci_epc * __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); From patchwork Mon May 2 06:06:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833876 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23D93C433EF for ; Mon, 2 May 2022 06:06:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348929AbiEBGKI (ORCPT ); Mon, 2 May 2022 02:10:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383424AbiEBGKH (ORCPT ); Mon, 2 May 2022 02:10:07 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67D574EF49 for ; Sun, 1 May 2022 23:06:37 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id z16so11555937pfh.3 for ; Sun, 01 May 2022 23:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FL4JimMUhmY1BeTMTK+TnPmU576KVxmETjweuyLuCOo=; b=OFXE66pE/ktWSt/5voVeEhMhzzjJ3ORO0W5OjxJds9qw+k7j2EG9ORxSHmD5i8yEm5 nC9O4KPZiYx+rv4InxZiPdWLN2X4hDs0DhNp1k2iT/ZeAFpAmYyTDJIBCYb9udtNrq+G xPCzCRXZ2b+LgvRYHNkcR98uDFeQdjZNhZ9q7kZSRWU2Z0MDzV3ZeYTHPoWoNpv7+fQs cky8tLry5aLxOdICsNscsAYGlpDeRdlIcFXEG11VuGjhzJ9+YMFlhmiwe7E7yb13rf+H 4HE25MLXBrJ52iZQPuL9A9rrp+85ZdIa9POCM2WQQBOBUr8zfcQh0BR8L4/uAdM8Mxz6 4TuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FL4JimMUhmY1BeTMTK+TnPmU576KVxmETjweuyLuCOo=; b=rg8iLMDwTYiqS38r5vQolJi3L58DnU3UDNhnRJnrTay/V12S6dC+h73s4BQNQGHm3P 5ze+z4dxp9p6ju9PocjSjLMW6NllGj+6Sn2RRU8bS/O1kzJaKElotMYe6DmVUAp8PNlU frFMMuy4OUGz7i19y3+hLZ0nPhE7cWrYGpJzMNk1DVIu8LED8HRZDtQsBv6u6vnkYrn5 Ik98CX/yWXePHkmPdWUwqIFFj8Vw2bH4No2jQPi3t02WZ/BpeNxNw7ya6wcm/M5/1vAM Z6sBrgWpSJqkGMDyHpZs80DREtEvW0OPB6MSjleNKbJUTeSFgq5X2+ibGrFcbPJymhCu 9P6Q== X-Gm-Message-State: AOAM530lHV15XsAWCm3AJgh0WBwsETQ8BBQpJPhCh19L4+e3ylN+w6Wv aLjN/tL+NHy1BIOsaEa8bkk3 X-Google-Smtp-Source: ABdhPJxb6iPxT001JHILmsfK5SvyQcjtft+sZmMyKCsyzDQDauyPZCbU2PiXuVxii4Sz+RFpxlBhLQ== X-Received: by 2002:a62:e518:0:b0:4fa:9333:ddbd with SMTP id n24-20020a62e518000000b004fa9333ddbdmr10156182pff.11.1651471596890; Sun, 01 May 2022 23:06:36 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:36 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 4/8] PCI: endpoint: Add linkdown notifier support Date: Mon, 2 May 2022 11:36:07 +0530 Message-Id: <20220502060611.58987-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to notify the EPF device about the linkdown event from the EPC device. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 17 +++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 3bc9273d0a08..8401c2750c9e 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -697,6 +697,23 @@ void pci_epc_linkup(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_linkup); +/** + * pci_epc_linkdown() - Notify the EPF device that EPC device has dropped the + * connection with the Root Complex. + * @epc: the EPC device which has dropped the link with the host + * + * Invoke to Notify the EPF device that the EPC device has dropped the + * connection with the Root Complex. + */ +void pci_epc_linkdown(struct pci_epc *epc) +{ + if (!epc || IS_ERR(epc)) + return; + + atomic_notifier_call_chain(&epc->notifier, LINK_DOWN, NULL); +} +EXPORT_SYMBOL_GPL(pci_epc_linkdown); + /** * pci_epc_init_notify() - Notify the EPF device that EPC device's core * initialization is completed. diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c414a08bfd67..d346ab9ae061 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -215,6 +215,7 @@ void pci_epc_destroy(struct pci_epc *epc); int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); void pci_epc_linkup(struct pci_epc *epc); +void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 0c94cc1513bc..b1fcd88d0b1f 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -20,6 +20,7 @@ enum pci_epc_interface_type; enum pci_notify_event { CORE_INIT, LINK_UP, + LINK_DOWN, }; enum pci_barno { From patchwork Mon May 2 06:06:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833877 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 563EBC433EF for ; Mon, 2 May 2022 06:06:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383435AbiEBGKM (ORCPT ); Mon, 2 May 2022 02:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383439AbiEBGKK (ORCPT ); Mon, 2 May 2022 02:10:10 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 078B74F462 for ; Sun, 1 May 2022 23:06:40 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id j8so11703155pll.11 for ; Sun, 01 May 2022 23:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=emy+se/hKalbH2tp0a4mK8E86GGOMmeQZbEu2D153u4=; b=gmG8NgYNfGEjNCcuFO9JZOXXmkueQfPGdn69XdTXChZw7LgJKOCytt1QGrtVshbjlG 7nxhD/YJXODxEck25e3j6+lr+C2PTvWL7owGdIiYQn8O7q9yszO1r4l0JZ4wuNDBDQgB 7eQLbQgnu0HChXYnJUFjlN8iUPsDI0UJmIeaCSGk4z6mYNvI9xlS3TmjhM3faJcqlyrl S+GUvCXuJHi+SoVopgAwLQXR6SlVhDKZgAQkiaUVMu3jd0yibz/98Q4Qit/yuDSDNaGW mBxRECnt6Ftia7BPyHiJ+/JLl2bU2TcK2UIS3gYAy9vLLOuIZOrP6CVtBz11He7HCW02 DiDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=emy+se/hKalbH2tp0a4mK8E86GGOMmeQZbEu2D153u4=; b=XTfUkv1ZyhesyAqWEd7BBCc4ZFmqRE8VKvLmCiVUlf489PNeVddgApUr7DUKaOs249 lMaGx00VsmmBBMlIpFoof1EvIKuAb8/RWDAfDV5f6ATALmV5n4B0lY/2lcQjgKqrqk+u h+DFO/HW9sFCr1Ks0uW+uXwJDnbx76SCia2DpeKkJlGyGDrASjcNmsWhhk2iE8blwCi7 sJXAwn3GyTONOfVk57qxU9dTOUWxIFOi4Gp+wIrne1vqFjuiAROTCLuwgU3OvbipL1v0 bQkPlRowlY2K31NjfcEzZB4UEncnnMR4/zU8r/kRllr48UJQOhNXxhp0xLCEGzzVGkt7 36xw== X-Gm-Message-State: AOAM532ciCOVNEQEhC8l/2TwbZuobJRjGmEF3hHhQUnU/fHqfdCeNABw /dvjj/isYkd4M1R2rp5Yg0m3 X-Google-Smtp-Source: ABdhPJxZpaVR+CBbIhn1WxJ9NylF/NJ9w8C24Qx49e19NaDRtUQ07QLsCjO6Q96FB4VDSjdCkTysqg== X-Received: by 2002:a17:903:234d:b0:15d:4055:d7aa with SMTP id c13-20020a170903234d00b0015d4055d7aamr10196956plh.167.1651471600035; Sun, 01 May 2022 23:06:40 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:39 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/8] PCI: endpoint: Add BME notifier support Date: Mon, 2 May 2022 11:36:08 +0530 Message-Id: <20220502060611.58987-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to notify the EPF device about the Bus Master Enable (BME) event received by the EPC device from the Root complex. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 17 +++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 8401c2750c9e..6120d99bff73 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -731,6 +731,23 @@ void pci_epc_init_notify(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_init_notify); +/** + * pci_epc_bme_notify() - Notify the EPF device that the EPC device has received + * the BME event from the Root complex + * @epc: the EPC device that received the BME event + * + * Invoke to Notify the EPF device that the EPC device has received the Bus + * Master Enable (BME) event from the Root complex + */ +void pci_epc_bme_notify(struct pci_epc *epc) +{ + if (!epc || IS_ERR(epc)) + return; + + atomic_notifier_call_chain(&epc->notifier, BME, NULL); +} +EXPORT_SYMBOL_GPL(pci_epc_bme_notify); + /** * pci_epc_destroy() - destroy the EPC device * @epc: the EPC device that has to be destroyed diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index d346ab9ae061..8454610df4c3 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -217,6 +217,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, void pci_epc_linkup(struct pci_epc *epc); void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); +void pci_epc_bme_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index b1fcd88d0b1f..e03c57129ed5 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -21,6 +21,7 @@ enum pci_notify_event { CORE_INIT, LINK_UP, LINK_DOWN, + BME, }; enum pci_barno { From patchwork Mon May 2 06:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833878 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58787C433FE for ; Mon, 2 May 2022 06:06:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383442AbiEBGKN (ORCPT ); Mon, 2 May 2022 02:10:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357937AbiEBGKL (ORCPT ); Mon, 2 May 2022 02:10:11 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03F194FC44 for ; Sun, 1 May 2022 23:06:43 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id p8so11550062pfh.8 for ; Sun, 01 May 2022 23:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PdeJyrAXD9bV7ofsp6PZP8FNw3ldBFFBZZjktwKzfAQ=; b=JRtFD/BNr6MYu1sW228vEjCTznBOimfGyL2+KcRKKevlX4fUtx3iKfdJhDybZfdHRV 19AmptZVlYHL0z31E5nBMfsHmtxRJjez1GbFlQRd2wMpdgwD4YE3djfp1FiIKEd6NEPu gYQlKNX8fCaKqQrsg6WArJ0sSTkAab+k3SI2oGGQtYEBNURJL0dCsmD+9u4Ai5y4EShT NEibiivVkyLc0wkJRnORv0l0TQdLSit/S+lx+UNsOMRiPoa2bPPLSGU9fq0Gu3HQOtCP aTFEwROxWsvjKfJi6Lku8nfoZbrZdglKRSIfkGEIh4nebhupZ+KctbXngsnRLVkPE5q6 QeLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PdeJyrAXD9bV7ofsp6PZP8FNw3ldBFFBZZjktwKzfAQ=; b=dCOUp62NexhoFIF3RUz7EO51fJZPR13qvC8+akPZiX60yQzooL37La3v/A2AnRnOu+ fBxa9Y0RdQMsfjrckWmjUy3bteJZC1JFyZ7Lr0l3VUtkETe+wSj1Yac7X3K5u8DrucQK KhWXh7A7yW16hKUzKMjEwkipm88wjB8YDEEINI6UMFTAgCTjsrGtCA4WrGsInb5GVfnV orhxq31RVkuEjC+9e2Hu0L057CI3nS0JiWBa91Ne33FPRrfZtSpWmRxUgplrDG3NGwXH 8uTWAVMchUQn+Nq5RHZZBEX5XUqyPalz8Ei+RQolXdoaaLXUpVKtO693HZWf0xKnxBtX 0JJg== X-Gm-Message-State: AOAM531oSxm/j5nM8IkYG89YrxmPCR3O8S9WlYhMnygJX79+Zkq1ULMC PLyQly/NuD6F87Zg0E93voSJ X-Google-Smtp-Source: ABdhPJzF6Gn2GNHpVPP8zhiQVusSfdVrgtGxGamUdIIAJ+rECZ//fMTwXWWxZTJkpDF1j6Fa3l1bcw== X-Received: by 2002:a63:82c6:0:b0:3ab:2601:5e2d with SMTP id w189-20020a6382c6000000b003ab26015e2dmr8493084pgd.251.1651471603127; Sun, 01 May 2022 23:06:43 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:42 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 6/8] PCI: qcom-ep: Add support for Link down notification Date: Mon, 2 May 2022 11:36:09 +0530 Message-Id: <20220502060611.58987-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to pass Link down notification to Endpoint function driver so that the LINK_DOWN event can be processed by the function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 6ce8eddf3a37..9fb6e960f73d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -497,6 +497,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; + pci_epc_linkdown(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; From patchwork Mon May 2 06:06:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833879 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E03AFC433F5 for ; Mon, 2 May 2022 06:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234047AbiEBGK3 (ORCPT ); Mon, 2 May 2022 02:10:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383453AbiEBGKQ (ORCPT ); Mon, 2 May 2022 02:10:16 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C6624EF4D for ; Sun, 1 May 2022 23:06:47 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id s137so10973985pgs.5 for ; Sun, 01 May 2022 23:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFFLVggrg1ac+VShl7a/O0crU97cZXxJdc7Qv9e6jpo=; b=MRG6uDZiye2a9VzfSOg9GkFQs5ay31pWHHk2FPZGRApfAdH62jlvIoWohPApjbKOHo /O+QVPZE6sLqVffHfG++1ce3NAmeEPvzmU1uGkire2ZaqAQ3LWQoKIw72nQuFTEqzx69 ngOHLqxqDiNyZtIxUseAHw7OkafI+h7eAX8Z9eIlJ2sJtHK1BBmUfCKh8uEp/me5Qt3J 7nOkWE5zs6At7golyrghSvRk0or71dM3Ti4DAobUWQyIaSW/E4CVdl4vfwEd6ekDTtf4 dxqrBIFlQnGhoW3qddIXKiz1GeFexibRJzIPI0A3lREsvkO+eV0cVdqbKMOH7ITG7wNB 2aJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFFLVggrg1ac+VShl7a/O0crU97cZXxJdc7Qv9e6jpo=; b=aQ4G4yrMvS2P8mbhnf/8QMbDxaZuEB2uEkZareOtenkt4EHimfJmb115Zu7nqQvAvT Ylb3vwoCOKyaongMpzAblUYAdBUGjG1Z/dS5DGr2JIvPUFuF5khNLg35fK9f4RO0pEy6 6PFWTL7Wh64syecjOl75pDPIHSOva2GLO2/E0GBKT4+avJImi/Ct8RpL6vTuyGMUxlIy DQNDQEhKaLy5f3aRo0xN11Qc/z1xrC1N8ac2ZLpS5ValyVtqR5wivusIQV8cMIjDBpuP uq5TTLnsaLJ2ziNuJA7pyQHrMfsvsrrJd5uJnVh0RTeTMH+DmYqZsbTBrGWFICECcsC3 97pQ== X-Gm-Message-State: AOAM530pF1zGZNBdWFWxnaIZ1k8uVphfX3AS9eT5dcXXmCv/2FmUEHds zCrW+48haCIKHSZg8ozlUf29 X-Google-Smtp-Source: ABdhPJw9w/hA1X1uXcsqpbETEhCfGo2yjeVJzZGsedrGj0r7LUsHume70kvxejv+Sc5Z/teqJIEhUA== X-Received: by 2002:a63:d04a:0:b0:3c1:65f2:5d09 with SMTP id s10-20020a63d04a000000b003c165f25d09mr8574707pgi.201.1651471606339; Sun, 01 May 2022 23:06:46 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:46 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 7/8] PCI: qcom-ep: Add support for BME notification Date: Mon, 2 May 2022 11:36:10 +0530 Message-Id: <20220502060611.58987-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to pass BME (Bus Master Enable) notification to Endpoint function driver so that the BME event can be processed by the function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 9fb6e960f73d..67ec52ad87bd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -501,6 +501,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; + pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); From patchwork Mon May 2 06:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12833880 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C636C433FE for ; Mon, 2 May 2022 06:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382689AbiEBGKx (ORCPT ); Mon, 2 May 2022 02:10:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383486AbiEBGKi (ORCPT ); Mon, 2 May 2022 02:10:38 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6228051313 for ; Sun, 1 May 2022 23:06:50 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id i62so10982044pgd.6 for ; Sun, 01 May 2022 23:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qL3Xk4i7o3UQDTmWTBFhAVM3P0U5Z5danFVnlmhWQU8=; b=CtDYa+9rPrahTWxdPX13retvUVvs4Vrobf4PgFMToLII8bMacFJj+QQrgX4vZYBfdy nlJIuJYDDq7BnkZeI8YvZbnNrAl8w50yyKALZQpOmzzCSv6qbcXiC0fpXWl5dkWM/kaf Cf/aKhdFLkEtyWCj2qDSzdqupsB5KiWZf7tTUUQKj0/X+Zx46xSDnyivPzGxuQRBB0oD vPiCE8BMrPLV+4aysNAAeMgg3p+GJ8egDF3UmXe4XLTWB+N/4/LQF1GymPpYfA28Jewn eTgb9jj/nTKB/9HnLl6SYwCOoX3Rkl9LsGQff8ZdN0tXosL74xU4qjUIv+D9w1Omr+Ug IJGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qL3Xk4i7o3UQDTmWTBFhAVM3P0U5Z5danFVnlmhWQU8=; b=WZfs6lurkIgbgJfjIkM6CoyzPtRX+X+kHQDUWTg6L2J926yzK6Lz8yCi0VcRd+x51Q EuD04Fg9G24iPqdoLD3JIUajUI28iJ1cUyHa1Y3DDPZiqBBmarhOlGZlOJptHqdZKqI4 t2VYq0tdgifaHJBLFMeME6USWkuDDsn5QrQLt4Qi4Tg4Ovp77C2Vk6ZztDjoOgwItAeL fRAhotDCsxL9VT4JF/sUyjLrikeIFH+t+LgdlJJUF6Z2iORDTplPJiTcnHRoWYQarjK/ xXBWVdI7rMZnPcGhxQm3vGTaF1lpECaQFYzozxNxaLenivnoY9E+iFYBVg3bnlARett+ bBLw== X-Gm-Message-State: AOAM532/93hooo9M7QrsaHGJW4C7At4kOol3Ef++CS1JZwUMQxD8UCIb CHVdi7yXurApxmEFEES9rHzG X-Google-Smtp-Source: ABdhPJxskezcORxtvqy4ATQjhlEIvBxEON3WMDr/MmKeG4ZkcnLMaygsynDRGW7NqqhQ371q9Pyu5Q== X-Received: by 2002:a62:33c2:0:b0:50d:a588:daab with SMTP id z185-20020a6233c2000000b0050da588daabmr9610562pfz.31.1651471609629; Sun, 01 May 2022 23:06:49 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:49 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 8/8] PCI: endpoint: Add PCI Endpoint function driver for MHI bus Date: Mon, 2 May 2022 11:36:11 +0530 Message-Id: <20220502060611.58987-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCI Endpoint driver for the Qualcomm MHI (Modem Host Interface) bus. The driver implements the MHI function over PCI in the endpoint device such as SDX55 modem. The MHI endpoint function driver acts as a controller driver for the MHI Endpoint stack and carries out all PCI related activities like mapping the host memory using iATU, triggering MSIs etc... Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/Kconfig | 10 + drivers/pci/endpoint/functions/Makefile | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 436 +++++++++++++++++++ 3 files changed, 447 insertions(+) create mode 100644 drivers/pci/endpoint/functions/pci-epf-mhi.c diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig index 5f1242ca2f4e..93497fb70e31 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -25,3 +25,13 @@ config PCI_EPF_NTB device tree. If in doubt, say "N" to disable Endpoint NTB driver. + +config PCI_EPF_MHI + tristate "PCI Endpoint driver for MHI bus" + depends on PCI_ENDPOINT && MHI_BUS_EP + help + Enable this configuration option to enable the PCI Endpoint + driver for Modem Host Interface (MHI) bus found in Qualcomm + modems such as SDX55. + + If in doubt, say "N" to disable Endpoint driver for MHI bus. diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile index 96ab932a537a..eee99b2e9103 100644 --- a/drivers/pci/endpoint/functions/Makefile +++ b/drivers/pci/endpoint/functions/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o obj-$(CONFIG_PCI_EPF_NTB) += pci-epf-ntb.o +obj-$(CONFIG_PCI_EPF_MHI) += pci-epf-mhi.o diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c new file mode 100644 index 000000000000..a8119841a252 --- /dev/null +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI EPF driver for MHI Endpoint devices + * + * Copyright (C) 2022 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include + +#define MHI_VERSION_1_0 0x01000000 + +struct pci_epf_mhi_ep_info { + const struct mhi_ep_cntrl_config *config; + struct pci_epf_header *epf_header; + enum pci_barno bar_num; + u32 epf_flags; + u32 msi_count; + u32 mru; +}; + +#define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .dir = DMA_TO_DEVICE, \ + } + +#define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .dir = DMA_FROM_DEVICE, \ + } + +static const struct mhi_ep_channel_config mhi_v1_channels[] = { + MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"), + MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"), + MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"), + MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"), + MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"), + MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"), + MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"), + MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"), + MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"), + MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"), + MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"), + MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"), + MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"), + MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"), + MHI_EP_CHANNEL_CONFIG_UL(36, "IP_SW0"), + MHI_EP_CHANNEL_CONFIG_DL(37, "IP_SW0"), +}; + +static const struct mhi_ep_cntrl_config mhi_v1_config = { + .max_channels = 128, + .num_channels = ARRAY_SIZE(mhi_v1_channels), + .ch_cfg = mhi_v1_channels, + .mhi_version = MHI_VERSION_1_0, +}; + +static struct pci_epf_header sdx55_header = { + .vendorid = PCI_VENDOR_ID_QCOM, + .deviceid = 0x0306, + .baseclass_code = PCI_BASE_CLASS_COMMUNICATION, + .subclass_code = PCI_CLASS_COMMUNICATION_MODEM & 0xff, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sdx55_info = { + .config = &mhi_v1_config, + .epf_header = &sdx55_header, + .bar_num = BAR_0, + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count = 32, + .mru = 0x8000, +}; + +struct pci_epf_mhi { + const struct pci_epf_mhi_ep_info *info; + struct mhi_ep_cntrl mhi_cntrl; + struct pci_epf *epf; + struct mutex lock; + void __iomem *mmio; + resource_size_t mmio_phys; + enum pci_notify_event event; + u32 mmio_size; + int irq; + bool mhi_registered; +}; + +static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, + phys_addr_t *phys_ptr, void __iomem **virt, size_t size) +{ + struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf_mhi->epf->epc; + size_t offset = pci_addr & (epc->mem->window.page_size - 1); + void __iomem *virt_addr; + phys_addr_t phys_addr; + int ret; + + virt_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, size + offset); + if (!virt_addr) + return -ENOMEM; + + ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr, pci_addr - offset, size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, phys_addr, virt_addr, size + offset); + + return ret; + } + + *phys_ptr = phys_addr + offset; + *virt = virt_addr + offset; + + return 0; +} + +static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, + phys_addr_t phys_addr, void __iomem *virt_addr, size_t size) +{ + struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf->epc; + size_t offset = pci_addr & (epc->mem->window.page_size - 1); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr - offset); + pci_epc_mem_free_addr(epc, phys_addr - offset, virt_addr - offset, size + offset); +} + +void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector) +{ + struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf->epc; + + /* + * Vector is incremented by 1 here as the DWC core will decrement it before + * writing to iATU. + */ + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, vector + 1); +} + +int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void __iomem *to, + size_t size) +{ + struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf_mhi->epf->epc; + void __iomem *tre_buf; + phys_addr_t tre_phys; + size_t offset = from % 0x1000; + int ret; + + mutex_lock(&epf_mhi->lock); + + tre_buf = pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); + if (!tre_buf) { + mutex_unlock(&epf_mhi->lock); + return -ENOMEM; + } + + ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, from - offset, + size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_fromio(to, tre_buf + offset, size); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, void __iomem *from, u64 to, + size_t size) +{ + struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf_mhi->epf->epc; + void __iomem *tre_buf; + phys_addr_t tre_phys; + size_t offset = to % 0x1000; + int ret; + + mutex_lock(&epf_mhi->lock); + + tre_buf = pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); + if (!tre_buf) { + mutex_unlock(&epf_mhi->lock); + return -ENOMEM; + } + + ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, to - offset, + size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_toio(tre_buf + offset, from, size); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +static int pci_epf_mhi_notifier(struct notifier_block *nb, unsigned long val, void *data) +{ + struct pci_epf *epf = container_of(nb, struct pci_epf, nb); + struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info = epf_mhi->info; + struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; + struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; + int ret; + + switch (val) { + case CORE_INIT: + epf_bar->phys_addr = epf_mhi->mmio_phys; + epf_bar->size = epf_mhi->mmio_size; + epf_bar->barno = info->bar_num; + epf_bar->flags = info->epf_flags; + ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "Failed to set BAR: %d\n", ret); + return NOTIFY_BAD; + } + + ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, + order_base_2(info->msi_count)); + if (ret) { + dev_err(dev, "Failed to set MSI configuration: %d\n", ret); + return NOTIFY_BAD; + } + + ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, epf->header); + if (ret) { + dev_err(dev, "Failed to set Configuration header: %d\n", ret); + return NOTIFY_BAD; + } + + break; + case LINK_UP: + mhi_cntrl->mmio = epf_mhi->mmio; + mhi_cntrl->irq = epf_mhi->irq; + mhi_cntrl->mru = info->mru; + + /* Assign the struct dev of PCI EP as MHI controller device */ + mhi_cntrl->cntrl_dev = epc->dev.parent; + mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq; + mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map; + mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; + mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host; + mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host; + + /* Register the MHI EP controller */ + ret = mhi_ep_register_controller(mhi_cntrl, info->config); + if (ret) { + dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); + return NOTIFY_BAD; + } + + epf_mhi->mhi_registered = true; + break; + case LINK_DOWN: + if (epf_mhi->mhi_registered) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered = false; + } + + break; + case BME: + /* Power up the MHI EP stack if link is up and stack is in power down state */ + if (!mhi_cntrl->enabled && epf_mhi->mhi_registered) { + ret = mhi_ep_power_up(mhi_cntrl); + if (ret) { + dev_err(dev, "Failed to power up MHI EP: %d\n", ret); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered = false; + return NOTIFY_BAD; + } + } + + break; + default: + dev_err(&epf->dev, "Invalid MHI EP notifier event: %d\n", epf_mhi->event); + return NOTIFY_BAD; + } + + return NOTIFY_OK; +} + +static int pci_epf_mhi_bind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + struct pci_epc *epc = epf->epc; + struct platform_device *pdev = to_platform_device(epc->dev.parent); + struct device *dev = &epf->dev; + struct resource *res; + int ret; + + if (WARN_ON_ONCE(!epc)) + return -EINVAL; + + /* Get MMIO base address from Endpoint controller */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); + epf_mhi->mmio_phys = res->start; + epf_mhi->mmio_size = resource_size(res); + + epf_mhi->mmio = ioremap_wc(epf_mhi->mmio_phys, epf_mhi->mmio_size); + if (IS_ERR(epf_mhi->mmio)) + return PTR_ERR(epf_mhi->mmio); + + ret = platform_get_irq_byname(pdev, "doorbell"); + if (ret < 0) { + dev_err(dev, "Failed to get Doorbell IRQ\n"); + iounmap(epf_mhi->mmio); + return ret; + } + + epf_mhi->irq = ret; + + epf->nb.notifier_call = pci_epf_mhi_notifier; + pci_epc_register_notifier(epc, &epf->nb); + + return 0; +} + +static void pci_epf_mhi_unbind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info = epf_mhi->info; + struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; + struct pci_epc *epc = epf->epc; + + pci_epc_unregister_notifier(epc, &epf->nb); + + /* + * Forcefully power down the MHI EP stack. Only way to bring the MHI EP stack + * back to working state after successive bind is by getting BME from host. + */ + if (epf_mhi->mhi_registered) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered = false; + } + + iounmap(epf_mhi->mmio); + pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); +} + +static int pci_epf_mhi_probe(struct pci_epf *epf, const struct pci_epf_device_id *id) +{ + struct pci_epf_mhi_ep_info *info = (struct pci_epf_mhi_ep_info *) id->driver_data; + struct pci_epf_mhi *epf_mhi; + struct device *dev = &epf->dev; + + epf_mhi = devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL); + if (!epf_mhi) + return -ENOMEM; + + epf->header = info->epf_header; + epf_mhi->info = info; + epf_mhi->epf = epf; + + mutex_init(&epf_mhi->lock); + + epf_set_drvdata(epf, epf_mhi); + + return 0; +} + +static const struct pci_epf_device_id pci_epf_mhi_ids[] = { + { + .name = "sdx55", .driver_data = (kernel_ulong_t) &sdx55_info, + }, + {}, +}; + +static struct pci_epf_ops pci_epf_mhi_ops = { + .unbind = pci_epf_mhi_unbind, + .bind = pci_epf_mhi_bind, +}; + +static struct pci_epf_driver pci_epf_mhi_driver = { + .driver.name = "pci_epf_mhi", + .probe = pci_epf_mhi_probe, + .id_table = pci_epf_mhi_ids, + .ops = &pci_epf_mhi_ops, + .owner = THIS_MODULE, +}; + +static int __init pci_epf_mhi_init(void) +{ + return pci_epf_register_driver(&pci_epf_mhi_driver); +} +module_init(pci_epf_mhi_init); + +static void __exit pci_epf_mhi_exit(void) +{ + pci_epf_unregister_driver(&pci_epf_mhi_driver); +} +module_exit(pci_epf_mhi_exit); + +MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2");