From patchwork Tue May 3 20:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D16C433FE for ; Tue, 3 May 2022 20:05:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238168AbiECUJR (ORCPT ); Tue, 3 May 2022 16:09:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237803AbiECUJI (ORCPT ); Tue, 3 May 2022 16:09:08 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F7E4B879; Tue, 3 May 2022 13:05:35 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id t5so10449489edw.11; Tue, 03 May 2022 13:05:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o3MWZsx6Wz0oJnhXHc5EgYRJIPgHEoxFAS+Idrf7kxw=; b=WTjNcPu/nddUOPrhaKacXQUTLslQDS13Knv/clKmNqWtsDC/596MjJ0MVZGLyAYD+y jc5lhndBakfJW89eic7hJIwBWVaoQ2E9mHjoP1mA3MeH1vthl22N3nq08iTeJI6DKake eHYUSPQO35eeV+xYd8Bfkark0hoELMKmtWl6p+3f53dR+LODq7HqySGfxZxR0jVVLQ1w qIBc7NUEx5Sd0sdVpiiQVEFg2B/kx5jdtZMy2z4aURRFuW/QA3utTi3KSgrG1/UaUT2s PFbdbYgvlwU6zzLBteknOcx/AiKzLQHwgJ3viGkbnMRQWXRWn+hhoyiM47FuFM3TdhSx F88Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o3MWZsx6Wz0oJnhXHc5EgYRJIPgHEoxFAS+Idrf7kxw=; b=KTO9Eat3H6hM/bIyb7hSPWt15tZQB7uXJhWxx8jQcioEJcpTPd6bOKFkuPqRBM/NDR bI3CKj/S2O4jCmwRcwUjYLchx3yqwqkj1m4XU8ZpjWRoN3kCyYGQ8AMSdJQM57+NviUq 7ng52yO0cf03LuPt21MWu+w8yTu89U3x0KbkzAuG7ePrElJnrmOrp8Dmmw6L6xnKjkNp 0KSJkGWdTb1q+x/HUuW82ZZuiYgX1gzT48N8hfcSDG2nZ009K3BomlHXuuDwiid5F+cL 6mSAvTBHLTfiYDwFfOmgRMKGIICHoMUEjsI82OCHSluKuDRKPYRBKWQfszU147xyaMgo QLmA== X-Gm-Message-State: AOAM530cLa/2QqTBObz0tqMgJyE7d9iPbDrpoY+LllyiHiKuW124Dw5M HAImNmBDxcmOMm4glbF/uBg= X-Google-Smtp-Source: ABdhPJwt27N2VjqPhn9z7ncxzJJmn9AE4qeMODZgXlBMPH4QxsSqZSTfiMCiNmG52xN5Ml7jGvTg1A== X-Received: by 2002:a05:6402:1450:b0:425:e43f:7ccd with SMTP id d16-20020a056402145000b00425e43f7ccdmr19898570edx.299.1651608333643; Tue, 03 May 2022 13:05:33 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ee47-20020a056402292f00b0041d893ed437sm8688450edb.2.2022.05.03.13.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:05:33 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 1/5] dt-bindings: thermal: tsens: Add ipq8074 compatible Date: Tue, 3 May 2022 22:05:26 +0200 Message-Id: <20220503200530.4019673-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 has tsens v2.3.0 block, though unlike existing v2 IP it only uses one IRQ, so tsens v2 compatible cannot be used as the fallback. We also have to make sure that correct interrupts are set according to compatibles, so populate interrupt information per compatibles. Signed-off-by: Robert Marko --- Changes in v3: * Remove implied min/maxItem properties as pointed by Rob Changes in v2: * No need for a list in compatible check * Specify minItems and maxItems for interrupt and interrupt-names --- .../bindings/thermal/qcom-tsens.yaml | 76 ++++++++++++++++--- 1 file changed, 65 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index b6406bcc683f..23f69eead67e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -56,6 +56,10 @@ properties: - qcom,sm8350-tsens - const: qcom,tsens-v2 + - description: v2 of TSENS with combined interrupt + enum: + - qcom,ipq8074-tsens + reg: items: - description: TM registers @@ -63,15 +67,11 @@ properties: interrupts: minItems: 1 - items: - - description: Combined interrupt if upper or lower threshold crossed - - description: Interrupt if critical threshold crossed + maxItems: 2 interrupt-names: minItems: 1 - items: - - const: uplow - - const: critical + maxItems: 2 nvmem-cells: minItems: 1 @@ -124,22 +124,61 @@ allOf: then: properties: interrupts: - maxItems: 1 + items: + - description: Combined interrupt if upper or lower threshold crossed interrupt-names: - maxItems: 1 + items: + - const: uplow - else: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-tsens + - qcom,msm8996-tsens + - qcom,msm8998-tsens + - qcom,sc7180-tsens + - qcom,sc7280-tsens + - qcom,sc8180x-tsens + - qcom,sdm630-tsens + - qcom,sdm845-tsens + - qcom,sm8150-tsens + - qcom,sm8250-tsens + - qcom,sm8350-tsens + - qcom,tsens-v2 + then: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed + interrupt-names: + items: + - const: uplow + - const: critical + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-tsens + then: properties: interrupts: - minItems: 2 + items: + - description: Combined interrupt if upper, lower or critical thresholds crossed interrupt-names: - minItems: 2 + items: + - const: combined - if: properties: compatible: contains: enum: + - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 - qcom,tsens-v2 @@ -222,4 +261,19 @@ examples: #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; + + - | + #include + // Example 4 (for any IPQ8074 based SoC-s): + tsens4: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + + interrupts = ; + interrupt-names = "combined"; + + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; ... 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[88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ee47-20020a056402292f00b0041d893ed437sm8688450edb.2.2022.05.03.13.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:05:34 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 2/5] drivers: thermal: tsens: Add support for combined interrupt Date: Tue, 3 May 2022 22:05:27 +0200 Message-Id: <20220503200530.4019673-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200530.4019673-1-robimarko@gmail.com> References: <20220503200530.4019673-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for signaling both up/low and critical trips. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 1 + drivers/thermal/qcom/tsens-v0_1.c | 1 + drivers/thermal/qcom/tsens-v1.c | 1 + drivers/thermal/qcom/tsens-v2.c | 1 + drivers/thermal/qcom/tsens.c | 37 ++++++++++++++++++++++++++----- drivers/thermal/qcom/tsens.h | 2 ++ 6 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 67c1748cdf73..ee584e5b07e5 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 = { static struct tsens_features tsens_8960_feat = { .ver_major = VER_0, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 0, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index f136cb350238..6effb822bf3c 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_priv *priv) static struct tsens_features tsens_v0_1_feat = { .ver_major = VER_0_1, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 573e261ccca7..a4f561a6e582 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_priv *priv) static struct tsens_features tsens_v1_feat = { .ver_major = VER_1_X, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index b293ed32174b..129cdb247381 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -31,6 +31,7 @@ static struct tsens_features tsens_v2_feat = { .ver_major = VER_2_X, .crit_int = 1, + .combo_int = 0, .adc = 0, .srot_split = 1, .max_sensors = 16, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 154d3cb19c88..69b6f7b97e9e 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -532,6 +532,26 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) return IRQ_HANDLED; } +/** + * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Handle the combined interrupt as if it were 2 separate interrupts, so call the + * critical handler first and then the up/low one. + * + * Return: IRQ_HANDLED + */ +static irqreturn_t tsens_combined_irq_thread(int irq, void *data) +{ + irqreturn_t ret; + + ret = tsens_critical_irq_thread(irq, data); + ret = tsens_irq_thread(irq, data); + + return ret; +} + static int tsens_set_trips(void *_sensor, int low, int high) { struct tsens_sensor *s = _sensor; @@ -1080,13 +1100,18 @@ static int tsens_register(struct tsens_priv *priv) tsens_mC_to_hw(priv->sensor, 0)); } - ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); - if (ret < 0) - return ret; + if (priv->feat->combo_int) { + ret = tsens_register_irq(priv, "combined", + tsens_combined_irq_thread); + } else { + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); + if (ret < 0) + return ret; - if (priv->feat->crit_int) - ret = tsens_register_irq(priv, "critical", - tsens_critical_irq_thread); + if (priv->feat->crit_int) + ret = tsens_register_irq(priv, "critical", + tsens_critical_irq_thread); + } return ret; } diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 1471a2c00f15..4614177944d6 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -495,6 +495,7 @@ enum regfield_ids { * struct tsens_features - Features supported by the IP * @ver_major: Major number of IP version * @crit_int: does the IP support critical interrupts? + * @combo_int: does the IP use one IRQ for up, low and critical thresholds? * @adc: do the sensors only output adc code (instead of temperature)? * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? @@ -504,6 +505,7 @@ enum regfield_ids { struct tsens_features { unsigned int ver_major; unsigned int crit_int:1; + unsigned int combo_int:1; unsigned int adc:1; unsigned int srot_split:1; unsigned int has_watchdog:1; From patchwork Tue May 3 20:05:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B6E2C433EF for ; Tue, 3 May 2022 20:05:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238084AbiECUJR (ORCPT ); Tue, 3 May 2022 16:09:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238111AbiECUJM (ORCPT ); Tue, 3 May 2022 16:09:12 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CF0D17A9C; Tue, 3 May 2022 13:05:38 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id g20so21064447edw.6; Tue, 03 May 2022 13:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=S7mbVu6+3bbSuyR9MBMSh10cZl+yedOVDmkIw2pNMHgBBw1iblztjezZ0R7KkCa/Z+ bDvzGlXeUzzQ9EpmVOfyp61y9NY+jm6ROSi+EQkGPfv5ylgvVSLqe16kXmSPHCaGvdyQ I4+zIBIRS4QdtoClkqkIYeuXq1MvrWi2BzzFbuITPDdxbxNBDWpnWjz9M3w9POvpmxkB lojzM/Z8xicb/X4DZOVsPleus9oNkfn+VHlP//XYSmGxtGazkzGgW1XUZzw7sBqsFaTC lViGiz0/Srh+gxW3ImGx8sqGNk7xwXsMT2hx5pnJhUjMq5+Tj0CUDv5gwsZACjo56pqS eImg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=5BK0KP3Ub5dow+vouxIBDQXOcyWBpSxpGcdzTtOBPzba/pofeNfKSnXxzGRh1/c5SP B+4hMKGu2kWaeu/R1V7O6JcwWxIv9smKg0a+ql6ansZEbFPAKBbrmlr8R24mHGzOccAh EruuWR8sTsN5RGLLVLifsGYSAsKDtpvQhdc5J3/ucXCrbhFRF+RHEJ2Wve7Sy8Q0WzoB n6OICJMSHaThouEXwoEXSP4E7q4J7dS+TsUj9ll9mfoE1+W+9eMZFEwyaLsNLNSq2rm8 qAeat7ORWEPv0JR1Y8idTVg+zTROniT7/FknrcCgolNqYLy/6Wm348KH8FxVc6MXAwtx nfYw== X-Gm-Message-State: AOAM530jvqTSBRkeG42tS9vOBc7SJNmRot/o6On9fK9PPzee4e1C8MKm XRFKRYuKBLAWK+fX4SVsGO4= X-Google-Smtp-Source: ABdhPJw0E3FIvglNgN66EYv5teb9pu7TDi7cQ2ljqDL5wBNZ+kedyY2qYnnpA1CKfQihjG1Lp/e/wg== X-Received: by 2002:a05:6402:1a42:b0:424:20bb:3e37 with SMTP id bf2-20020a0564021a4200b0042420bb3e37mr20164328edb.29.1651608337002; Tue, 03 May 2022 13:05:37 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ee47-20020a056402292f00b0041d893ed437sm8688450edb.2.2022.05.03.13.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:05:36 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 3/5] drivers: thermal: tsens: allow configuring min and max trips Date: Tue, 3 May 2022 22:05:28 +0200 Message-Id: <20220503200530.4019673-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200530.4019673-1-robimarko@gmail.com> References: <20220503200530.4019673-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 and IPQ6018 dont support negative trip temperatures and support up to 204 degrees C as the max trip temperature. So, instead of always setting the -40 as min and 120 degrees C as max allow it to be configured as part of the features. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 2 ++ drivers/thermal/qcom/tsens-v0_1.c | 2 ++ drivers/thermal/qcom/tsens-v1.c | 2 ++ drivers/thermal/qcom/tsens-v2.c | 2 ++ drivers/thermal/qcom/tsens.c | 4 ++-- drivers/thermal/qcom/tsens.h | 4 ++++ 6 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index ee584e5b07e5..4585904fb380 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_feat = { .adc = 1, .srot_split = 0, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; struct tsens_plat_data data_8960 = { diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6effb822bf3c..2c203ff374e6 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a4f561a6e582..1d7f8a80bd13 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 129cdb247381..9babc69bfd22 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_feat = { .adc = 0, .srot_split = 1, .max_sensors = 16, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 69b6f7b97e9e..b7701d5efdfc 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor, int low, int high) dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); - cl_high = clamp_val(high, -40000, 120000); - cl_low = clamp_val(low, -40000, 120000); + cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp); + cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp); high_val = tsens_mC_to_hw(s, cl_high); low_val = tsens_mC_to_hw(s, cl_low); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4614177944d6..747004476347 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -501,6 +501,8 @@ enum regfield_ids { * with SROT only being available to secure boot firmware? * @has_watchdog: does this IP support watchdog functionality? * @max_sensors: maximum sensors supported by this version of the IP + * @trip_min_temp: minimum trip temperature supported by this version of the IP + * @trip_max_temp: maximum trip temperature supported by this version of the IP */ struct tsens_features { unsigned int ver_major; @@ -510,6 +512,8 @@ struct tsens_features { unsigned int srot_split:1; unsigned int has_watchdog:1; unsigned int max_sensors; + int trip_min_temp; + int trip_max_temp; }; /** From patchwork Tue May 3 20:05:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBD8AC35274 for ; Tue, 3 May 2022 20:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237437AbiECUJQ (ORCPT ); Tue, 3 May 2022 16:09:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238116AbiECUJO (ORCPT ); Tue, 3 May 2022 16:09:14 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E88371A81F; Tue, 3 May 2022 13:05:40 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id i19so35408239eja.11; Tue, 03 May 2022 13:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=FPw/kgO3kRxUOvJ0Ls1YbCPnbUV0Dd4LhhhhKMQUfqqdPhWAEwQ8MvItKLDjxiQPXp FkYVY2Q3hQ4ykRgNYJidQICznTbsRdSP9+iCS0mdV8p3fjm+Y4H1zcI+bYasgU+Yu8e9 bE5iP/nySKJktmYKqC4+Iys2cpZKL7OjaazAy7UQUHsNFfESmdjFgOw336gyXUiTbpIS pdh8Bks7jH+ELJca9EF6IHeiTltBVF4KY8L41hAwrmS/m5SUUIhpBqV/ZB7x2iZ90R9h KyWGiPtIfwmxRFiwWRvCHOHUO9P7s7cni8or6PfEnbomkD8kp1RnEtkGh+KCYb2GiEGO rA1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=2Ggxcfw7LxNB07jyGSoON9fDh+Of9NYlHYg1Tg53WV0z0eTq2GIpNTupFsYFWFg9f1 V8ZxDbQSsoqaNRrlvxhxLPCzdxXXhCrUHLNX+ARTEB4mUFscYk0kMlbjJgvsEWREwb0D 4LO8RdyhZZXUkK8VRzLYUaiH2bUtBltmG0ya306+C7rfz04frKpkQsJPztw1zTGd0Yt9 4JbqrF0A8Nxh6QslvuUldyl6kmH+v5T94iPYO7vjreFczxQExlAD2hP+PQt7perb99Zt t3RSDG2CdTjrYLl9JlYCm6iHXQxvBFPOUYhWovUhxtM5Us2FUKearr7LTwtapCqc3QSO 7oTQ== X-Gm-Message-State: AOAM53059xndyPErvAzY6EFzu3XKe3WyOSqH9ihqD0ojDK74vSQM1yYX /Cdn9TTqweK9sev49nljAJo= X-Google-Smtp-Source: ABdhPJy97wcx2+LQYk1Z0yYUYdRE+FDtycigEOVnhsq0UROZnJzxl30FOcTr/0vzDwv23e42Kw1AXA== X-Received: by 2002:a17:907:7d89:b0:6f3:ef24:ddd2 with SMTP id oz9-20020a1709077d8900b006f3ef24ddd2mr17109585ejc.550.1651608339476; Tue, 03 May 2022 13:05:39 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ee47-20020a056402292f00b0041d893ed437sm8688450edb.2.2022.05.03.13.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:05:38 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 4/5] drivers: thermal: tsens: add IPQ8074 support Date: Tue, 3 May 2022 22:05:29 +0200 Message-Id: <20220503200530.4019673-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200530.4019673-1-robimarko@gmail.com> References: <20220503200530.4019673-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP it only has one IRQ, that is used for up/low as well as critical. It also does not support negative trip temperatures. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 9babc69bfd22..29a61d2d6ca3 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_feat = { .trip_max_temp = 120000, }; +static struct tsens_features ipq8074_feat = { + .ver_major = VER_2_X, + .crit_int = 1, + .combo_int = 1, + .adc = 0, + .srot_split = 1, + .max_sensors = 16, + .trip_min_temp = 0, + .trip_max_temp = 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = { .fields = tsens_v2_regfields, }; +struct tsens_plat_data data_ipq8074 = { + .ops = &ops_generic_v2, + .feat = &ipq8074_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b7701d5efdfc..3624daaaf34b 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -990,6 +990,9 @@ static const struct of_device_id tsens_table[] = { { .compatible = "qcom,ipq8064-tsens", .data = &data_8960, + }, { + .compatible = "qcom,ipq8074-tsens", + .data = &data_ipq8074, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 747004476347..8dd990d944ad 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; extern struct tsens_plat_data data_tsens_v1, data_8976; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */ From patchwork Tue May 3 20:05:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED15DC433F5 for ; Tue, 3 May 2022 20:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238240AbiECUJV (ORCPT ); Tue, 3 May 2022 16:09:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237460AbiECUJQ (ORCPT ); Tue, 3 May 2022 16:09:16 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A0E21A81F; Tue, 3 May 2022 13:05:42 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id n10so18050684ejk.5; Tue, 03 May 2022 13:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=Pe5LGI4BFACdp0284FSLxeZMpgqgM2fUgE66SGVSEi1UAfeWVoTIPO3yoZVP4T9T1V oKjbecVh+r/wwdXtuMY2ZtKR459i/rBLbT15m+pWubmtT5bV8BtQq+gt5g6cybCTQccD qsdne7RyOwG0TliV6yGD316wsdaPuJk6AAinLCTOEHkSyPisenzsb713Niqi/h/Tu4Ix QG0Fn+pnkBKntzIdJAFhybZeFatIclfXCEtTqmzgusec/CIt06UlzcwIKRJYrYfuWxxb 8OVC+1/m0SVTVREEqD+NHtZ4koNTZqLcnwILMOHHXMHnNJNUMDhxdT2qvl2aXkyVbqtO 6/DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=Wx/m03Og2Rv1hWgNfcF+QgOR89QR4pHMJzgA2tanQzyoq6gYw273MCEX/BjJAPtkA3 pZB0fZAZR5K4sY1cq/uRXw8fVUArGugWlU3i8YbhtRHLrs+Oy4eEVe4PZvHfEkwSZMnn /aZ/2DxCNUtwdRypxOB3n+Lw3eyXRrYhCNJ84k4pRG7xmtFdXw/0qVQCFjum496lamDQ wqJZsgPgs4bE1A5RmUBCtQNbXlVwpS87BmDAPWz+VQkqR0TYb19AiYfqf3KYea1haK/O pJe/ZeLMnkFbt6NA3rprABNQl5o6eMBouucByYle3M14GdtyIKAht14c83te/ZdLhKBZ h/AA== X-Gm-Message-State: AOAM5312assnsMBI+Wcv7Sm2ejg7bC9cUF+/v7Cn4TCT+yaRFCjBKysB yxD/nApx7xMZ7zvLeDFq45Y= X-Google-Smtp-Source: ABdhPJzvZ/B7Fl5zFKE2FPIj0VQCrTfJuai2JKU5rC5U0RRAS8CECpwZwz/oVn9LGxPLQdeUyjmzFg== X-Received: by 2002:a17:907:97cc:b0:6da:a8fb:d1db with SMTP id js12-20020a17090797cc00b006daa8fbd1dbmr17406488ejc.267.1651608341185; Tue, 03 May 2022 13:05:41 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ee47-20020a056402292f00b0041d893ed437sm8688450edb.2.2022.05.03.13.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:05:40 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 5/5] arm64: dts: ipq8074: add thermal nodes Date: Tue, 3 May 2022 22:05:30 +0200 Message-Id: <20220503200530.4019673-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200530.4019673-1-robimarko@gmail.com> References: <20220503200530.4019673-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index afbae86cf6d3..76e02490b968 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -332,6 +332,16 @@ prng: rng@e3000 { status = "disabled"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; @@ -1092,4 +1102,90 @@ wifi: wifi@c0000000 { status = "disabled"; }; }; + + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + }; + + nss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + }; + + nss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + }; + + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 11>; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 12>; + }; + + cluster_thermal: cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 13>; + }; + + wcss-phyb0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 14>; + }; + + wcss-phyb1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 15>; + }; + }; };