From patchwork Tue May 3 21:22:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836346 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C87C43217 for ; Tue, 3 May 2022 21:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242751AbiECV1E (ORCPT ); Tue, 3 May 2022 17:27:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242779AbiECV1D (ORCPT ); Tue, 3 May 2022 17:27:03 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 61F3A41627; Tue, 3 May 2022 14:23:27 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 0929616D1; Wed, 4 May 2022 00:24:00 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 0929616D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613040; bh=7HFHf4H6BqchalrRsFSaOiF5MajsEXQSmhrKvpdLbKA=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=LMiWvfyrl3fc3bZAjEGczclR1fSYLQelohqyjK7ydhOVZcFM4Lh5qCByoR2BY251A JiJw+TTdx/Fe3k9gmAXK/rz2CIZGBWzMkqLh9aDgV+pmvm1Y3awUTW+jlXRKRGva1J QdE5dUzTkW7XwGa6s7cyjhxplKJVPTe4nYkuVET0= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:26 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 01/13] PCI: dwc: Stop link in the host init error and de-initialization Date: Wed, 4 May 2022 00:22:48 +0300 Message-ID: <20220503212300.30105-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It's logically correct to undo everything what was done in case of an error is discovered or in the corresponding cleanup counterpart. Otherwise the host controller will be left in an undetermined state. Seeing the link is set up in the Host-initialization method it will be right to de-activate it there in the cleanup-on-error block and stop the link in the antagonistic routine - dw_pcie_host_deinit(). The link de-activation is a platform-specific thing and is supposed to be implemented in the framework of the dw_pcie_ops.stop_link() operation. Fixes: 886a9c134755 ("PCI: dwc: Move link handling into common code") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-host.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..7403b1709726 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -420,8 +420,14 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->sysdata = pp; ret = pci_host_probe(bridge); - if (!ret) - return 0; + if (ret) + goto err_stop_link; + + return 0; + +err_stop_link: + if (pci->ops && pci->ops->stop_link) + pci->ops->stop_link(pci); err_free_msi: if (pp->has_msi_ctrl) @@ -432,8 +438,14 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + pci_stop_root_bus(pp->bridge->bus); pci_remove_root_bus(pp->bridge->bus); + + if (pci->ops && pci->ops->stop_link) + pci->ops->stop_link(pci); + if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); } From patchwork Tue May 3 21:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836345 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 995E9C433F5 for ; Tue, 3 May 2022 21:23:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242782AbiECV1D (ORCPT ); Tue, 3 May 2022 17:27:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242680AbiECV1C (ORCPT ); Tue, 3 May 2022 17:27:02 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2302B41620; Tue, 3 May 2022 14:23:28 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 1BDC316D6; Wed, 4 May 2022 00:24:01 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 1BDC316D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613041; bh=Go84IpXAHFc/LHfNIGML74WiUTZQAGtam3QAbp3gIcA=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=hC1h+s6lUcMej3QMN3IZ5hi8934q6hGjsUK+kwJIrf7WvkD6fUk5JCIRn5jNYxz/Y uUZm1+zi4T84Fj2rw71ehAR+jX0FgeZtA+IMUvryBSzk597q4yqPM8UzuvAuztnUij LAr0bxtRNkumsWFddGNF1V5u9UiJ13sbVB6q5i4Q= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:27 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 02/13] PCI: dwc: Don't use generic IO-ops for DBI-space access Date: Wed, 4 May 2022 00:22:49 +0300 Message-ID: <20220503212300.30105-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") replaced the locally defined DW PCIe host controller config-space accessors with the generic methods pci_generic_config_read() and pci_generic_config_write(). It was intended that the corresponding bus-mapping callback returned a correct virtual address of the passed PCI config-space register. The problem of the proposed solution was that it didn't take into account the way the host config-space is accessed on the DW PCIe. Depending on the DW PCIe IP-core synthesize parameters different interfaces can be used to access the host and peripheral config/memory spaces. The former one can be accessed via the DBI interface, while the later ones is reached via the AHB/AXI application bus. In case if the DW PCIe controller is configured to have a dedicated DBI interface, the way it is mapped into the IO-memory turns to be platform-specific. For such setups the DWC PCIe driver provides a set of the callbacks dw_pcie_ops.{read_dbi,write_dbi} so the platforms glue-drivers would be able to take into account the DBI bus IO peculiarities. Since commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") these methods haven't been utilized during the generic host initialization performed by the PCIe subsystem code. I don't really know how come there have been no problems spotted for the Histb/Exynos/Kirin PCIe controllers so far, but in our case with dword aligned IO requirement the generic config-space accessors can't be utilized for the host config-space. Thus in order to make sure the host config-space is properly accessed via the DBI bus let's get back the dw_pcie_rd_own_conf() and dw_pcie_wr_own_conf() methods. They are going to be just wrappers around the already defined dw_pcie_read_dbi()/dw_pcie_write_dbi() functions with proper arguments conversion. These methods perform the platform-specific config-space IO if the DBI accessors are specified, otherwise they call normal MMIO operations. Fixes: c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") Signed-off-by: Serge Semin --- .../pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7403b1709726..a250869334a5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -534,10 +534,40 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) { + *val = ~0U; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val = dw_pcie_read_dbi(pci, where, size); + + return PCIBIOS_SUCCESSFUL; +} + +static int dw_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + + return PCIBIOS_SUCCESSFUL; +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, - .read = pci_generic_config_read, - .write = pci_generic_config_write, + .read = dw_pcie_rd_own_conf, + .write = dw_pcie_wr_own_conf, }; void dw_pcie_setup_rc(struct pcie_port *pp) From patchwork Tue May 3 21:22:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836348 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB299C4332F for ; Tue, 3 May 2022 21:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237718AbiECV1F (ORCPT ); Tue, 3 May 2022 17:27:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242778AbiECV1D (ORCPT ); Tue, 3 May 2022 17:27:03 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5EED44162D; Tue, 3 May 2022 14:23:29 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 1D88916D7; Wed, 4 May 2022 00:24:02 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 1D88916D7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613042; bh=OoVanQ5yHiv0xhE+4SxgGCL4ZPscVZSKRi+k0Dp0Pu4=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=WqBBT8V8GSa1uspDANgO6tEUvItY/vR2mDUUYUKXlQ2MYY4RxD4s6khMFjAAGfBnk zZQSuLOybikWFNaE2kXhov4SHm6QSQlBK1RBxT+a2puFtE/svh5UCZqw1akhtfIL9m xuod+aruFyQtmoKsqEe4hN5Je4tm5wypqeTkyXUI= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:28 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 03/13] PCI: dwc: Add unroll iATU space support to the regions disable method Date: Wed, 4 May 2022 00:22:50 +0300 Message-ID: <20220503212300.30105-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f ("PCI: dwc: designware: Add EP mode support"). Since then it hasn't changed at all. For all that time the method has supported the viewport version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores older than v4.80a since the newer controllers are equipped with the unrolled iATU/eDMA space. It means the methods using it like pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work correctly for the DW PCIe controllers with unrolled iATU CSRs. The same concerns the dw_pcie_setup_rc() method, which disables the outbound iATU entries before re-initializing them. So in order to fix the problems denoted above let's convert the dw_pcie_disable_atu() method to disabling the iATU inbound and outbound regions in the unrolled iATU CSRs in case the DW PCIe controller has been synthesized with the ones support. The former semantics will be remained for the controller having iATU mapped over the viewport. Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Reported-by: kernel test robot --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d92c8a25094f..7dc8c360a0d4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, return; } - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + if (pci->iatu_unroll_enabled) { + if (region == PCIE_ATU_REGION_INBOUND) { + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } else { + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } + } else { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + } } int dw_pcie_wait_for_link(struct dw_pcie *pci) From patchwork Tue May 3 21:22:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836347 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 279F6C43219 for ; Tue, 3 May 2022 21:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242804AbiECV1F (ORCPT ); Tue, 3 May 2022 17:27:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242786AbiECV1D (ORCPT ); Tue, 3 May 2022 17:27:03 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 21CB74161F; Tue, 3 May 2022 14:23:30 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 2A7C516D8; Wed, 4 May 2022 00:24:03 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 2A7C516D8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613043; bh=XYnO1lsXXAnMSVaqJeTDa7D3vkcagfwfusr5cHoPFV8=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=b9ADFNQvh1+CWQT95JVYQ2DwJoirsRwnoy3vZOdELAvbW6FcKEo++HPD9rsxdsfbL 5zPzDoUZAbwMZTs1Dkt66yl4tKYHHrh0ZYmSdaB/FkbE/kEMESwlt8mQ3uaadmPz8u feWpbgsa2OVD8D51bvIPxaeoxjp2g6p2NulDbbHA= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:29 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 04/13] PCI: dwc: Disable outbound windows for controllers with iATU Date: Wed, 4 May 2022 00:22:51 +0300 Message-ID: <20220503212300.30105-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In accordance with the dw_pcie_setup_rc() method semantics and judging by what the comment added in commit dd193929d91e ("PCI: designware: Explain why we don't program ATU for some platforms") states there are DWC PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU enabled and use it's own address translation approach implemented. In these cases at the very least there is no point in touching the DW PCIe iATU CSRs. Moreover depending on the vendor-specific address translation implementation it might be even erroneous. So let's move the iATU windows disabling procedure to being under the corresponding conditional statement clause thus performing that procedure only if the iATU is expected to be available on the platform. Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a250869334a5..4e5c89c19f78 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -572,7 +572,6 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { - int i; u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -623,19 +622,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); - /* Ensure all outbound windows are disabled so there are multiple matches */ - for (i = 0; i < pci->num_ob_windows; i++) - dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); - /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { - int atu_idx = 0; + int i, atu_idx = 0; struct resource_entry *entry; + /* + * Ensure all outbound windows are disabled so there are + * multiple matches + */ + for (i = 0; i < pci->num_ob_windows; i++) + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); + /* Get last memory resource entry */ resource_list_for_each_entry(entry, &pp->bridge->windows) { if (resource_type(entry->res) != IORESOURCE_MEM) From patchwork Tue May 3 21:22:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836349 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4349EC433EF for ; Tue, 3 May 2022 21:23:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242817AbiECV1G (ORCPT ); Tue, 3 May 2022 17:27:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242799AbiECV1F (ORCPT ); Tue, 3 May 2022 17:27:05 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6279541620; Tue, 3 May 2022 14:23:31 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 2AE8216DA; Wed, 4 May 2022 00:24:04 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 2AE8216DA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613044; bh=D8s4kkAaMIVtZOOq7LxKW6V3CsdUxny+ktG1+sp0I80=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=a5fr0Paw9piakX2d30BiZCXR/w2GqYURaiGLQhXKIMumZnDzOIz8YNWYiGFhIa/Cz tppZf5QfT54pCNTSqWqVWA7CzVm38xkEECgro5GWot9zCVP0VN3fvWLsqH9f5gSZeO pYaShBC4OVuKqAlZ0tdIoXWcSSG3DTkU2cjdWBv0= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:30 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Pankaj Dubey , Shradha Todi CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 05/13] PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address Date: Wed, 4 May 2022 00:22:52 +0300 Message-ID: <20220503212300.30105-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It was wrong to use the region size parameter in order to determine whether the INCREASE_REGION_SIZE flag needs to be set for the outbound iATU entry because in general there are cases when combining a region base address and size together produces the out of bounds upper range limit while upper_32_bits(size) still returns zero. So having a region size within the permitted values doesn't mean the region limit address will fit to the corresponding CSR. Here is the way iATU calculates the in- and outbound untranslated regions if the INCREASE_REGION_SIZE flag is cleared [1]: Start address: End address: 63 31 0 63 31 0 +---------------+---------------+ +---------------+---------------+ | | | 0s | | | | Fs | +---------------+---------------+ +---------------+---------------+ upper base | lower base !upper! base | limit address address address address So the region start address is determined by the iATU lower and upper base address registers, while the region upper boundary is calculated based on the 32-bits limit address register and the upper part of the base address. In accordance with that logic for instance the range 0xf0000000 @ 0x20000000 does have the size smaller than 4GB, but the actual limit address turns to be invalid forming the untranslated address map as [0xf0000000; 0x1000FFFF], which isn't what the original range was. In order to fix that we need to check whether the size after being added to the lower part of the base address causes the 4GB range overflow. If it does then we need to set the INCREASE_REGION_SIZE flag thus activating the extended limit address by means of an additional iATU CSR (upper limit address register) [2]: Start address: End address: 63 31 0 63 x 31 0 +---------------+---------------+ +---------------+---------------+ | | | 0s | | | | | Fs | +---------------+---------------+ +---------------+---------------+ upper base | lower base upper | upper | limit address address address base | limit | address|address| Otherwise there is enough room in the 32-bits wide limit address register, and the flag can be left unset. Note the case when the size-based flag setting approach is correct implies requiring to have the size-aligned base addresses only. But that constraint isn't relevant to the PCIe ranges accepted by the kernel. There is also no point in implementing it either seeing the problem can be easily fixed by checking the whole limit address instead of the region size. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-36, p.175 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-37, p.176 Fixes: 5b4cf0f65324 ("PCI: dwc: Add upper limit address for outbound iATU") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- Changelog v2: - Fix the end address in the example of the patch log. It should be 0x1000FFFF and not 0x0000FFFF (@Manivannan). --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 7dc8c360a0d4..d737af058903 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -287,8 +287,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr)); val = type | PCIE_ATU_FUNC_NUM(func_no); - val = upper_32_bits(size - 1) ? - val | PCIE_ATU_INCREASE_REGION_SIZE : val; + if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr)) + val |= PCIE_ATU_INCREASE_REGION_SIZE; if (pci->version == 0x490A) val = dw_pcie_enable_ecrc(val); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val); @@ -315,6 +315,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, u64 pci_addr, u64 size) { u32 retries, val; + u64 limit_addr; if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); @@ -325,6 +326,8 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, return; } + limit_addr = cpu_addr + size - 1; + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index); dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, @@ -332,17 +335,18 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, upper_32_bits(cpu_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, - lower_32_bits(cpu_addr + size - 1)); + lower_32_bits(limit_addr)); if (pci->version >= 0x460A) dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT, - upper_32_bits(cpu_addr + size - 1)); + upper_32_bits(limit_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(pci_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(pci_addr)); val = type | PCIE_ATU_FUNC_NUM(func_no); - val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ? - val | PCIE_ATU_INCREASE_REGION_SIZE : val; + if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && + pci->version >= 0x460A) + val |= PCIE_ATU_INCREASE_REGION_SIZE; if (pci->version == 0x490A) val = dw_pcie_enable_ecrc(val); dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val); From patchwork Tue May 3 21:22:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836353 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D94CC433F5 for ; Tue, 3 May 2022 21:24:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242888AbiECV1W (ORCPT ); Tue, 3 May 2022 17:27:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242807AbiECV1G (ORCPT ); Tue, 3 May 2022 17:27:06 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 50CF041628; Tue, 3 May 2022 14:23:32 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 4C90D16D1; Wed, 4 May 2022 00:24:05 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 4C90D16D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613045; bh=4OLkEPnNiaEYM2Le/qmF6TkXVnEMMKdL6uK97mFME5Y=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=eN16idtFtSgSZMQPsnxUgL+JvjevtGUBpGQ3Rg8C97ZRLUb4f8J3Nwnsga6Ra5CJy 1NSyXJzuzbnXzss9NBbQn04eY2nZ0H/o4eHBneZOHfdj7tC/jXlJ+pOMstNen/bGXO wznZ6/Vpsjmog7HfzreJ9hCjOUf3TpNc61AojtfU= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:31 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 06/13] PCI: dwc: Add braces to the multi-line if-else statements Date: Wed, 4 May 2022 00:22:53 +0300 Message-ID: <20220503212300.30105-7-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In accordance with [1] if there is at least one multi-line if-else clause in the statement, then each clause will need to be surrounded by the braces. The driver code violates that coding style rule in a few places. Let's fix it. [1] Documentation/process/coding-style.rst Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0eda8236c125..7c9315fffe24 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -699,9 +699,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (!pci->dbi_base2) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); - if (!res) + if (!res) { pci->dbi_base2 = pci->dbi_base + SZ_4K; - else { + } else { pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base2)) return PTR_ERR(pci->dbi_base2); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d737af058903..9f4d2b44612b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -699,8 +699,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) pci->atu_size = SZ_4K; dw_pcie_iatu_detect_regions_unroll(pci); - } else + } else { dw_pcie_iatu_detect_regions(pci); + } dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); From patchwork Tue May 3 21:22:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836350 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E43ECC433EF for ; Tue, 3 May 2022 21:23:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242936AbiECV1X (ORCPT ); Tue, 3 May 2022 17:27:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242863AbiECV1W (ORCPT ); Tue, 3 May 2022 17:27:22 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 691CE41632; Tue, 3 May 2022 14:23:33 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 5E05C16D6; Wed, 4 May 2022 00:24:06 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 5E05C16D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613046; bh=1LEzq7uEU4+vzq4sUsHD/tXEJkpmJ5noJd8Q4gwxeW0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Wm8lntYhHD+s0DZu0M6heTk/HA+0VKSZTEafivcsfmtOgeE5OigbvIDEgpSutpCYo cHRaCxkNTr5Vp380O06v5yjs0YwbM1vr/BVeURebWcx6g5+o6F3ebwm0sp3X4CTK4l wsxMLL/PnsmJbMtYOTEdRprw9q2DPfqjA5VPTthw= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:32 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 07/13] PCI: dwc: Add trailing new-line literals to the log messages Date: Wed, 4 May 2022 00:22:54 +0300 Message-ID: <20220503212300.30105-8-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There are two places in the DW PCIe controller driver, which omit the trailing newlines in the log info and warn messages. Not having them there will cause leaving the messages in the printk ring buffer until a next '\n'-terminated message is printed (it will consequently cause the buffer flush). As it isn't what the corresponding code implies let's add the new-line characters in the messages. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 4e5c89c19f78..1c815d3bead9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -662,7 +662,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) } if (pci->num_ob_windows <= atu_idx) - dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)", + dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n", pci->num_ob_windows); } diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 9f4d2b44612b..3bd1cfd12148 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -706,7 +706,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); - dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound", + dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound\n", pci->num_ob_windows, pci->num_ib_windows); } From patchwork Tue May 3 21:22:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836356 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5898C4321E for ; Tue, 3 May 2022 21:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240888AbiECV1d (ORCPT ); Tue, 3 May 2022 17:27:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242868AbiECV1W (ORCPT ); Tue, 3 May 2022 17:27:22 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0E2D441638; Tue, 3 May 2022 14:23:33 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 721B916A9; Wed, 4 May 2022 00:24:07 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 721B916A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613047; bh=aZ0FrYvdbbu8Dgya3SIuok2wzI17oaJMGYt84OA6t2M=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Dq+bMEOBAp03ImhYsN36vwLB7KNT6XscOGIA5ZkvC7yyu2PQ7oBviPa2uxdZtchgD wX4S5CgbPWmJqd86jjWrdstUV4rkeEBEaVVOuvnxfz1CHnVEe9nd196kqVQIoozhv5 gG4fanaoJPSz3UvacvAJQ8qLRTo+nhzgt0Qwy9rE= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:33 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 08/13] PCI: dwc: Discard IP-core version checking on unrolled iATU detection Date: Wed, 4 May 2022 00:22:55 +0300 Message-ID: <20220503212300.30105-9-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It's pretty much pointless. Even though unrolled version of the internal ATU has been indeed available since DWC PCIe v4.80a IP-core, there is no guarantee it was enabled during the IP-core configuration (Synopsys suggests to contact the Solvnet support for guidance of how to do that for the newer IP-cores). So the only reliable way to find out the unrolled iATU feature availability is indeed to check the iATU viewport register content. In accordance with the reference manual [1] if the register doesn't exist (unrolled iATU is enabled) it's content is fixed with 0xff-s, otherwise it will contain some zeros. So we can freely drop the IP-core version checking in this matter then and use the dw_pcie_iatu_unroll_enabled() method only to detect whether iATU/eDMA space is unrolled. [1] DesignWare Cores, PCI Express Controller, Register Desciptions, v.4.90a, December 2016, p.855 Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3bd1cfd12148..e3d2c11e6998 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -600,15 +600,15 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) } -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) { u32 val; val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); if (val == 0xffffffff) - return 1; + return true; - return 0; + return false; } static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci) @@ -680,9 +680,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); - if (pci->version >= 0x480A || (!pci->version && - dw_pcie_iatu_unroll_enabled(pci))) { - pci->iatu_unroll_enabled = true; + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + if (pci->iatu_unroll_enabled) { if (!pci->atu_base) { struct resource *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); From patchwork Tue May 3 21:22:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836354 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6801BC4332F for ; Tue, 3 May 2022 21:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242874AbiECV1d (ORCPT ); Tue, 3 May 2022 17:27:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242878AbiECV1W (ORCPT ); Tue, 3 May 2022 17:27:22 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1BB5141627; Tue, 3 May 2022 14:23:34 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 5F12416D8; Wed, 4 May 2022 00:24:08 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 5F12416D8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613048; bh=9PcRuQEaH+jvkJWJj0pj6vOsFD3ddTPPKALUi/ORWCk=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=alkGb13GFTu62m73PN6DWszLWlNGDaXOPk54J5Ka0fmp7wsrivcGQXar1aoSRZkkG zQ23EHvEUdZLKLy3WuditcWWHtici0t/JpaZ3DnON0IUrQQVIo6yH9njrRcgz/CUij WP6NpC05FnIrF3a/+CdT4Yvfad09vElMxueqggDM= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:34 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 09/13] PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi() Date: Wed, 4 May 2022 00:22:56 +0300 Message-ID: <20220503212300.30105-10-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org While the rest of the generic DWC PCIe code is using the dedicated IO-mem accessors, the dw_pcie_link_up() method for some unobvious reason directly calls readl() to get PortLogic.DEBUG1 register content. Since the way the dbi-bus is accessed can be platform-specific let's replace the direct dbi memory space read procedure with the readl-wrapper invocation. Thus we'll have a slightly more generic dw_pcie_link_up() method. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index e3d2c11e6998..6e81264fdfb4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -548,7 +548,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) if (pci->ops && pci->ops->link_up) return pci->ops->link_up(pci); - val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); return ((val & PCIE_PORT_DEBUG1_LINK_UP) && (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); } From patchwork Tue May 3 21:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836351 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA2FC433EF for ; Tue, 3 May 2022 21:23:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242999AbiECV1Z (ORCPT ); Tue, 3 May 2022 17:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242887AbiECV1W (ORCPT ); Tue, 3 May 2022 17:27:22 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 221464162E; Tue, 3 May 2022 14:23:36 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 5D53816A9; Wed, 4 May 2022 00:24:09 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 5D53816A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613049; bh=bo5OqnK+Z6C/zfKXy1FN6D2uyOimMZxXIfJNT8kWNlI=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=icKemu7SIwVe5HDWo/ep1D9y8aOHLzTYni1wpNEF53a3vC9mME5CA6sE+3K6iE3NE 4yxxXUuURFofMY9YRBUEsQ2hYa1P5mL9cGNmPf5MrxrT86g2UwgopxDo5vp+e7Qqn4 2H11maKoNHZiZfaLEfpHYaufos/aY7SHAYGV0tIM= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:35 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Niklas Cassel , Joao Pinto CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 10/13] PCI: dwc: Deallocate EPC memory on EP init error Date: Wed, 4 May 2022 00:22:57 +0300 Message-ID: <20220503212300.30105-11-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If the dw_pcie_ep_init() method fails to perform any action after the EPC memory is initialized and the MSI memory region is allocated, the later parts won't be undone thus causing the memory leak. Let's fix that by introducing the cleanup-on-error path in the dw_pcie_ep_init() method, which will be taken should any consequent erroneous situation happens. Fixes: 2fd0c9d966cc ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init") Signed-off-by: Serge Semin --- Changelog v2: - This is a new patch create as a result of the discussion in: Link: https://lore.kernel.org/linux-pci/20220324014836.19149-26-Sergey.Semin@baikalelectronics.ru --- .../pci/controller/dwc/pcie-designware-ep.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 7c9315fffe24..7ad349c32082 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -780,8 +780,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, epc->mem->window.page_size); if (!ep->msi_mem) { + ret = -ENOMEM; dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); - return -ENOMEM; + goto err_exit_epc_mem; } if (ep->ops->get_features) { @@ -790,6 +791,19 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } - return dw_pcie_ep_init_complete(ep); + ret = dw_pcie_ep_init_complete(ep); + if (ret) + goto err_free_epc_mem; + + return 0; + +err_free_epc_mem: + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, + epc->mem->window.page_size); + +err_exit_epc_mem: + pci_epc_mem_exit(epc); + + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init); From patchwork Tue May 3 21:22:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836355 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 572A5C433FE for ; Tue, 3 May 2022 21:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242680AbiECV1b (ORCPT ); Tue, 3 May 2022 17:27:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242900AbiECV1X (ORCPT ); Tue, 3 May 2022 17:27:23 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F264D4198D; Tue, 3 May 2022 14:23:36 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 5607716D1; Wed, 4 May 2022 00:24:10 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 5607716D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613050; bh=oslhO17dYHGFIhWNNUG9XBnFq2z7WSrBbWWUbSeRRGk=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=hg6fXzul40AbgnhsWa/mt14/U61QAgb7Tv3MAONU1943Vu6RXmXADFl0MPk+Bfk+N f47aaEzcQRSJ7NvKQAthj2Wp78pYKoRl+Y8A/nDsuzmKSRyVPZ/zaP2NxHe26SsJss +7ysQfqaNQijiR/TRDdb8nRE4OjbTBrwjTUIgy2s= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:36 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 11/13] PCI: dwc-plat: Simplify the probe method return value handling Date: Wed, 4 May 2022 00:22:58 +0300 Message-ID: <20220503212300.30105-12-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The whole switch-case-logic implemented in the DWC PCIe RC/EP probe procedure doesn't seem well thought through. First of all the ret variable is unused in the EP-case and is only partly involved in the RC-case of the switch-case statement, which unnecessary complicates the code. Secondly the probe method will return zero if an unknown mode is detected. That is improbable situation since the OF-device data is initialized only with valid modes, but such code is still wrong at least from maintainability point of view. So let's convert the switch-case part of the probe function to being more coherent. We suggest to use the local ret variable to preserve the status of the case-clauses and return its value from the probe procedure after the work is done. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 0c5de87d3cc6..fea785096261 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -153,20 +153,21 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) return -ENODEV; ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev); - if (ret < 0) - return ret; break; case DW_PCIE_EP_TYPE: if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) return -ENODEV; pci->ep.ops = &pcie_ep_ops; - return dw_pcie_ep_init(&pci->ep); + ret = dw_pcie_ep_init(&pci->ep); + break; default: dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); + ret = -EINVAL; + break; } - return 0; + return ret; } static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = { From patchwork Tue May 3 21:22:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836352 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7134DC433EF for ; Tue, 3 May 2022 21:24:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231690AbiECV1b (ORCPT ); Tue, 3 May 2022 17:27:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242909AbiECV1X (ORCPT ); Tue, 3 May 2022 17:27:23 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 364E34163F; Tue, 3 May 2022 14:23:37 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 46BD416D6; Wed, 4 May 2022 00:24:11 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 46BD416D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613051; bh=DWfIhQOlThJ6h1HtDk1Jv4zywOs8e0bFpuSN9WfYfs4=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ST3CBNxFw9aKNHigL70CVKAAZkG4CdoQaJMJc6T0DJSLXLNOrBVwOP8dHwr+cLyAC heGM1J622OyyK8/NYUFKfCiS8pel1ff1ayjRB3ng8+PhE9cQOA79OsuW/jheA/GeBv bEiaIv+ASl2q4UhGMoZDvu1aaoTaDC5JdfqdbGLs= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:37 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 12/13] PCI: dwc-plat: Discard unused regmap pointer Date: Wed, 4 May 2022 00:22:59 +0300 Message-ID: <20220503212300.30105-13-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The regmap pointer was added into the dw_plat_pcie structure in commit 1d906b22076e ("PCI: dwc: Add support for EP mode"), but it hasn't been utilized neither in the code submitted in the denoted so far nor in the platform driver evolving afterwards. Drop it then for good. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index fea785096261..99cf2ac5b0ba 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -17,13 +17,11 @@ #include #include #include -#include #include "pcie-designware.h" struct dw_plat_pcie { struct dw_pcie *pci; - struct regmap *regmap; enum dw_pcie_device_mode mode; }; From patchwork Tue May 3 21:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12836357 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EF13C433F5 for ; Tue, 3 May 2022 21:24:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243052AbiECV1k (ORCPT ); Tue, 3 May 2022 17:27:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242947AbiECV1Y (ORCPT ); Tue, 3 May 2022 17:27:24 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E50E34161F; Tue, 3 May 2022 14:23:39 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 377A816A9; Wed, 4 May 2022 00:24:12 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 377A816A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651613052; bh=1f4SBFBJMaiyWW+OZ9FwRsB77hHDXlOvNwoIoORkwEc=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Jb27D/wdLNlDtQyTHTCfnCOvqenrXizO1iA995zACny6lJh6/EGVVl/Galj2aTFPm oB3aA3GpYwVONTwl6B6Yunv6VAURyiM2ZW0GImxbyx28QUWuabWYvmFWRL3hxPF+xX pn7nbu7iXf4CU7sLdIxjCaEoNIuAbLjDKUwLBe0w= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 May 2022 00:23:38 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v2 13/13] PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration Date: Wed, 4 May 2022 00:23:00 +0300 Message-ID: <20220503212300.30105-14-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> References: <20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The denoted forward declaration used to be required to get the OF-device ID structure by calling the of_match_device() method. The later method invocation has been replaced with the of_device_get_match_data() call in the commit 5c204204cf24 ("PCI: designware-plat: Prefer of_device_get_match_data()"). Thus the forward declaration of the OF-compatible device strings no longer needed. Drop it for good. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 99cf2ac5b0ba..e606c5d5f06f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -29,8 +29,6 @@ struct dw_plat_pcie_of_data { enum dw_pcie_device_mode mode; }; -static const struct of_device_id dw_plat_pcie_of_match[]; - static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { };