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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:30:39 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Date: Wed, 4 May 2022 16:25:50 +0400 Message-Id: <20220504122601.335495-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053043_668923_EB62543F X-CRM114-Status: GOOD ( 15.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add clock definitions for Mediatek MT6735 clocks provided by apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 10 +++ .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++ .../clock/mediatek,mt6735-infracfg.h | 25 ++++++ .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++ .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++ 5 files changed, 167 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h diff --git a/MAINTAINERS b/MAINTAINERS index 2869a958f5e4..e917039b9d8c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12437,6 +12437,16 @@ S: Maintained F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml F: drivers/mmc/host/mtk-sd.c +MEDIATEK MT6735 CLOCK DRIVERS +M: Yassine Oudjana +L: linux-clk@vger.kernel.org +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h +F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h + MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau M: Lorenzo Bianconi diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h new file mode 100644 index 000000000000..3dda719fd5d5 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H +#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H + +#define ARMPLL 0 +#define MAINPLL 1 +#define UNIVPLL 2 +#define MMPLL 3 +#define MSDCPLL 4 +#define VENCPLL 5 +#define TVDPLL 6 +#define APLL1 7 +#define APLL2 8 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..979a174ff8b6 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H +#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H + +#define DBGCLK 0 +#define GCE 1 +#define TRBG 2 +#define CPUM 3 +#define DEVAPC 4 +#define AUDIO 5 +#define GCPU 6 +#define L2C_SRAM 7 +#define M4U 8 +#define CLDMA 9 +#define CONNMCU_BUS 10 +#define KP 11 +#define APXGPT 12 +#define SEJ 13 +#define CCIF0_AP 14 +#define CCIF1_AP 15 +#define PMIC_SPI 16 +#define PMIC_WRAP 17 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..16f3c6a9a772 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H +#define _DT_BINDINGS_CLK_MT6735_PERICFG_H + +#define DISP_PWM 0 +#define THERM 1 +#define PWM1 2 +#define PWM2 3 +#define PWM3 4 +#define PWM4 5 +#define PWM5 6 +#define PWM6 7 +#define PWM7 8 +#define PWM 9 +#define USB0 10 +#define IRDA 11 +#define APDMA 12 +#define MSDC30_0 13 +#define MSDC30_1 14 +#define MSDC30_2 15 +#define MSDC30_3 16 +#define UART0 17 +#define UART1 18 +#define UART2 19 +#define UART3 20 +#define UART4 21 +#define BTIF 22 +#define I2C0 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define AUXADC 27 +#define SPI0 28 +#define IRTX 29 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h new file mode 100644 index 000000000000..a771910a4b8a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H +#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H + +#define AD_SYS_26M_CK 0 +#define CLKPH_MCK_O 1 +#define DMPLL 2 +#define DPI_CK 3 +#define WHPLL_AUDIO_CK 4 + +#define SYSPLL_D2 5 +#define SYSPLL_D3 6 +#define SYSPLL_D5 7 +#define SYSPLL1_D2 8 +#define SYSPLL1_D4 9 +#define SYSPLL1_D8 10 +#define SYSPLL1_D16 11 +#define SYSPLL2_D2 12 +#define SYSPLL2_D4 13 +#define SYSPLL3_D2 14 +#define SYSPLL3_D4 15 +#define SYSPLL4_D2 16 +#define SYSPLL4_D4 17 +#define UNIVPLL_D2 18 +#define UNIVPLL_D3 19 +#define UNIVPLL_D5 20 +#define UNIVPLL_D26 21 +#define UNIVPLL1_D2 22 +#define UNIVPLL1_D4 23 +#define UNIVPLL1_D8 24 +#define UNIVPLL2_D2 25 +#define UNIVPLL2_D4 26 +#define UNIVPLL2_D8 27 +#define UNIVPLL3_D2 28 +#define UNIVPLL3_D4 29 +#define MSDCPLL_D2 30 +#define MSDCPLL_D4 31 +#define MSDCPLL_D8 32 +#define MSDCPLL_D16 33 +#define VENCPLL_D3 34 +#define TVDPLL_D2 35 +#define TVDPLL_D4 36 +#define DMPLL_D2 37 +#define DMPLL_D4 38 +#define DMPLL_D8 39 +#define AD_SYS_26M_D2 40 + +#define AXI_SEL 41 +#define MEM_SEL 42 +#define DDRPHY_SEL 43 +#define MM_SEL 44 +#define PWM_SEL 45 +#define VDEC_SEL 46 +#define MFG_SEL 47 +#define CAMTG_SEL 48 +#define UART_SEL 49 +#define SPI_SEL 50 +#define USB20_SEL 51 +#define MSDC50_0_SEL 52 +#define MSDC30_0_SEL 53 +#define MSDC30_1_SEL 54 +#define MSDC30_2_SEL 55 +#define MSDC30_3_SEL 56 +#define AUDIO_SEL 57 +#define AUDINTBUS_SEL 58 +#define PMICSPI_SEL 59 +#define SCP_SEL 60 +#define ATB_SEL 61 +#define DPI0_SEL 62 +#define SCAM_SEL 63 +#define MFG13M_SEL 64 +#define AUD1_SEL 65 +#define AUD2_SEL 66 +#define IRDA_SEL 67 +#define IRTX_SEL 68 +#define DISPPWM_SEL 69 + +#endif From patchwork Wed May 4 12:25:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:16 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Date: Wed, 4 May 2022 16:25:51 +0400 Message-Id: <20220504122601.335495-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053218_470937_B9E1EC73 X-CRM114-Status: GOOD ( 14.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add reset definitions for Mediatek MT6735 resets provided by infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 2 ++ .../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++ .../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h diff --git a/MAINTAINERS b/MAINTAINERS index e917039b9d8c..de15c3d50d2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..86448f946568 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H +#define _DT_BINDINGS_RST_MT6735_INFRACFG_H + +#define EMI_REG_RST 0 +#define DRAMC0_AO_RST 1 +#define AP_CIRQ_EINT_RST 3 +#define APXGPT_RST 4 +#define SCPSYS_RST 5 +#define KP_RST 6 +#define PMIC_WRAP_RST 7 +#define CLDMA_AO_TOP_RST 8 +#define EMI_RST 16 +#define CCIF_RST 17 +#define DRAMC0_RST 18 +#define EMI_AO_REG_RST 19 +#define CCIF_AO_RST 20 +#define TRNG_RST 21 +#define SYS_CIRQ_RST 22 +#define GCE_RST 23 +#define MM_IOMMU_RST 24 +#define CCIF1_RST 25 +#define CLDMA_TOP_PD_RST 26 +#define CBIP_P2P_MFG 27 +#define CBIP_P2P_APMIXED 28 +#define CBIP_P2P_CKSYS 29 +#define CBIP_P2P_MIPI 30 +#define CBIP_P2P_DDRPHY 31 + +#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..6cdfaa7ddadf --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H +#define _DT_BINDINGS_RST_MT6735_PERICFG_H + +#define UART0_SW_RST 0 +#define UART1_SW_RST 1 +#define UART2_SW_RST 2 +#define UART3_SW_RST 3 +#define UART4_SW_RST 4 +#define BTIF_SW_RST 6 +#define DISP_PWM_SW_RST 7 +#define PWM_SW_RST 8 +#define AUXADC_SW_RST 10 +#define DMA_SW_RST 11 +#define IRDA_SW_RST 12 +#define IRTX_SW_RST 13 +#define THERM_SW_RST 16 +#define MSDC2_SW_RST 17 +#define MSDC3_SW_RST 17 +#define MSDC0_SW_RST 19 +#define MSDC1_SW_RST 20 +#define I2C0_SW_RST 22 +#define I2C1_SW_RST 23 +#define I2C2_SW_RST 24 +#define I2C3_SW_RST 25 +#define USB_SW_RST 28 + +#define SPI0_SW_RST 33 + +#endif From patchwork Wed May 4 12:25:52 2022 Content-Type: text/plain; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:22 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Date: Wed, 4 May 2022 16:25:52 +0400 Message-Id: <20220504122601.335495-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053226_389176_043F9CA4 X-CRM114-Status: GOOD ( 12.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add compatible strings for MT6735 apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../bindings/arm/mediatek/mediatek,infracfg.yaml | 8 +++++--- .../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 4 +++- .../devicetree/bindings/clock/mediatek,topckgen.yaml | 4 +++- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml index 8681b785ed6d..aa1bb13e0d67 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: description: The Mediatek infracfg controller provides various clocks and reset outputs - to the system. The clock values can be found in , - and reset values in and - . + to the system. The clock values can be found in + and , and reset values in + , and + . properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6779-infracfg_ao - mediatek,mt6797-infracfg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 611f666f359d..94e5e003e60e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 770546195fb5..3a186621e7a9 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in . + The clock values can be found in + and . properties: compatible: @@ -32,6 +33,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixedsys - mediatek,mt7629-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index 5b8b37a2e594..920bf0828d58 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in . + The clock values can be found in and + . properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt7629-topckgen From patchwork Wed May 4 12:25:53 2022 Content-Type: text/plain; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:28 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/13] clk: composite: Export clk_unregister_composite Date: Wed, 4 May 2022 16:25:53 +0400 Message-Id: <20220504122601.335495-5-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053237_093060_F825D6BA X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana This is required to build the Mediatek clock core as a module. Doing so currently fails: ERROR: modpost: "clk_unregister_composite" [drivers/clk/mediatek/clk-mtk.ko] undefined! Fixes: cb50864f6cee ("clk: mediatek: Implement mtk_clk_unregister_composites() API") Signed-off-by: Yassine Oudjana --- drivers/clk/clk-composite.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index b9c5f904f535..0935a54c9d81 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -425,6 +425,7 @@ void clk_unregister_composite(struct clk *clk) clk_unregister(clk); kfree(composite); } +EXPORT_SYMBOL_GPL(clk_unregister_composite); void clk_hw_unregister_composite(struct clk_hw *hw) { From patchwork Wed May 4 12:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A61D0C433EF for ; Wed, 4 May 2022 12:33:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9Y5op6WFn+1EhQLp1hwpkXAmppQqrxrkKiQ83RtbjWM=; b=eSF3hqW3kKWV1p ilwRSMP1EO7hy1tLIz2gUJIy8JcWU9klkBCt4JyqNlDTNYGWs4Grbm9l+rH7u0Bq9VF0GWO6SIkUV HK4n16nGneaAfXpaL/4MhTNHelMRcE9lpBd8FuuQGgZVGrYgKVtd7SIqawNEkHQzv+GYq+tly7Tec XXLibvjb9f2jLNGCfKOtZl1CtbuvY7XqdrNmlGH0w+WBAEXfyqHKgHgPC/Tkr24iuxYS7Vz3TiP7M AH+BKjaekB5pRMGGsPZ/udg2TslNtAZWiO2/sA5/CPn0tSWhSsE6F6Xz+FfUtPHUHtuyekd9bXl5g fMajs3kAwWh6y+xwsOnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBQ-00AjHu-Kx; Wed, 04 May 2022 12:32:44 +0000 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBI-00AjCZ-Ce; Wed, 04 May 2022 12:32:37 +0000 Received: by mail-ej1-x634.google.com with SMTP id bv19so2586731ejb.6; Wed, 04 May 2022 05:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CNKzAxju2H5F78AxmBtE86NJhowOrzcymru33IBzxRo=; b=fhgI+VpoueobRqvh9tlA+tLmknI0/GBMBlZVChuFNtle9pQIpmqvLOhKfM6Dmjr1xw R3/4j2ipVTMcLVfcdiFVhPLlaPqRNY5t3H+rxBSFArOYE5xwpZxH3Jq/6mwZQVR5g5nH DS3m+OPLGiWRLFkR1OgFSMe8XxRKuEH9W86Sit7CTWaS36IS1BcjrV89ZJ+WtFIIoN5V SMHkwP1Nl0jDUWaKx2biMH+3mBhtuY+mAxeY2i82RlP9W3AZmkdHxsVek7a/DNULJQMK QeOxtBznr+PojfyE1rhzKOyrX/n2xr6Tt/U/VTGSbiKJy7ewUjeVFX4fuW8b/wFLsQHw dYPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CNKzAxju2H5F78AxmBtE86NJhowOrzcymru33IBzxRo=; b=mHekafLLu27iiTijTvKVvris6dR3vg/SQ/wRNiBp6YGHVKP2LP9tNT2wSLgEWgU7uU ExMNCyWEBlez397dOmPGTo73fm9NstPA7NdWd1EEjMI1E22rzX6VMBhlnmT5K6YU6AE+ 2SbHzHupKAvzQp1Bw5u853s/SDYeTH4esdxYVAv4ItpW3pIhXSEFDQQ9tdtPQ4zs0YON ae40523Tu8rLcnvIWRUVLxHbnMR9uaycJALZ2b79+fEBwM4jd1vHiuEZMAIqtnWWAoUX mMo81gSVjBQDueZ6AtiNB4zMByyKrssegieK2WgzVYidwZ6MZMfNFUTWihSNlZNGYqEk DWJA== X-Gm-Message-State: AOAM533Sj+TPenBnLCMOMiGODcJpXTrhFInUQYERPd087bHPcRkP3Xlj 7hDKMEyDKEwnWtktW3kInHbwoF1xL28= X-Google-Smtp-Source: ABdhPJz1LfNQyXPrgPpEVU72LKcwzEzy3aEBePRzfJCjCXhN8ogrNFGeDXHVMFOxKgDBPTqeQGtifQ== X-Received: by 2002:a17:907:980d:b0:6d6:f910:513a with SMTP id ji13-20020a170907980d00b006d6f910513amr18770753ejc.643.1651667555088; Wed, 04 May 2022 05:32:35 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:34 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Date: Wed, 4 May 2022 16:25:54 +0400 Message-Id: <20220504122601.335495-6-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053236_490640_4CEB98FD X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Export mtk_free_clk_data to allow using it in clock drivers built as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4063261cf56..0746b0f5beda 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -52,6 +52,7 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data) kfree(clk_data->clks); kfree(clk_data); } +EXPORT_SYMBOL_GPL(mtk_free_clk_data); int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data) From patchwork Wed May 4 12:25:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DF36C433EF for ; Wed, 4 May 2022 12:34:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SKwyEXQsFv4/BeLRjUl/lbWV/Ry5CQ65Ck9tDiLzlSg=; b=HPYVi+43czQdvw 4bVmxncn4GxO6ZfAdocQv2PL+b9m1vNlJKVtWeuen3UgNHmdgQbNvo1XpObJUHn6pUsd1FQpPuSRX pLo/fJ4FvxJTT9BJeB+j4KJyOuGiz7P/roV1jO56zEZXWaJaPJyzH/t8uRXUReuSzJhlt9qPXRhRT 4vNQgbpQSX9exLTwckN3A2SyCxDu9Sd+nLHYxgkfbL/dJ+1OWIaE+Evm97oh1VkTrVWyC6pWQP6nS IMoWTCIpsA7oqa1XWs3cXpadeAprQd7B5hnYHLaiCHM2AEGRF4asjeHIewqAWSYKmRDvEz1R0nXtk mHVRWsTxukEdlNvhNLnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmECK-00Ajsu-GK; Wed, 04 May 2022 12:33:40 +0000 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBO-00AjGh-81; Wed, 04 May 2022 12:32:44 +0000 Received: by mail-ej1-x62d.google.com with SMTP id j6so2554041ejc.13; Wed, 04 May 2022 05:32:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nBKA3UWWI9ka6cADxyOyqQzWUHiKDpIGUD+hMYCWwIE=; b=IyuGDa6VlGR8uuGgrygUdtZZA5TYqkZHkTBcLz+i70K9r+1qT8CbupcEsDQTytvDhw Y9K4JOoTspW2qMnjuniMQ3KmpsPvcIEEsMz7zT4woWw8Dcz1G9KaMHPew+nml4bFPyBH fchFcSRfPi+Mj2wS2r5oOsNSpLDNKPg3OZVAzL4MGx5me1tNRdFRMl5+zb1fir2fpSaH 3Ka/fgqO72ar+MmR81PLsewQqPsqzpEDqTJVO4ogn2nBIswn/PMZOgXzFC9k458Q8C1r Z5u/3nkYuxWTg0eERZQVbxU87/8s/HpT4ysl6+lMnYDX337XhVtm5+rMz8xoOdeyPre7 TZmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nBKA3UWWI9ka6cADxyOyqQzWUHiKDpIGUD+hMYCWwIE=; b=ykaLihz1plZw0xTdIEFAq+f4p5gwkhk+OWqj7GRfN6+nMBF/x0H87LewyrXeq2CAn1 7peIoXUN2+M6CZPqyACONJUBBywvepeg4ZBNJogroaHn2Uv0d2FE6HQddJjbKFASfRGc byo2ycMbaj0ZaZURmLoFoBJW7ynAjr0Pn/NNCihOkUEalKMBi31ODy9rlSJYY2fBE4Bj 1MIdqlK4rtllIrCVg0ctBiqH2CVvQQX5eE9Tku/wxb3fyf/Egou5DpJXJ2H2uJZpuXax ZZWDdgQjjD//iv22EqCEeX9b0DaRZ5PZ6u4v2xwBhAsWE6njR++x3EFeeydzmjw54rmx q1MQ== X-Gm-Message-State: AOAM532zaxYlEs4WazyONof+t1yfh1F4CC2MS55DOdSqzH0qWyB7xipR YrFLeZ6JDWnRcIdMu6TP06I= X-Google-Smtp-Source: ABdhPJyh3RaGuyNMpjEnKgDQjawtnF9SoXDPNlstOvMG1X0fvWRNarG3SkkNIl/eZ8ahLkcMZBxLAA== X-Received: by 2002:a17:906:4985:b0:6ef:b344:2a56 with SMTP id p5-20020a170906498500b006efb3442a56mr20451501eju.625.1651667560889; Wed, 04 May 2022 05:32:40 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:40 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Date: Wed, 4 May 2022 16:25:55 +0400 Message-Id: <20220504122601.335495-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053242_349583_5EB5DCAF X-CRM114-Status: GOOD ( 22.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add a driver for MT6735 apmixedsys PLLs. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++++++++++++++++++++ 4 files changed, 283 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c diff --git a/MAINTAINERS b/MAINTAINERS index de15c3d50d2d..1077712edb4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12442,6 +12442,7 @@ M: Yassine Oudjana L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: drivers/clk/mediatek/clk-mt6735-apmixed.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d5936cfb3bee..ab364892f602 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -117,6 +117,13 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. +config COMMON_CLK_MT6735_APMIXED + tristate "Clock driver for MediaTek MT6735 apmixedsys" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 apmixedsys clocks. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index caf2ce93d666..7f45a22c6178 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o +obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) += clk-mt6735-apmixed.o obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-apmixed.c b/drivers/clk/mediatek/clk-mt6735-apmixed.c new file mode 100644 index 000000000000..6c4ec77d1d19 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-apmixed.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define AP_PLL_CON_5 0x014 +#define ARMPLL_CON0 0x200 +#define ARMPLL_CON1 0x204 +#define ARMPLL_PWR_CON0 0x20c +#define MAINPLL_CON0 0x210 +#define MAINPLL_CON1 0x214 +#define MAINPLL_PWR_CON0 0x21c +#define UNIVPLL_CON0 0x220 +#define UNIVPLL_CON1 0x224 +#define UNIVPLL_PWR_CON0 0x22c +#define MMPLL_CON0 0x230 +#define MMPLL_CON1 0x234 +#define MMPLL_PWR_CON0 0x23c +#define MSDCPLL_CON0 0x240 +#define MSDCPLL_CON1 0x244 +#define MSDCPLL_PWR_CON0 0x24c +#define VENCPLL_CON0 0x250 +#define VENCPLL_CON1 0x254 +#define VENCPLL_PWR_CON0 0x25c +#define TVDPLL_CON0 0x260 +#define TVDPLL_CON1 0x264 +#define TVDPLL_PWR_CON0 0x26c +#define APLL1_CON0 0x270 +#define APLL1_CON1 0x274 +#define APLL1_CON2 0x278 +#define APLL1_PWR_CON0 0x27c +#define APLL2_CON0 0x280 +#define APLL2_CON1 0x284 +#define APLL2_CON2 0x288 +#define APLL2_PWR_CON0 0x28c + +#define CON0_RST_BAR BIT(24) + +static const struct mtk_pll_data apmixed_plls[] = { + { + .id = ARMPLL, + .name = "armpll", + .parent_name = "clk26m", + + .reg = ARMPLL_CON0, + .pwr_reg = ARMPLL_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = ARMPLL_CON1, + .pd_shift = 24, + + .pcw_reg = ARMPLL_CON1, + .pcw_chg_reg = ARMPLL_CON1, + .pcwbits = 21, + + .flags = PLL_AO + }, + { + .id = MAINPLL, + .name = "mainpll", + .parent_name = "clk26m", + + .reg = MAINPLL_CON0, + .pwr_reg = MAINPLL_PWR_CON0, + .en_mask = 0xf0000101, + + .pd_reg = MAINPLL_CON1, + .pd_shift = 24, + + .pcw_reg = MAINPLL_CON1, + .pcw_chg_reg = MAINPLL_CON1, + .pcwbits = 21, + + .flags = HAVE_RST_BAR, + .rst_bar_mask = CON0_RST_BAR + }, + { + .id = UNIVPLL, + .name = "univpll", + .parent_name = "clk26m", + + .reg = UNIVPLL_CON0, + .pwr_reg = UNIVPLL_PWR_CON0, + .en_mask = 0xfc000001, + + .pd_reg = UNIVPLL_CON1, + .pd_shift = 24, + + .pcw_reg = UNIVPLL_CON1, + .pcw_chg_reg = UNIVPLL_CON1, + .pcwbits = 21, + + .flags = HAVE_RST_BAR, + .rst_bar_mask = CON0_RST_BAR + }, + { + .id = MMPLL, + .name = "mmpll", + .parent_name = "clk26m", + + .reg = MMPLL_CON0, + .pwr_reg = MMPLL_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = MMPLL_CON1, + .pd_shift = 24, + + .pcw_reg = MMPLL_CON1, + .pcw_chg_reg = MMPLL_CON1, + .pcwbits = 21 + }, + { + .id = MSDCPLL, + .name = "msdcpll", + .parent_name = "clk26m", + + .reg = MSDCPLL_CON0, + .pwr_reg = MSDCPLL_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = MSDCPLL_CON1, + .pd_shift = 24, + + .pcw_reg = MSDCPLL_CON1, + .pcw_chg_reg = MSDCPLL_CON1, + .pcwbits = 21, + }, + { + .id = VENCPLL, + .name = "vencpll", + .parent_name = "clk26m", + + .reg = VENCPLL_CON0, + .pwr_reg = VENCPLL_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = VENCPLL_CON1, + .pd_shift = 24, + + .pcw_reg = VENCPLL_CON1, + .pcw_chg_reg = VENCPLL_CON1, + .pcwbits = 21, + + .flags = HAVE_RST_BAR, + .rst_bar_mask = CON0_RST_BAR + }, + { + .id = TVDPLL, + .name = "tvdpll", + .parent_name = "clk26m", + + .reg = TVDPLL_CON0, + .pwr_reg = TVDPLL_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = TVDPLL_CON1, + .pd_shift = 24, + + .pcw_reg = TVDPLL_CON1, + .pcw_chg_reg = TVDPLL_CON1, + .pcwbits = 21 + }, + { + .id = APLL1, + .name = "apll1", + .parent_name = "clk26m", + + .reg = APLL1_CON0, + .pwr_reg = APLL1_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = APLL1_CON0, + .pd_shift = 4, + + .pcw_reg = APLL1_CON1, + .pcw_chg_reg = APLL1_CON1, + .pcwbits = 31, + + .tuner_reg = APLL1_CON2, + .tuner_en_reg = AP_PLL_CON_5, + .tuner_en_bit = 0 + }, + { + .id = APLL2, + .name = "apll2", + .parent_name = "clk26m", + + .reg = APLL2_CON0, + .pwr_reg = APLL2_PWR_CON0, + .en_mask = 0x00000001, + + .pd_reg = APLL2_CON0, + .pd_shift = 4, + + .pcw_reg = APLL2_CON1, + .pcw_chg_reg = APLL2_CON1, + .pcwbits = 31, + + .tuner_reg = APLL1_CON2, + .tuner_en_reg = AP_PLL_CON_5, + .tuner_en_bit = 1 + } +}; + +int clk_mt6735_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk_onecell_data *clk_data; + int ret; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); + if (!clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, clk_data); + + ret = mtk_clk_register_plls(pdev->dev.of_node, apmixed_plls, + ARRAY_SIZE(apmixed_plls), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register PLLs: %pe\n", + ERR_PTR(ret)); + return ret; + } + + ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + clk_data); + if (ret) + dev_err(&pdev->dev, "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + + return ret; +} + +int clk_mt6735_apmixed_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_plls(apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_apmixedsys[] = { + { .compatible = "mediatek,mt6735-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_apmixed = { + .probe = clk_mt6735_apmixed_probe, + .remove = clk_mt6735_apmixed_remove, + .driver = { + .name = "clk-mt6735-apmixed", + .of_match_table = of_match_mt6735_apmixedsys, + }, +}; +module_platform_driver(clk_mt6735_apmixed); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 apmixedsys clock driver"); +MODULE_LICENSE("GPL"); From patchwork Wed May 4 12:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:46 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Date: Wed, 4 May 2022 16:25:56 +0400 Message-Id: <20220504122601.335495-8-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053252_428556_4DE18BD8 X-CRM114-Status: GOOD ( 21.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add a driver for MT6735 topckgen clocks. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 ++++++++++++++++++++ 4 files changed, 1168 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c diff --git a/MAINTAINERS b/MAINTAINERS index 1077712edb4b..d9d6449f910e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12443,6 +12443,7 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c +F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ab364892f602..7c19e2d7bb02 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,13 @@ config COMMON_CLK_MT6735_APMIXED help This driver supports MediaTek MT6735 apmixedsys clocks. +config COMMON_CLK_MT6735_TOPCKGEN + tristate "Clock driver for MediaTek MT6735 topckgen" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 topckgen clocks. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 7f45a22c6178..e8e892c4145f 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) += clk-mt6735-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) += clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/mediatek/clk-mt6735-topckgen.c new file mode 100644 index 000000000000..444c87aed71e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-mux.h" + +#include + +#define CLK_CFG_0 0x40 +#define CLK_CFG_0_SET 0x44 +#define CLK_CFG_0_CLR 0x48 +#define CLK_CFG_1 0x50 +#define CLK_CFG_1_SET 0x54 +#define CLK_CFG_1_CLR 0x58 +#define CLK_CFG_2 0x60 +#define CLK_CFG_2_SET 0x64 +#define CLK_CFG_2_CLR 0x68 +#define CLK_CFG_3 0x70 +#define CLK_CFG_3_SET 0x74 +#define CLK_CFG_3_CLR 0x78 +#define CLK_CFG_4 0x80 +#define CLK_CFG_4_SET 0x84 +#define CLK_CFG_4_CLR 0x88 +#define CLK_CFG_5 0x90 +#define CLK_CFG_5_SET 0x94 +#define CLK_CFG_5_CLR 0x98 +#define CLK_CFG_6 0xa0 +#define CLK_CFG_6_SET 0xa4 +#define CLK_CFG_6_CLR 0xa8 +#define CLK_CFG_7 0xb0 +#define CLK_CFG_7_SET 0xb4 +#define CLK_CFG_7_CLR 0xb8 + +static DEFINE_SPINLOCK(mt6735_topckgen_lock); + +/* Some clocks with unknown details are modeled as fixed clocks */ +static const struct mtk_fixed_clk top_fixed_clks[] = { + { + /* + * This clock is available as a parent option for multiple + * muxes and seems like an alternative name for clk26m at first, + * but it appears alongside it in several muxes which should + * mean it is a separate clock. + */ + .id = AD_SYS_26M_CK, + .name = "ad_sys_26m_ck", + .parent = "clk26m", + .rate = 26 * MHZ, + }, + { + /* + * This clock is the parent of DMPLL divisors. It might be MEMPLL + * or its parent, as DMPLL appears to be an alternative name for + * MEMPLL. + */ + .id = CLKPH_MCK_O, + .name = "clkph_mck_o", + .parent = NULL + }, + { + /* + * DMPLL clock (dmpll_ck), controlled by DDRPHY. + */ + .id = DMPLL, + .name = "dmpll", + .parent = "clkph_mck_o" + }, + { + /* + * MIPI DPI clock. Parent option for dpi0_sel. Unknown parent. + */ + .id = DPI_CK, + .name = "dpi_ck", + .parent = NULL + }, + { + /* + * This clock is a child of WHPLL which is controlled by + * the modem. + */ + .id = WHPLL_AUDIO_CK, + .name = "whpll_audio_ck", + .parent = NULL + }, +}; + +static const struct mtk_fixed_factor top_divs[] = { + { + .id = SYSPLL_D2, + .name = "syspll_d2", + .parent_name = "mainpll", + .mult = 1, + .div = 2 + }, + { + .id = SYSPLL_D3, + .name = "syspll_d3", + .parent_name = "mainpll", + .mult = 1, + .div = 3 + }, + { + .id = SYSPLL_D5, + .name = "syspll_d5", + .parent_name = "mainpll", + .mult = 1, + .div = 5 + }, + { + .id = SYSPLL1_D2, + .name = "syspll1_d2", + .parent_name = "mainpll", + .mult = 1, + .div = 2 + }, + { + .id = SYSPLL1_D4, + .name = "syspll1_d4", + .parent_name = "mainpll", + .mult = 1, + .div = 4 + }, + { + .id = SYSPLL1_D8, + .name = "syspll1_d8", + .parent_name = "mainpll", + .mult = 1, + .div = 8 + }, + { + .id = SYSPLL1_D16, + .name = "syspll1_d16", + .parent_name = "mainpll", + .mult = 1, + .div = 16 + }, + { + .id = SYSPLL2_D2, + .name = "syspll2_d2", + .parent_name = "mainpll", + .mult = 1, + .div = 2 + }, + { + .id = SYSPLL2_D4, + .name = "syspll2_d4", + .parent_name = "mainpll", + .mult = 1, + .div = 4 + }, + { + .id = SYSPLL3_D2, + .name = "syspll3_d2", + .parent_name = "mainpll", + .mult = 1, + .div = 2 + }, + { + .id = SYSPLL3_D4, + .name = "syspll3_d4", + .parent_name = "mainpll", + .mult = 1, + .div = 4 + }, + { + .id = SYSPLL4_D2, + .name = "syspll4_d2", + .parent_name = "mainpll", + .mult = 1, + .div = 2 + }, + { + .id = SYSPLL4_D4, + .name = "syspll4_d4", + .parent_name = "mainpll", + .mult = 1, + .div = 4 + }, + { + .id = UNIVPLL_D2, + .name = "univpll_d2", + .parent_name = "univpll", + .mult = 1, + .div = 2 + }, + { + .id = UNIVPLL_D3, + .name = "univpll_d3", + .parent_name = "univpll", + .mult = 1, + .div = 3 + }, + { + .id = UNIVPLL_D5, + .name = "univpll_d5", + .parent_name = "univpll", + .mult = 1, + .div = 5 + }, + { + .id = UNIVPLL_D26, + .name = "univpll_d26", + .parent_name = "univpll", + .mult = 1, + .div = 26 + }, + { + .id = UNIVPLL1_D2, + .name = "univpll1_d2", + .parent_name = "univpll", + .mult = 1, + .div = 2 + }, + { + .id = UNIVPLL1_D4, + .name = "univpll1_d4", + .parent_name = "univpll", + .mult = 1, + .div = 4 + }, + { + .id = UNIVPLL1_D8, + .name = "univpll1_d8", + .parent_name = "univpll", + .mult = 1, + .div = 8 + }, + { + .id = UNIVPLL2_D2, + .name = "univpll2_d2", + .parent_name = "univpll", + .mult = 1, + .div = 2 + }, + { + .id = UNIVPLL2_D4, + .name = "univpll2_d4", + .parent_name = "univpll", + .mult = 1, + .div = 4 + }, + { + .id = UNIVPLL2_D8, + .name = "univpll2_d8", + .parent_name = "univpll", + .mult = 1, + .div = 8 + }, + { + .id = UNIVPLL3_D2, + .name = "univpll3_d2", + .parent_name = "univpll", + .mult = 1, + .div = 2 + }, + { + .id = UNIVPLL3_D4, + .name = "univpll3_d4", + .parent_name = "univpll", + .mult = 1, + .div = 4 + }, + { + .id = MSDCPLL_D2, + .name = "msdcpll_d2", + .parent_name = "msdcpll", + .mult = 1, + .div = 2 + }, + { + .id = MSDCPLL_D4, + .name = "msdcpll_d4", + .parent_name = "msdcpll", + .mult = 1, + .div = 4 + }, + { + .id = MSDCPLL_D8, + .name = "msdcpll_d8", + .parent_name = "msdcpll", + .mult = 1, + .div = 8 + }, + { + .id = MSDCPLL_D16, + .name = "msdcpll_d16", + .parent_name = "msdcpll", + .mult = 1, + .div = 16 + }, + { + .id = VENCPLL_D3, + .name = "vencpll_d3", + .parent_name = "vencpll", + .mult = 1, + .div = 3 + }, + { + .id = TVDPLL_D2, + .name = "tvdpll_d2", + .parent_name = "tvdpll", + .mult = 1, + .div = 2 + }, + { + .id = TVDPLL_D4, + .name = "tvdpll_d4", + .parent_name = "tvdpll", + .mult = 1, + .div = 4 + }, + { + .id = DMPLL_D2, + .name = "dmpll_d2", + .parent_name = "clkph_mck_o", + .mult = 1, + .div = 2 + }, + { + .id = DMPLL_D4, + .name = "dmpll_d4", + .parent_name = "clkph_mck_o", + .mult = 1, + .div = 4 + }, + { + .id = DMPLL_D8, + .name = "dmpll_d8", + .parent_name = "clkph_mck_o", + .mult = 1, + .div = 8 + }, + { + .id = AD_SYS_26M_D2, + .name = "ad_sys_26m_d2", + .parent_name = "clk26m", + .mult = 1, + .div = 2 + }, +}; + +static const char * const axi_sel_parents[] = { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll", + "dmpll_d2" +}; + +static const char * const mem_sel_parents[] = { + "clk26m", + "dmpll" +}; + +static const char * const ddrphycfg_parents[] = { + "clk26m", + "syspll1_d8" +}; + +static const char * const mm_sel_parents[] = { + "clk26m", + "vencpll", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll" +}; + +static const char * const pwm_sel_parents[] = { + "clk26m", + "univpll2_d4", + "univpll3_d2", + "univpll1_d4" +}; + +static const char * const vdec_sel_parents[] = { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "syspll_d2", + "syspll2_d2", + "msdcpll_d2" +}; + +static const char * const mfg_sel_parents[] = { + "clk26m", + "mmpll", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "syspll_d3", + "syspll1_d2", + "syspll_d5", + "univpll_d3", + "univpll1_d2" +}; + +static const char * const camtg_sel_parents[] = { + "clk26m", + "univpll_d26", + "univpll2_d2", + "syspll3_d2", + "syspll3_d4", + "msdcpll_d4" +}; + +static const char * const uart_sel_parents[] = { + "clk26m", + "univpll2_d8" +}; + +static const char * const spi_sel_parents[] = { + "clk26m", + "syspll3_d2", + "msdcpll_d8", + "syspll2_d4", + "syspll4_d2", + "univpll2_d4", + "univpll1_d8" +}; + +static const char * const usb20_sel_parents[] = { + "clk26m", + "univpll1_d8", + "univpll3_d4" +}; + +static const char * const msdc50_0_sel_parents[] = { + "clk26m", + "syspll1_d2", + "syspll2_d2", + "syspll4_d2", + "univpll_d5", + "univpll1_d4" +}; + +static const char * const msdc30_0_sel_parents[] = { + "clk26m", + "msdcpll", + "msdcpll_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d3", + "univpll_d26", + "syspll2_d4", + "univpll_d2" +}; + +static const char * const msdc30_1_2_sel_parents[] = { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "syspll2_d4" +}; + +static const char * const msdc30_3_sel_parents[] = { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "msdcpll_d16", + "syspll2_d4" +}; + +static const char * const audio_sel_parents[] = { + "clk26m", + "syspll3_d4", + "syspll4_d4", + "syspll1_d16" +}; + +static const char * const aud_intbus_sel_parents[] = { + "clk26m", + "syspll1_d4", + "syspll4_d2", + "dmpll_d4" +}; + +static const char * const pmicspi_sel_parents[] = { + "clk26m", + "syspll1_d8", + "syspll3_d4", + "syspll1_d16", + "univpll3_d4", + "univpll_d26", + "dmpll_d4", + "dmpll_d8" +}; + +static const char * const scp_sel_parents[] = { + "clk26m", + "syspll1_d8", + "dmpll_d2", + "dmpll_d4" +}; + +static const char * const atb_sel_parents[] = { + "clk26m", + "syspll1_d2", + "syspll_d5", + "dmpll" +}; + +static const char * const dpi0_sel_parents[] = { + "clk26m", + "tvdpll", + "tvdpll_d2", + "tvdpll_d4", + "dpi_ck" +}; + +static const char * const scam_sel_parents[] = { + "clk26m", + "syspll3_d2", + "univpll2_d4", + "vencpll_d3" +}; + +static const char * const mfg13m_sel_parents[] = { + "clk26m", + "ad_sys_26m_d2" +}; + +static const char * const aud_1_2_sel_parents[] = { + "clk26m", + "apll1" +}; + +static const char * const irda_sel_parents[] = { + "clk26m", + "univpll2_d4" +}; + +static const char * const irtx_sel_parents[] = { + "clk26m", + "ad_sys_26m_ck" +}; + +static const char * const disppwm_sel_parents[] = { + "clk26m", + "univpll2_d4", + "syspll4_d2_d8", + "ad_sys_26m_ck" +}; + +static const struct mtk_mux top_muxes[] = { + { + .id = AXI_SEL, + .name = "axi_sel", + .parent_names = axi_sel_parents, + .num_parents = ARRAY_SIZE(axi_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_0, + .set_ofs = CLK_CFG_0_SET, + .clr_ofs = CLK_CFG_0_CLR, + + .mux_shift = 0, + .mux_width = 3, + + .ops = &mtk_mux_clr_set_upd_ops, + }, + { + .id = MEM_SEL, + .name = "mem_sel", + .parent_names = mem_sel_parents, + .num_parents = ARRAY_SIZE(mem_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_0, + .set_ofs = CLK_CFG_0_SET, + .clr_ofs = CLK_CFG_0_CLR, + + .mux_shift = 8, + .mux_width = 1, + + .ops = &mtk_mux_clr_set_upd_ops, + }, + { + .id = DDRPHY_SEL, + .name = "ddrphycfg_sel", + .parent_names = ddrphycfg_parents, + .num_parents = ARRAY_SIZE(ddrphycfg_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_0, + .set_ofs = CLK_CFG_0_SET, + .clr_ofs = CLK_CFG_0_CLR, + + .mux_shift = 16, + .mux_width = 1, + + .ops = &mtk_mux_clr_set_upd_ops, + }, + { + .id = MM_SEL, + .name = "mm_sel", + .parent_names = mm_sel_parents, + .num_parents = ARRAY_SIZE(mm_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_0, + .set_ofs = CLK_CFG_0_SET, + .clr_ofs = CLK_CFG_0_CLR, + + .mux_shift = 24, + .mux_width = 3, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = PWM_SEL, + .name = "pwm_sel", + .parent_names = pwm_sel_parents, + .num_parents = ARRAY_SIZE(pwm_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_1, + .set_ofs = CLK_CFG_1_SET, + .clr_ofs = CLK_CFG_1_CLR, + + .mux_shift = 0, + .mux_width = 2, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = VDEC_SEL, + .name = "vdec_sel", + .parent_names = vdec_sel_parents, + .num_parents = ARRAY_SIZE(vdec_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_1, + .set_ofs = CLK_CFG_1_SET, + .clr_ofs = CLK_CFG_1_CLR, + + .mux_shift = 8, + .mux_width = 3, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MFG_SEL, + .name = "mfg_sel", + .parent_names = mfg_sel_parents, + .num_parents = ARRAY_SIZE(mfg_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_1, + .set_ofs = CLK_CFG_1_SET, + .clr_ofs = CLK_CFG_1_CLR, + + .mux_shift = 16, + .mux_width = 4, + .gate_shift = 23, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = CAMTG_SEL, + .name = "camtg_sel", + .parent_names = camtg_sel_parents, + .num_parents = ARRAY_SIZE(camtg_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_1, + .set_ofs = CLK_CFG_1_SET, + .clr_ofs = CLK_CFG_1_CLR, + + .mux_shift = 24, + .mux_width = 3, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = UART_SEL, + .name = "uart_sel", + .parent_names = uart_sel_parents, + .num_parents = ARRAY_SIZE(uart_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_2, + .set_ofs = CLK_CFG_2_SET, + .clr_ofs = CLK_CFG_2_CLR, + + .mux_shift = 0, + .mux_width = 1, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = SPI_SEL, + .name = "spi_sel", + .parent_names = spi_sel_parents, + .num_parents = ARRAY_SIZE(spi_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_2, + .set_ofs = CLK_CFG_2_SET, + .clr_ofs = CLK_CFG_2_CLR, + + .mux_shift = 8, + .mux_width = 3, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = USB20_SEL, + .name = "usb20_sel", + .parent_names = usb20_sel_parents, + .num_parents = ARRAY_SIZE(usb20_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_2, + .set_ofs = CLK_CFG_2_SET, + .clr_ofs = CLK_CFG_2_CLR, + + .mux_shift = 16, + .mux_width = 2, + .gate_shift = 23, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MSDC50_0_SEL, + .name = "msdc50_0_sel", + .parent_names = msdc50_0_sel_parents, + .num_parents = ARRAY_SIZE(msdc50_0_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_2, + .set_ofs = CLK_CFG_2_SET, + .clr_ofs = CLK_CFG_2_CLR, + + .mux_shift = 24, + .mux_width = 3, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MSDC30_0_SEL, + .name = "msdc30_0_sel", + .parent_names = msdc30_0_sel_parents, + .num_parents = ARRAY_SIZE(msdc30_0_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_3, + .set_ofs = CLK_CFG_3_SET, + .clr_ofs = CLK_CFG_3_CLR, + + .mux_shift = 0, + .mux_width = 4, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MSDC30_1_SEL, + .name = "msdc30_1_sel", + .parent_names = msdc30_1_2_sel_parents, + .num_parents = ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_3, + .set_ofs = CLK_CFG_3_SET, + .clr_ofs = CLK_CFG_3_CLR, + + .mux_shift = 8, + .mux_width = 3, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MSDC30_2_SEL, + .name = "msdc30_2_sel", + .parent_names = msdc30_1_2_sel_parents, + .num_parents = ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_3, + .set_ofs = CLK_CFG_3_SET, + .clr_ofs = CLK_CFG_3_CLR, + + .mux_shift = 16, + .mux_width = 3, + .gate_shift = 23, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MSDC30_3_SEL, + .name = "msdc30_3_sel", + .parent_names = msdc30_3_sel_parents, + .num_parents = ARRAY_SIZE(msdc30_3_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_3, + .set_ofs = CLK_CFG_3_SET, + .clr_ofs = CLK_CFG_3_CLR, + + .mux_shift = 24, + .mux_width = 4, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = AUDIO_SEL, + .name = "audio_sel", + .parent_names = audio_sel_parents, + .num_parents = ARRAY_SIZE(audio_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_4, + .set_ofs = CLK_CFG_4_SET, + .clr_ofs = CLK_CFG_4_CLR, + + .mux_shift = 0, + .mux_width = 2, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = AUDINTBUS_SEL, + .name = "aud_intbus_sel", + .parent_names = aud_intbus_sel_parents, + .num_parents = ARRAY_SIZE(aud_intbus_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_4, + .set_ofs = CLK_CFG_4_SET, + .clr_ofs = CLK_CFG_4_CLR, + + .mux_shift = 8, + .mux_width = 2, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = PMICSPI_SEL, + .name = "pmicspi_sel", + .parent_names = pmicspi_sel_parents, + .num_parents = ARRAY_SIZE(pmicspi_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_4, + .set_ofs = CLK_CFG_4_SET, + .clr_ofs = CLK_CFG_4_CLR, + + .mux_shift = 16, + .mux_width = 3, + + .ops = &mtk_mux_clr_set_upd_ops, + }, + { + .id = SCP_SEL, + .name = "scp_sel", + .parent_names = scp_sel_parents, + .num_parents = ARRAY_SIZE(scp_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_4, + .set_ofs = CLK_CFG_4_SET, + .clr_ofs = CLK_CFG_4_CLR, + + .mux_shift = 24, + .mux_width = 2, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = ATB_SEL, + .name = "atb_sel", + .parent_names = atb_sel_parents, + .num_parents = ARRAY_SIZE(atb_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_5, + .set_ofs = CLK_CFG_5_SET, + .clr_ofs = CLK_CFG_5_CLR, + + .mux_shift = 0, + .mux_width = 2, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = DPI0_SEL, + .name = "dpi0_sel", + .parent_names = dpi0_sel_parents, + .num_parents = ARRAY_SIZE(dpi0_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_5, + .set_ofs = CLK_CFG_5_SET, + .clr_ofs = CLK_CFG_5_CLR, + + .mux_shift = 8, + .mux_width = 3, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = SCAM_SEL, + .name = "scam_sel", + .parent_names = scam_sel_parents, + .num_parents = ARRAY_SIZE(scam_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_5, + .set_ofs = CLK_CFG_5_SET, + .clr_ofs = CLK_CFG_5_CLR, + + .mux_shift = 16, + .mux_width = 2, + .gate_shift = 23, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = MFG13M_SEL, + .name = "mfg13m_sel", + .parent_names = mfg13m_sel_parents, + .num_parents = ARRAY_SIZE(mfg13m_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_5, + .set_ofs = CLK_CFG_5_SET, + .clr_ofs = CLK_CFG_5_CLR, + + .mux_shift = 24, + .mux_width = 1, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = AUD1_SEL, + .name = "aud_1_sel", + .parent_names = aud_1_2_sel_parents, + .num_parents = ARRAY_SIZE(aud_1_2_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_6, + .set_ofs = CLK_CFG_6_SET, + .clr_ofs = CLK_CFG_6_CLR, + + .mux_shift = 0, + .mux_width = 1, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = AUD2_SEL, + .name = "aud_2_sel", + .parent_names = aud_1_2_sel_parents, + .num_parents = ARRAY_SIZE(aud_1_2_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_6, + .set_ofs = CLK_CFG_6_SET, + .clr_ofs = CLK_CFG_6_CLR, + + .mux_shift = 8, + .mux_width = 1, + .gate_shift = 15, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = IRDA_SEL, + .name = "irda_sel", + .parent_names = irda_sel_parents, + .num_parents = ARRAY_SIZE(irda_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_6, + .set_ofs = CLK_CFG_6_SET, + .clr_ofs = CLK_CFG_6_CLR, + + .mux_shift = 16, + .mux_width = 1, + .gate_shift = 23, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = IRTX_SEL, + .name = "irtx_sel", + .parent_names = irtx_sel_parents, + .num_parents = ARRAY_SIZE(irtx_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_6, + .set_ofs = CLK_CFG_6_SET, + .clr_ofs = CLK_CFG_6_CLR, + + .mux_shift = 24, + .mux_width = 1, + .gate_shift = 31, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id = DISPPWM_SEL, + .name = "disppwm_sel", + .parent_names = disppwm_sel_parents, + .num_parents = ARRAY_SIZE(disppwm_sel_parents), + .flags = CLK_SET_RATE_PARENT, + + .mux_ofs = CLK_CFG_7, + .set_ofs = CLK_CFG_7_SET, + .clr_ofs = CLK_CFG_7_CLR, + + .mux_shift = 0, + .mux_width = 2, + .gate_shift = 7, + + .ops = &mtk_mux_gate_clr_set_upd_ops, + }, +}; + +int clk_mt6735_topckgen_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk_onecell_data *clk_data; + int ret; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(top_fixed_clks) + + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes)); + if (!clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, clk_data); + + ret = mtk_clk_register_fixed_clks(top_fixed_clks, + ARRAY_SIZE(top_fixed_clks), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register fixed clocks: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register dividers: %pe\n", + ERR_PTR(ret)); + goto unregister_fixed_clks; + } + + ret = mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), + pdev->dev.of_node, &mt6735_topckgen_lock, + clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register muxes: %pe\n", + ERR_PTR(ret)); + goto unregister_factors; + } + + ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + clk_data); + if (ret) { + dev_err(&pdev->dev, + "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_muxes; + } + + return 0; +unregister_muxes: + mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(top_fixed_clks, + ARRAY_SIZE(top_fixed_clks), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + + return ret; +} + +int clk_mt6735_topckgen_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_topckgen[] = { + { .compatible = "mediatek,mt6735-topckgen" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_topckgen = { + .probe = clk_mt6735_topckgen_probe, + .remove = clk_mt6735_topckgen_remove, + .driver = { + .name = "clk-mt6735-topckgen", + .of_match_table = of_match_mt6735_topckgen, + }, +}; +module_platform_driver(clk_mt6735_topckgen); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 topckgen clock driver"); +MODULE_LICENSE("GPL"); From patchwork Wed May 4 12:25:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837839 Return-Path: X-Spam-Checker-Version: SpamAssassin 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:52 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Date: Wed, 4 May 2022 16:25:57 +0400 Message-Id: <20220504122601.335495-9-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053256_469143_AD9E8B7A X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana This allows it to be used in drivers built as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-gate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index da52023f8455..8af907b82f8f 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -261,6 +261,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, return PTR_ERR(clk); } +EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, int num, From patchwork Wed May 4 12:25:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3F3DC433F5 for ; Wed, 4 May 2022 12:36:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8xO8IzvbyPbgp/20Nh0VIMO5Lbeg+xS27/f+/8qSIeo=; b=JpjtjPpA5sVVKi +aamiJ4t1HDhndMjIKrEzOVwqnKJsYKnvdj+qqBvjyzNJidVVW/dG8zPjblYXhQ0XqT4NXw92s3qu n9VeD4triZOulnoNRsKttDBzCHR596RpluuQrrN1sds3XBbzNBsiIjqt8UbAhlxYIzaLm9c5A3KQa fdwfZWkM2nnuXF9GVY0YrFtf+qCcjIJe5IHhJzzCow/1A5dzFtineSeX63TRHThCeL95NfEglRUkv CatrfM4cOwhUwXNvRvR6N8HsDhjg2hlZTfdGKHKXDtyEA1KFVywO+9gIqzAsyikyKqEcVrmVjCpGD 88X6fHT7Hh8Wx8+5Wcfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEE8-00Akxn-Sy; Wed, 04 May 2022 12:35:33 +0000 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBg-00AjT9-Lp; Wed, 04 May 2022 12:33:02 +0000 Received: by mail-ed1-x530.google.com with SMTP id z19so1511489edx.9; Wed, 04 May 2022 05:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aPFSi/mWYMYdcINHgbvPpjSUWnzyR9p2rv5umtn3cjI=; b=UEFVed+rgiC1aLFETWO3cJXmKIhCocpF3HO/nI8utDBVg39ruLl5QFVsv4iuKvsveR 5qATWQ8FXfIGg/WmYfD4hppEDR+bjU9R2cpZK2b80cZj7hMm+DyQg4GkyCqvOrn9a6Hn Jf33IeqUyVSd18068d9DNkH5Ci1mOYNBziuQ4Kaaevxnfjp8ORdU3Y25YF4pBNcjVqPh K8jQg1FaR/BuZ27aXWahyAQCbLO6jopxmHRzaaxQPMilhwrwlBSIB0tsiMLKv1NQ4Njf ekXwbKBISFCg5eZx9ktY6Ge82DA4gMnJYoZ6k/x/ApvaQftQjfV5cP8tDj0Y4xVYp4Jy sDnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aPFSi/mWYMYdcINHgbvPpjSUWnzyR9p2rv5umtn3cjI=; b=l4QrNsUek6lND0OLYyrAgOr5OpJRU7bmEDfoz6gVknRm0lnUIphmXQghpUPbrwVUtr 6MYdmLZu1PCdlXvPmRQ5xkphu7j26Q2JFjySqRPWCBpIwgYl94ncDeJ67+pCDIkxh30Z Kos4AkHNqZiM/qouRXCjIpSo9NeErCrhOtXGu86WwA/5ZKM5po+8hJOi5Xv5U3qXg+UD dXpyU8uO69oPJpcayUt8hwQvlr8mmgLn6sT2LKhzoP94dkUwhfh8uFTvEH8Wd/c38PUD 5mv9Ijnn/KKQrMSGzMZCLn8+OEq2TDu4UPx7NH+O34QM3gVWKHOrwDDLn8cHxo3RWwkv VtVQ== X-Gm-Message-State: AOAM531cKPdvSX7Rfv6Ls0IZEheP/zFioV5QMbRlwDrZ5r+ArJWymgn0 Kf6QdVW+LqoLLgF0vcFUSWA= X-Google-Smtp-Source: ABdhPJw1ji77MznXPOLUih012rHNfyRY1v0DSI/u5kQreEXOVa6/qDVm+wA0fswuDakV4xVmX1s1FA== X-Received: by 2002:aa7:c318:0:b0:426:4aae:de6d with SMTP id l24-20020aa7c318000000b004264aaede6dmr22660856edq.208.1651667578090; Wed, 04 May 2022 05:32:58 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:57 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Date: Wed, 4 May 2022 16:25:58 +0400 Message-Id: <20220504122601.335495-10-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053300_808934_0115F1CE X-CRM114-Status: GOOD ( 10.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Export mtk_register_reset_controller and mtk_register_reset_controller_set_clr to support building reset drivers as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/reset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..6c2effe6afef 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct device_node *np, mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops); } +EXPORT_SYMBOL_GPL(mtk_register_reset_controller); void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs) @@ -136,5 +137,6 @@ void mtk_register_reset_controller_set_clr(struct device_node *np, mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops_set_clr); } +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); MODULE_LICENSE("GPL"); From patchwork Wed May 4 12:25:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8482BC433EF for ; Wed, 4 May 2022 12:37:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2U3rZNDeH5P/qiJaRklNjODBdO/f5L9rKuYeCWl1HnM=; b=GBU6wpca/fG9py 5HH5XudNOCFu6uhXfS8i8qGaMFFiNLktG/BcTK2WC7r6ezDuU3ns/owm5DTlnbz32GTDxoX0EJmeP 8hX93c3h3ttwIuzxThjYTGJMzQNMJFZ40SKQRFN63i2Kzb7YpHR9QGg9U2CPviLTnDakicT6rOfFt Jw2d2VO2DRV1Huu1talmUwAuMs32Zs6jNHFNuV1+b0SqUqzvD8Jw7Ocf+u4cSI7nBKZfnZDKqKYn7 Q2Mai8X0fOiZwpH2RbGS7ysCVQ+oke206RGCU9GaOIkfaQdGlXDf9j5p6RYFgfrTAaFTGVyA38Mnh k/NHw/QlSI/IAM+TwNoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEEf-00AlGw-TQ; Wed, 04 May 2022 12:36:06 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBm-00AjXj-5r; Wed, 04 May 2022 12:33:08 +0000 Received: by mail-ej1-x62c.google.com with SMTP id g6so2619993ejw.1; Wed, 04 May 2022 05:33:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4IPakMiBG8qMu0eZo70xqgp2PUHni7/ktt8LMUY1Go=; b=m2F3pyQcK4IPVHZeQQykxgWkJZ1MtrhVtyc+P5bf0ZH9Jgjrd9slbkr6T10zzXsT+O SKHQFHHdY5qa4+N6+extiji2ToJUpU1QA7nhtiokTSthTdyYP9uF5yhEBM0crd8gZ+dm rT/ivTV8NWMtSG8uX/h7nhs7t5a3n3Ocz+G+nyiJl350Oxj7dTJgCkCqKmvRnn3E2fR8 tzepYb9AVE4tY1GqMS9N3OXMIeHUJkUVJRwihnqxrpyP9eI4Vw2JoS6zCxZik3rzoOtG 8X7VyjxXcZxIDjOIiqt69uuL8B3dcep7tExY6hoe+MUvVqvC1Dniu2r8BN23G9TUleMQ 0mUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c4IPakMiBG8qMu0eZo70xqgp2PUHni7/ktt8LMUY1Go=; b=tdjrR/JtexmSikLDFDWx3O3U334cU/ccv+QBtij9ftdkVHxeY0pxH8mBUK4nbxQm6E Fk6QZfWypLmzCETpTJg4aRNRSvA9Ykjd40lnBdP/y2k+0KABj1cxrNOrTAJrXPm3inM3 pgCLQnOiaW6yoBaCiao3aGX80NYlfEV74yzuk7cAPordjTRF/tn0ZKlX0YnRhRnT82VY B8XJxHmOUa1KO8sMl4qlAurECrza22zcQnjpzP+gUP5FCpW5Jhxf0otCnHrczoOXNVwL pn/lPZ2FACArELcQWceEorCZjlALrJE7ioyBejWRBPNF+8kxTwBVKC1juzuk4fJ6/xhk d+Dg== X-Gm-Message-State: AOAM532S4n0VOuzxYtiL13Xur9266W8Z8UO214X6NZELYdWOoP9dzC/S B2OV28Or/cmO+IR1YW59/cw= X-Google-Smtp-Source: ABdhPJzjBn9KrdvJXPPoHERPbtQfki+JAaYMq/RQlJZ15Om95MsCxhMPcv/ncYAS2F1IyQC4vW+3dQ== X-Received: by 2002:a17:906:a2c2:b0:6e7:efc2:17f2 with SMTP id by2-20020a170906a2c200b006e7efc217f2mr19194685ejb.542.1651667583997; Wed, 04 May 2022 05:33:03 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:03 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Date: Wed, 4 May 2022 16:25:59 +0400 Message-Id: <20220504122601.335495-11-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053306_284198_7F7A4821 X-CRM114-Status: GOOD ( 15.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Return a struct mtk_reset* when registering a reset controller in preparation for adding an unregister helper that will take it as an argument. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.h | 6 +++--- drivers/clk/mediatek/reset.c | 22 ++++++++++++---------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..317905ec4a36 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -190,10 +190,10 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); +struct mtk_reset *mtk_register_reset_controller(struct device_node *np, + unsigned int num_regs, int regofs); -void mtk_register_reset_controller_set_clr(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs); struct mtk_clk_desc { diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 6c2effe6afef..f853bc8a7092 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -90,9 +90,9 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; -static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, int regofs, - const struct reset_control_ops *reset_ops) +static struct mtk_reset *mtk_register_reset_controller_common( + struct device_node *np, unsigned int num_regs, int regofs, + const struct reset_control_ops *reset_ops) { struct mtk_reset *data; int ret; @@ -101,12 +101,12 @@ static void mtk_register_reset_controller_common(struct device_node *np, regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return (struct mtk_reset *)regmap; } data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return ERR_PTR(-ENOMEM); data->regmap = regmap; data->regofs = regofs; @@ -119,22 +119,24 @@ static void mtk_register_reset_controller_common(struct device_node *np, if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); - return; + return ERR_PTR(ret); } + + return data; } -void mtk_register_reset_controller(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller(struct device_node *np, unsigned int num_regs, int regofs) { - mtk_register_reset_controller_common(np, num_regs, regofs, + return mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops); } EXPORT_SYMBOL_GPL(mtk_register_reset_controller); -void mtk_register_reset_controller_set_clr(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs) { - mtk_register_reset_controller_common(np, num_regs, regofs, + return mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops_set_clr); } EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); From patchwork Wed May 4 12:26:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64D36C433F5 for ; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:09 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Date: Wed, 4 May 2022 16:26:00 +0400 Message-Id: <20220504122601.335495-12-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053311_606980_8A1FAC16 X-CRM114-Status: GOOD ( 11.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add a function to unregister a reset controller previously registered with mtk_register_reset_controller() or mtk_register_reset_controller_set_clr(), and do the necessary cleanup. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/reset.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 317905ec4a36..1a0462d9c20b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -196,6 +196,8 @@ struct mtk_reset *mtk_register_reset_controller(struct device_node *np, struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs); +void mtk_unregister_reset_controller(struct mtk_reset *data); + struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index f853bc8a7092..7201e1f5e07b 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -141,4 +141,11 @@ struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node *np, } EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); +void mtk_unregister_reset_controller(struct mtk_reset *data) +{ + reset_controller_unregister(&data->rcdev); + kfree(data); +} +EXPORT_SYMBOL_GPL(mtk_unregister_reset_controller); + MODULE_LICENSE("GPL"); From patchwork Wed May 4 12:26:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DB13C433F5 for ; Wed, 4 May 2022 12:39:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KqXyENeb2eFNWA1F63CBBT/yXuncAMCL2+oT5muBU5Y=; b=V01vp3iLiH3tDE oUA9mkoatJBXGhXABec/p7WDY8Rkd/mnN4rG2F6aGzeXsNJ/5ds6x5uPshblofp4OZBIzDJuDY0Qq GXf8Lz0ZAGtPIjAhF5VW8YZNRH2ax2Q9bWmo30OaeUsowun+7zrqOzjYiXnThHNsx9MfvNWsFlCNl zUmE+kCtV/dpNwKBDDxEcHdJLOU/FLYnATyol1xZGfbf2QR5LLX9OO5LbDysmcW7ZdSAKvap8gbId Aaz32/59JlAVgbZ79/57DkT5D6w6eAQyviUnRKynqKFsr76SQPr6Ln3kLVCS3H3G+iH15cSKXplyn +Nm3lmW05R/MCs7BDeLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEGH-00Am9V-Qe; Wed, 04 May 2022 12:37:48 +0000 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEBw-00Ajfw-LP; Wed, 04 May 2022 12:33:18 +0000 Received: by mail-ej1-x636.google.com with SMTP id kq17so2602226ejb.4; Wed, 04 May 2022 05:33:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oBISr3CZQqGcdCjvRVbXiYWtS6ToMPWn6L1o4go4QLA=; b=qlFSPsKMg6Pg+xqGsaVWBtz6kLGClPntmdrQKCtiGYn2Km5rzLw4vdnHmpYJRQR0TA WS08ngbPf7TK4NjqvvQMTuhFV4nf0h4hA62VAPjCr/X6AOZvJUHm+3kqLupaMeWLjBaZ Msy0yQKk71fxUe4P4AqKq2dLNKcrdqwsdheslTTMlu4zO6I58fzeLN48WVDYebdFnPq6 KxgfsRpxilMj76St4qilt1ELN5kQkGuz2YaRHQSYEIKYckG4ZTSEDiHUWOclljJLRubS Etyg1Qw3GKloCRllmkflWQR7YGNoTl2QI1oaMvMS6/L6MYzvZQXMSr+B+KdBewwYdxRF f9Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oBISr3CZQqGcdCjvRVbXiYWtS6ToMPWn6L1o4go4QLA=; b=hMOzJF5NMCYMjN12dTDiCF2d8N7rDw1/k10zS5bQaFUsjOVrudOuNdmOovc2ZA7CHK mrW7WIk3MzLnpyyUvJulmfS7/hxjPsSeTIHjJkkM251/2B4MpM6hzQ3k0uVb64CApZ2S 8BNoOSnQ3sIpvQCHe7ukOtelPA5jZ4/aEnEIEvFnpeE+0+OLM9fEDbzePRFQdaOeQQpY 9uFDFuJpWWVohJMZRwtsJ0+SPr8OYw1vOLQb2iIDzI9kFFtsq3sRF/z00MaBetsAsv0k E3pIayZbFM9xFBWZGNT1rY9C0QpL9Ihj7TbGYOdsW0/wQEOaj/+bar5UTK5/kp/Y4hsT AkMA== X-Gm-Message-State: AOAM532JpCtbECrTVfWo3xCzBro+9t5kJRtHc1LP+Ru4V96ehrG4GQgG LD46DBey2/ChnuDVDgPmMwQ= X-Google-Smtp-Source: ABdhPJzhH9mftAskdv28qpFFDeFdarqLbrsYcwEXevajGrJy6gxGdaY2Bd/IhcfZUhKdyHrgYAmLBA== X-Received: by 2002:a17:907:9958:b0:6e7:f67a:a1e7 with SMTP id kl24-20020a170907995800b006e7f67aa1e7mr19398668ejc.400.1651667595412; Wed, 04 May 2022 05:33:15 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Date: Wed, 4 May 2022 16:26:01 +0400 Message-Id: <20220504122601.335495-13-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053316_775171_2972B365 X-CRM114-Status: GOOD ( 23.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add a driver for MT6735 infracfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 +++++++++++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c diff --git a/MAINTAINERS b/MAINTAINERS index d9d6449f910e..8662f12f34a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12443,6 +12443,7 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c +F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7c19e2d7bb02..62195e5d90a0 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,13 @@ config COMMON_CLK_MT6735_APMIXED help This driver supports MediaTek MT6735 apmixedsys clocks. +config COMMON_CLK_MT6735_INFRACFG + tristate "Clock driver for MediaTek MT6735 infracfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 infracfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e8e892c4145f..e5c1da6e2711 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) += clk-mt6735-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) += clk-mt6735-infracfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) += clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/mediatek/clk-mt6735-infracfg.c new file mode 100644 index 000000000000..ce1a5739b3b2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define INFRA_RST0 0x30 +#define INFRA_GLOBALCON_PDN0 0x40 +#define INFRA_PDN1 0x44 +#define INFRA_PDN_STA 0x48 + +struct mt6735_infracfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs infra_cg_regs = { + .set_ofs = INFRA_GLOBALCON_PDN0, + .clr_ofs = INFRA_PDN1, + .sta_ofs = INFRA_PDN_STA, +}; + +static const struct mtk_gate infracfg_gates[] = { + { + .id = DBGCLK, + .name = "dbgclk", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 0, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = GCE, + .name = "gce", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 1, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = TRBG, + .name = "trbg", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 2, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = CPUM, + .name = "cpum", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 3, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = DEVAPC, + .name = "devapc", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 4, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = AUDIO, + .name = "audio", + .parent_name = "aud_intbus_sel", + .regs = &infra_cg_regs, + .shift = 5, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = GCPU, + .name = "gcpu", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 6, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = L2C_SRAM, + .name = "l2csram", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 7, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = M4U, + .name = "m4u", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 8, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = CLDMA, + .name = "cldma", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 12, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = CONNMCU_BUS, + .name = "connmcu_bus", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 15, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = KP, + .name = "kp", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 16, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = APXGPT, + .name = "apxgpt", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 18, + .ops = &mtk_clk_gate_ops_setclr, + .flags = CLK_IS_CRITICAL + }, + { + .id = SEJ, + .name = "sej", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 19, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = CCIF0_AP, + .name = "ccif0ap", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 20, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = CCIF1_AP, + .name = "ccif1ap", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 21, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PMIC_SPI, + .name = "pmicspi", + .parent_name = "pmicspi_sel", + .regs = &infra_cg_regs, + .shift = 22, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PMIC_WRAP, + .name = "pmicwrap", + .parent_name = "axi_sel", + .regs = &infra_cg_regs, + .shift = 23, + .ops = &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_infracfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_infracfg *infracfg; + int ret; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + infracfg = devm_kmalloc(&pdev->dev, sizeof(struct mt6735_infracfg), + GFP_KERNEL); + if (!infracfg) + return -ENOMEM; + + infracfg->clk_data = mtk_alloc_clk_data(ARRAY_SIZE(infracfg_gates)); + if (!infracfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, infracfg); + + ret = mtk_clk_register_gates_with_dev(pdev->dev.of_node, infracfg_gates, + ARRAY_SIZE(infracfg_gates), + infracfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + infracfg->clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + infracfg->reset_data = mtk_register_reset_controller(pdev->dev.of_node, + 1, INFRA_RST0); + if (IS_ERR(infracfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + infracfg->reset_data); + return PTR_ERR(infracfg->reset_data); + } + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); +free_clk_data: + mtk_free_clk_data(infracfg->clk_data); + + return ret; +} + +int clk_mt6735_infracfg_remove(struct platform_device *pdev) +{ + struct mt6735_infracfg *infracfg = platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(infracfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); + mtk_free_clk_data(infracfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_infracfg[] = { + { .compatible = "mediatek,mt6735-infracfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_infracfg = { + .probe = clk_mt6735_infracfg_probe, + .remove = clk_mt6735_infracfg_remove, + .driver = { + .name = "clk-mt6735-infracfg", + .of_match_table = of_match_mt6735_infracfg, + }, +}; +module_platform_driver(clk_mt6735_infracfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 infracfg clock and reset driver"); +MODULE_LICENSE("GPL"); From patchwork Wed May 4 12:26:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12837866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB3FDC433F5 for ; Wed, 4 May 2022 12:39:57 +0000 (UTC) DKIM-Signature: v=1; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:23 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Date: Wed, 4 May 2022 16:26:02 +0400 Message-Id: <20220504122601.335495-14-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_053325_580019_E0AB1D25 X-CRM114-Status: GOOD ( 24.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add a driver for MT6735 pericfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 ++++++++++++++++++++++ 4 files changed, 369 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c diff --git a/MAINTAINERS b/MAINTAINERS index 8662f12f34a2..5d90c2f2a587 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12444,6 +12444,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 62195e5d90a0..698ff2995460 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -131,6 +131,13 @@ config COMMON_CLK_MT6735_INFRACFG help This driver supports MediaTek MT6735 infracfg clocks and resets. +config COMMON_CLK_MT6735_PERICFG + tristate "Clock driver for MediaTek MT6735 pericfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 pericfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e5c1da6e2711..b1a4d18e382d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed. obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) += clk-mt6735-apmixed.o obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) += clk-mt6735-infracfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_PERICFG) += clk-mt6735-pericfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) += clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediatek/clk-mt6735-pericfg.c new file mode 100644 index 000000000000..8a01aa63a81e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define PERI_GLOBALCON_RST0 0x00 +#define PERI_GLOBALCON_PDN0_SET 0x08 +#define PERI_GLOBALCON_PDN0_CLR 0x10 +#define PERI_GLOBALCON_PDN0_STA 0x18 + +struct mt6735_pericfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs peri_cg_regs = { + .set_ofs = PERI_GLOBALCON_PDN0_SET, + .clr_ofs = PERI_GLOBALCON_PDN0_CLR, + .sta_ofs = PERI_GLOBALCON_PDN0_STA, +}; + +static const struct mtk_gate pericfg_gates[] = { + { + .id = DISP_PWM, + .name = "disp_pwm", + .parent_name = "disppwm_sel", + .regs = &peri_cg_regs, + .shift = 0, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = THERM, + .name = "therm", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 1, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM1, + .name = "pwm1", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 2, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM2, + .name = "pwm2", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 3, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM3, + .name = "pwm3", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 4, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM4, + .name = "pwm4", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 5, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM5, + .name = "pwm5", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 6, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM6, + .name = "pwm6", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 7, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM7, + .name = "pwm7", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 8, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = PWM, + .name = "pwm", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 9, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = USB0, + .name = "usb0", + .parent_name = "usb20_sel", + .regs = &peri_cg_regs, + .shift = 10, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = IRDA, + .name = "irda", + .parent_name = "irda_sel", + .regs = &peri_cg_regs, + .shift = 11, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = APDMA, + .name = "apdma", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 12, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = MSDC30_0, + .name = "msdc30_0", + .parent_name = "msdc30_0_sel", + .regs = &peri_cg_regs, + .shift = 13, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = MSDC30_1, + .name = "msdc30_1", + .parent_name = "msdc30_1_sel", + .regs = &peri_cg_regs, + .shift = 14, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = MSDC30_2, + .name = "msdc30_2", + .parent_name = "msdc30_2_sel", + .regs = &peri_cg_regs, + .shift = 15, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = MSDC30_3, + .name = "msdc30_3", + .parent_name = "msdc30_3_sel", + .regs = &peri_cg_regs, + .shift = 16, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = UART0, + .name = "uart0", + .parent_name = "uart_sel", + .regs = &peri_cg_regs, + .shift = 17, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = UART1, + .name = "uart1", + .parent_name = "uart_sel", + .regs = &peri_cg_regs, + .shift = 18, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = UART2, + .name = "uart2", + .parent_name = "uart_sel", + .regs = &peri_cg_regs, + .shift = 19, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = UART3, + .name = "uart3", + .parent_name = "uart_sel", + .regs = &peri_cg_regs, + .shift = 20, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = UART4, + .name = "uart4", + .parent_name = "uart_sel", + .regs = &peri_cg_regs, + .shift = 21, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = BTIF, + .name = "btif", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 22, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = I2C0, + .name = "i2c0", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 23, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = I2C1, + .name = "i2c1", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 24, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = I2C2, + .name = "i2c2", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 25, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = I2C3, + .name = "i2c3", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 26, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = AUXADC, + .name = "auxadc", + .parent_name = "axi_sel", + .regs = &peri_cg_regs, + .shift = 27, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = SPI0, + .name = "spi0", + .parent_name = "spi_sel", + .regs = &peri_cg_regs, + .shift = 28, + .ops = &mtk_clk_gate_ops_setclr + }, + { + .id = IRTX, + .name = "IRTX", + .parent_name = "irtx_sel", + .regs = &peri_cg_regs, + .shift = 29, + .ops = &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_pericfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_pericfg *pericfg; + int ret; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pericfg = devm_kmalloc(&pdev->dev, sizeof(struct mt6735_pericfg), + GFP_KERNEL); + if (!pericfg) + return -ENOMEM; + + pericfg->clk_data = mtk_alloc_clk_data(ARRAY_SIZE(pericfg_gates)); + if (!pericfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, pericfg); + + ret = mtk_clk_register_gates_with_dev(pdev->dev.of_node, pericfg_gates, + ARRAY_SIZE(pericfg_gates), + pericfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + pericfg->clk_data); + if (ret) { + dev_err(&pdev->dev, + "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + pericfg->reset_data = mtk_register_reset_controller(pdev->dev.of_node, 2, + PERI_GLOBALCON_RST0); + if (IS_ERR(pericfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + pericfg->reset_data); + return PTR_ERR(pericfg->reset_data); + } + + return 0; +unregister_gates: + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); +free_clk_data: + mtk_free_clk_data(pericfg->clk_data); + + return ret; +} + +int clk_mt6735_pericfg_remove(struct platform_device *pdev) +{ + struct mt6735_pericfg *pericfg = platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(pericfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); + mtk_free_clk_data(pericfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_pericfg[] = { + { .compatible = "mediatek,mt6735-pericfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_pericfg = { + .probe = clk_mt6735_pericfg_probe, + .remove = clk_mt6735_pericfg_remove, + .driver = { + .name = "clk-mt6735-pericfg", + .of_match_table = of_match_mt6735_pericfg, + }, +}; +module_platform_driver(clk_mt6735_pericfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 pericfg clock driver"); +MODULE_LICENSE("GPL");