From patchwork Wed May 4 12:27:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12837814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57DA6C43219 for ; Wed, 4 May 2022 12:27:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349468AbiEDMbM (ORCPT ); Wed, 4 May 2022 08:31:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349449AbiEDMbK (ORCPT ); Wed, 4 May 2022 08:31:10 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C4F727FFD for ; Wed, 4 May 2022 05:27:34 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id d6so1498629ede.8 for ; Wed, 04 May 2022 05:27:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fJgKFMAN9XJcQFXSIBW4zb7s2vD8f3jyjsxvG6sAqRM=; b=aJZprpLOg4Q7URVW5jrhkvvYRKTRJ0WJvFHRSp0e/jKAhS6/clUxjaaM7+B1zgJR8x S17FYIBh7thE163yPel2PMtUA8mQlaEeUMk3/rXEJRSNndkhzQnHafDQroXkbu9ZjJO7 VyNmJLUMG0HifB8uIJkPPWDcWbXlBtt6zLr3GOT6NFWlTByaHgmFGUjQM7dzoy0lRgsI 2cl+t29f3jA4eQBviaYAzfr5+rdZi8wNtxhK6C8Wl5FX4hUDdnJU6t0ExEG+4r6DZ8OP rl8QuAErnLKE1o2FgWu0mf9TUNVaB1+ZqJ81x0L2J7pwAR34W6x5Xs+LeiBOZbNO2Cyf seiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fJgKFMAN9XJcQFXSIBW4zb7s2vD8f3jyjsxvG6sAqRM=; b=odYCDiGxQ5C4hh85Vp+jNjYJNxBTnsd0sELu5NsKlHw3SwEpDoWTulqnNx1BMIqLmr Dxk8oEr8g7PPyV06iow/8UvpjDHvMyEuHnkf/nX1NXTVGgNvmI7ZPkiY4G9npGR5flDk kzS5AmQ8iERWBYKwjP6iFVSgoDXJKN8kCqXlwDFqaYlckqNy2dPS+xgSs/Ed1VCuAcw6 9v45NRdODRu56AyXG6dYX6Nx8hcrxpAYG4+QQA5KhANJIbwNpOE0ZmwClKGLYNRUsvad i/woa1XkTIjY1zt6ECJBHGYY/d8kMmP7N7snNdWbU2HC+B7nh15HVySvAzWh+wlHBD+7 O7hA== X-Gm-Message-State: AOAM5339qnqNUTHqaJF6dIS84tERWgTkJV/oszzKTxfRu73ILcSchaep tKBOyiqlrbaqk3KDmVdfnyJ4mg== X-Google-Smtp-Source: ABdhPJxTYHD9YTyrH51GmC8O/lzpaoP2eGs3uQ7+LAkDPt9RTm65JWxBa7AG+7/PdLC/nR55FcdDpw== X-Received: by 2002:a05:6402:42c8:b0:427:d087:29 with SMTP id i8-20020a05640242c800b00427d0870029mr12569999edc.53.1651667252790; Wed, 04 May 2022 05:27:32 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:32 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss Subject: [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Date: Wed, 4 May 2022 14:27:20 +0200 Message-Id: <20220504122725.179262-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace &rpmhpd power domain integers with their respective defines in order to improve legibility. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c0137bdcf94b..52428b6df64e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; From patchwork Wed May 4 12:27:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12837816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C71F9C433F5 for ; Wed, 4 May 2022 12:27:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349505AbiEDMbR (ORCPT ); Wed, 4 May 2022 08:31:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349475AbiEDMbO (ORCPT ); Wed, 4 May 2022 08:31:14 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D65EC240AC for ; Wed, 4 May 2022 05:27:35 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id i19so2539287eja.11 for ; Wed, 04 May 2022 05:27:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SZtgNhQCLIwWaKL1yB2gMLGxiN27hiFfoYdGo48Nhks=; b=heckFfNh5ZagxaBNRRVtdct9OMC+o65bMjCfTsyC10vp6vvl3IGCpNni/4M6Gsa9br aPbcRksCDJMISsFZxu9e4FcReOndipaPvsPStnEO0AXIBfJ+iYS16qwWC0ho6gnIIA04 tM9u5wPzwr5usfNtj3l+V8CCDItmQ6UhTcLP4m24i5DhzlwFQ74G/uhwKwq2dnNxWP50 FjcbPmy9NfNfYy+8LHINMiOOzxxpplO6TzVTCCa+6xE3K4vLFT3LDxvGsr56RZEjurzD 9oMk1j4SNTnMcD+3bibuHnwF/a+cSGrA7AQcDqev9dPcaKp0suR9LSMOz2FU5rcdCxx2 i7uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SZtgNhQCLIwWaKL1yB2gMLGxiN27hiFfoYdGo48Nhks=; b=d+9//Cq8AylN02fXQSUxc0YTpU8oLG3W/C5HBOrp0/o+09ali1u+EO7yPsDl0/pKpe nQt+0zUV7A3sht95hfqfpp/3KfiI5VW5IQkI4WvRirH/KktxXW9ChiektjTBdhs7pt63 4Kk+lvgGxqtFCW6bDiZM1+6iGW8+N1dvnlI+xdWsypUglQsN6c1WHhT1oqgNqCVbWBN1 XMnCvTxzK4xmHBTkWXRYHm/gRkKuIxEmWvNg5b7n3iAoU16meWYyDUeSZwAmv1i+YfEF djwnf5Xu9nIkXsFJwh9mdxQvSxzOtJkS6OkyUBFqJXadqTTXhRjlG/AiYrIlBRyPh9ON laGw== X-Gm-Message-State: AOAM530xMU85DB7arqakWhRignsQkn8HxQOtHrPYTy1b+n+MS/EL+tVB 6YO1Gw/vM+ecZfSpzXPoYH915Q== X-Google-Smtp-Source: ABdhPJyaG938PZmOYA6JnlUXoWEeCrM5uUBwp0eiR+D/W355isYQ5fTqzyNb2j2jfIlpb88jUVEeuw== X-Received: by 2002:a17:906:6d0a:b0:6f3:c1c8:f814 with SMTP id m10-20020a1709066d0a00b006f3c1c8f814mr20584177ejr.230.1651667254058; Wed, 04 May 2022 05:27:34 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:33 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss Subject: [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC Date: Wed, 4 May 2022 14:27:21 +0200 Message-Id: <20220504122725.179262-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jonathan Marek The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss Signed-off-by: Jonathan Marek --- Changes since v1 - Remove .name assignments for clk_parent_data - Dmitry - Use ARRAY_SIZE where possible - Dmitry - Remove commented out code - Dmitry - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry - Assign .parent_hws instead of .hw - Dmitry Changes since v2 - Switch license to dual BSD/GPL - Bjorn - Add Jonathans SoB - Jonathan - Add Linaro to copyright statement - Bjorn - Make .hw.init assignment const - Bjorn - Extract & deduplicate bi_tcxo parent_data - Bjorn - Removed further .name assignment - Bjorn - Move of_device_id declaration - Bjorn drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e27f37ac2d9c..9b1f54e634b9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -703,6 +703,14 @@ config SM_GPUCC_8250 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8350 + tristate "SM8350 Graphics Clock Controller" + select SM_GCC_8350 + help + Support for the graphics clock controller on SM8350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dff6aeb980e6..e1b7e49c8da4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c new file mode 100644 index 000000000000..68d85757e064 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-divider.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x18, + .alpha = 0x6000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static const struct clk_parent_data gpu_cc_parent = { + .fw_name = "bi_tcxo", +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x1A, + .alpha = 0xAAA, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x117c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x11c0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x11bc, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x1170, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1170, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_at_clk = { + .halt_reg = 0x1080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_at_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { + .halt_reg = 0x1094, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { + .halt_reg = 0x1084, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x120c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x120c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { + .halt_reg = 0x105c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x105c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk = { + .halt_reg = 0x1058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_vsense_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x1178, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1178, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x1204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { + .halt_reg = 0x802c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x802c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_0_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { + .halt_reg = 0x8030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_1_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, +}; + +static struct gdsc *gpu_cc_sm8350_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8030, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { + .config = &gpu_cc_sm8350_regmap_config, + .clks = gpu_cc_sm8350_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), + .resets = gpu_cc_sm8350_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), + .gdscs = gpu_cc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), +}; + +static int gpu_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); +} + +static const struct of_device_id gpu_cc_sm8350_match_table[] = { + { .compatible = "qcom,sm8350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); + +static struct platform_driver gpu_cc_sm8350_driver = { + .probe = gpu_cc_sm8350_probe, + .driver = { + .name = "sm8350-gpucc", + .of_match_table = gpu_cc_sm8350_match_table, + }, +}; + +static int __init gpu_cc_sm8350_init(void) +{ + return platform_driver_register(&gpu_cc_sm8350_driver); +} +subsys_initcall(gpu_cc_sm8350_init); + +static void __exit gpu_cc_sm8350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8350_driver); +} +module_exit(gpu_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed May 4 12:27:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12837815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 751F0C4321E for ; Wed, 4 May 2022 12:27:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349508AbiEDMbS (ORCPT ); Wed, 4 May 2022 08:31:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343701AbiEDMbN (ORCPT ); Wed, 4 May 2022 08:31:13 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF48E24BE4 for ; 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:34 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss , Dmitry Baryshkov Subject: [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Wed, 4 May 2022 14:27:22 +0200 Message-Id: <20220504122725.179262-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 9ebcb1943b0a..4090cc7ea2ae 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -20,6 +20,7 @@ description: | dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h + dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: @@ -31,6 +32,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,sm8350-gpucc clocks: items: diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..d2294e0d527e --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Wed May 4 12:27:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12837817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12092C43219 for ; Wed, 4 May 2022 12:27:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349521AbiEDMbS (ORCPT ); Wed, 4 May 2022 08:31:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349483AbiEDMbQ (ORCPT ); Wed, 4 May 2022 08:31:16 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80F522F034 for ; Wed, 4 May 2022 05:27:38 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id n10so2562312ejk.5 for ; Wed, 04 May 2022 05:27:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8yQv7sPHp2MFInhIaa2OViHGxJArb/DI811sduLPJCk=; b=FY8pTjCy4o+S26j8vzaNVz0steta5PQqiARBvA1tFfr1QUciC5jfqLzujqrRqwxz0q IbR7bjEOEiF0/c7jIl8qG4vwSgXlMx27aqGwR5w0vjl6qdLYp8itLrzRbJfR9lprZPve xPQ0Jhkgjjok2Jo8i7g8Z4OaBmUp7vj2JjzA8rSO9Sln5yNri9X55Q0THmfJRbvZALT6 VKH/YhZSljxwf/cps8ur3lDcZA4lsLpInQolnVSMenblD4GMNAviVwrTwNFDoUIVAxPS CKKGsOqmpIk86FfMe15/CyMw2fDnNcO1ndzXDP5FKjWB7AeWyjoNk9X7XF4BwgEH9WpM a6Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8yQv7sPHp2MFInhIaa2OViHGxJArb/DI811sduLPJCk=; b=fiCKsbrSM0iRR9yOW6pECvbSuMuH6YgkEQKr1v7Mc4VQC8bA95ZhKhs8tx6aeg0oTi avCbPc0fdL4Shu+vTZaGXOJvxXDXhz37t7h4/Z4xWUD4vHzxwMUQocGBZmWMvlEoG4zY HdE9DMkWI9AUEvMpK64jCCZnun2+tE1JDwoDfC2QgFwt6CYwkq+BFB1qTX2RMIn2ArhA XmTRgl55XbQEGJy4CKN9u3uR+14WYp+MAfiG8bczVB4JyZXT+R32QXQCfccJ1RTzNbPn DIxgnb6bCYbGQsX3/DlTjzi+K+iNw4nQjuLw01f/KQlkiyIFnP1Rc6iCBXXRJZ40icnU wFeA== X-Gm-Message-State: AOAM530X0Il+y1qgygiZ24sUPwz0qEc1CSn2bPt1oui9Ecwjc89V37r8 sv8N25GXnw1+83ccYiwCQKX/GQ== X-Google-Smtp-Source: ABdhPJy/m2fd8w0CCNuqZQghcyRpWZjDcLth2YFgSdzKh3lSp8R2l2sKXrs9ou+B7FB/2TTr8wm/RQ== X-Received: by 2002:a17:907:8a12:b0:6f4:a586:de8f with SMTP id sc18-20020a1709078a1200b006f4a586de8fmr5251137ejc.514.1651667256735; Wed, 04 May 2022 05:27:36 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:36 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss Subject: [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC Date: Wed, 4 May 2022 14:27:23 +0200 Message-Id: <20220504122725.179262-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jonathan Marek Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- Changes since v1 - Remove comment - Dmitry Changes since v2 - Add my SoB - Bjorn - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag drivers/clk/qcom/Kconfig | 4 +-- drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++- 2 files changed, 61 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9b1f54e634b9..1752ca0ee405 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -609,11 +609,11 @@ config SM_DISPCC_6125 splash screen config SM_DISPCC_8250 - tristate "SM8150 and SM8250 Display Clock Controller" + tristate "SM8150/SM8250/SM8350 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8150 and SM8250 devices. + SM8150/SM8250/SM8350 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index db9379634fb2..8e6cb990e387 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { { 249600000, 2000000000, 0 }, }; +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + static struct alpha_pll_config disp_cc_pll0_config = { .l = 0x47, .alpha = 0xE000, @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { { .compatible = "qcom,sc8180x-dispcc" }, { .compatible = "qcom,sm8150-dispcc" }, { .compatible = "qcom,sm8250-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - /* note: trion == lucid, except for the prepare() op */ + /* Apply differences for SM8150 and SM8350 */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { + static struct clk_rcg2 * const rcgs[] = { + &disp_cc_mdss_byte0_clk_src, + &disp_cc_mdss_byte1_clk_src, + &disp_cc_mdss_dp_aux1_clk_src, + &disp_cc_mdss_dp_aux_clk_src, + &disp_cc_mdss_dp_link1_clk_src, + &disp_cc_mdss_dp_link_clk_src, + &disp_cc_mdss_dp_pixel1_clk_src, + &disp_cc_mdss_dp_pixel2_clk_src, + &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_mdp_clk_src, + &disp_cc_mdss_pclk0_clk_src, + &disp_cc_mdss_pclk1_clk_src, + &disp_cc_mdss_rot_clk_src, + &disp_cc_mdss_vsync_clk_src, + }; + static struct clk_regmap_div * const divs[] = { + &disp_cc_mdss_byte0_div_clk_src, + &disp_cc_mdss_byte1_div_clk_src, + &disp_cc_mdss_dp_link1_div_clk_src, + &disp_cc_mdss_dp_link_div_clk_src, + }; + unsigned int i; + static bool offset_applied; + + /* only apply the offsets once (in case of deferred probe) */ + if (!offset_applied) { + for (i = 0; i < ARRAY_SIZE(rcgs); i++) + rcgs[i]->cmd_rcgr -= 4; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + divs[i]->reg -= 4; + divs[i]->width = 4; + } + + disp_cc_mdss_ahb_clk.halt_reg -= 4; + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; + + offset_applied = true; + } + + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table = lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table = lucid_5lpe_vco; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); From patchwork Wed May 4 12:27:24 2022 Content-Type: text/plain; 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:37 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss , Rob Herring Subject: [PATCH v3 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Wed, 4 May 2022 14:27:24 +0200 Message-Id: <20220504122725.179262-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jonathan Marek Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov --- Changes since v2 - Add my SoB - Bjorn .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file From patchwork Wed May 4 12:27:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12837818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A1DC433FE for ; Wed, 4 May 2022 12:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349507AbiEDMbV (ORCPT ); Wed, 4 May 2022 08:31:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349503AbiEDMbR (ORCPT ); Wed, 4 May 2022 08:31:17 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC68C3120D for ; Wed, 4 May 2022 05:27:39 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id i19so2539287eja.11 for ; Wed, 04 May 2022 05:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wSkVCDsS62zbNJ0pEY1QFDEvKoD+8WUgtpzbx395WvY=; b=DaRwqlhRNHO1EnPDdwOSWog92eK26kNofbp4s0Fos4zPvsnCS8Bjw19MFnUzy/QhJi 8bsUbAldb5kFs7AwS8h4p4b37j3l1XHLSE1dst4bo26gViDCaf5QZjAlhCiKqwDUOHek nBjkv7BWGL/MKGEi2rZMDZNIicg80KiS48xn2SQJedhkTyBeaatWeDO+awOAGWsCy/5Y iFfTyA9lz4xt5o0ymwt7tp1oyiz5bqAI4AOF3T4D6kRhjZuDtWx/Z4Vw2SzrNm+/qG5q pka+cIaQ9ZJ8JWTodvy4Rls/W9X2jAxijLk/x/4xpc1SYUw7fdFW8QLouBN/vV/vyWnd HkBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wSkVCDsS62zbNJ0pEY1QFDEvKoD+8WUgtpzbx395WvY=; b=6QfvBscnuy+iwRO/87sL7r8EbbOZLQfkoq2lETCpTPLhfmJThrtz5kz6IPoFaGRg6q p8HYyPpJ8zwoDIdffrOLPBrKY/oIrAdVprbIR7Tmdp/X4Y75GbzcI0l5cVrtZKCNkFpR Z8D1TsZ/mYEok+OGZlOq4Rwxmxw+1euN5OMMF5JxCSjhac24BHXj+vbBLjvkYtpN9WbN 9UdIXybtBrfmrEUaf28IKniLAS05cfGRACNZrmNJrRA4B/sqEtgSO+7uABlYKxUs/wZl KxVuMH53LHswzA3e1PiW0CDfy7bpvP8tWU5ytrHUUQWUqaSA5Efp/MZDkCW8Hizy1M1z n+dQ== X-Gm-Message-State: AOAM533PrM75S/+g3+2hX5T0LHcDpbBQ9vZdzqOmzIxbsLo/sngMO+65 IZS2jCCRXbgQrmJA6k5lXbc9Uw== X-Google-Smtp-Source: ABdhPJwzeDWUbTfQMHvYIFofhoD3QAniWPEvnXcFRDNNGxaal3xPhaLMgDnS/4fcZIeiXrdarZQDHQ== X-Received: by 2002:a17:907:3e21:b0:6f4:6c7c:c781 with SMTP id hp33-20020a1709073e2100b006f46c7cc781mr9972155ejc.735.1651667259320; Wed, 04 May 2022 05:27:39 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id mm30-20020a170906cc5e00b006f3ef214e06sm5675557ejb.108.2022.05.04.05.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:27:38 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss Subject: [PATCH v3 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Date: Wed, 4 May 2022 14:27:25 +0200 Message-Id: <20220504122725.179262-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220504122725.179262-1-robert.foss@linaro.org> References: <20220504122725.179262-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- Changes since v2 - Remove interconnect include - Bjorn arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 52428b6df64e..99464cd1299e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -2525,6 +2526,31 @@ usb_2_dwc3: usb@a800000 { }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>;