From patchwork Wed May 4 13:05:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837882 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1446AC433F5 for ; Wed, 4 May 2022 13:05:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350199AbiEDNJb (ORCPT ); Wed, 4 May 2022 09:09:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344202AbiEDNJ3 (ORCPT ); Wed, 4 May 2022 09:09:29 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A39512F00B; Wed, 4 May 2022 06:05:50 -0700 (PDT) X-UUID: 0cdd07134d494d70b6bbebba00ebe54a-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:0c7d9dcb-5444-4062-9682-71b3d1575ba1,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:0c7d9dcb-5444-4062-9682-71b3d1575ba1,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:1db32c16-2e53-443e-b81a-655c13977218,C OID:5ccef16228e4,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 0cdd07134d494d70b6bbebba00ebe54a-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1254656210; Wed, 04 May 2022 21:05:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 1/9] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property Date: Wed, 4 May 2022 21:05:32 +0800 Message-ID: <20220504130540.5902-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module for scaling clock frequency and adjust voltage. The phandle could be linked between CPU and MediaTek CCI for some MediaTek SoCs, like MT8183 and MT8186. The reason we need the link status between cpufreq and MediaTek cci is cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. Therefore, to prevent the issue of high frequency and low voltage, we need to use this to make sure mediatek cci is ready. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt index b8233ec91d3d..e0a4ba599abc 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt @@ -20,6 +20,13 @@ Optional properties: Vsram to fit SoC specific needs. When absent, the voltage scaling flow is handled by hardware, hence no software "voltage tracking" is needed. +- mediatek,cci: + Used to confirm the link status between cpufreq and mediatek cci. Because + cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. + To prevent the issue of high frequency and low voltage, we need to use this + property to make sure mediatek cci is ready. + For details of mediatek cci, please refer to + Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml - #cooling-cells: For details, please refer to Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml From patchwork Wed May 4 13:05:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837884 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11FABC433F5 for ; Wed, 4 May 2022 13:06:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350182AbiEDNJp (ORCPT ); Wed, 4 May 2022 09:09:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350151AbiEDNJa (ORCPT ); Wed, 4 May 2022 09:09:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A31992D1FE; Wed, 4 May 2022 06:05:48 -0700 (PDT) X-UUID: 16a14344a37d49ca862e2d36314b2450-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:73ae4dd8-54ab-42eb-965e-dbcd88de9e64,OB:10,L OB:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:73ae4dd8-54ab-42eb-965e-dbcd88de9e64,OB:10,LOB :20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:1fb32c16-2e53-443e-b81a-655c13977218,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 16a14344a37d49ca862e2d36314b2450-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 959914227; Wed, 04 May 2022 21:05:42 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:41 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 3/9] cpufreq: mediatek: Move voltage limits to platform data Date: Wed, 4 May 2022 21:05:34 +0800 Message-ID: <20220504130540.5902-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jia-Wei Chang Voltages and shifts are defined as macros originally. There are different requirements of these values for each MediaTek SoCs. Therefore, we add the platform data and move these values into it. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq.c | 90 ++++++++++++++++++++---------- 1 file changed, 61 insertions(+), 29 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 363ebecb2c80..80a3d4cd49ed 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -10,15 +10,21 @@ #include #include #include +#include #include #include #include -#define MIN_VOLT_SHIFT (100000) -#define MAX_VOLT_SHIFT (200000) -#define MAX_VOLT_LIMIT (1150000) #define VOLT_TOL (10000) +struct mtk_cpufreq_platform_data { + int min_volt_shift; + int max_volt_shift; + int proc_max_volt; + int sram_min_volt; + int sram_max_volt; +}; + /* * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in @@ -46,8 +52,11 @@ struct mtk_cpu_dvfs_info { struct notifier_block opp_nb; unsigned int opp_cpu; unsigned long opp_freq; + const struct mtk_cpufreq_platform_data *soc_data; }; +static struct platform_device *cpufreq_pdev; + static LIST_HEAD(dvfs_info_list); static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) @@ -65,6 +74,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, int new_vproc) { + const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; struct regulator *proc_reg = info->proc_reg; struct regulator *sram_reg = info->sram_reg; int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; @@ -76,7 +86,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vproc; } /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); + new_vsram = min(new_vproc + soc_data->min_volt_shift, + soc_data->sram_max_volt); if (pre_vproc < new_vproc) { /* @@ -99,10 +110,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vproc; } - vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); + vsram = min(new_vsram, + pre_vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { + vsram = soc_data->sram_max_volt; /* * If the target Vsram hits the maximum voltage, @@ -120,7 +132,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, ret = regulator_set_voltage(sram_reg, vsram, vsram + VOLT_TOL); - vproc = vsram - MIN_VOLT_SHIFT; + vproc = vsram - soc_data->min_volt_shift; } if (ret) return ret; @@ -154,7 +166,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vsram; } - vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); + vproc = max(new_vproc, + pre_vsram - soc_data->max_volt_shift); ret = regulator_set_voltage(proc_reg, vproc, vproc + VOLT_TOL); if (ret) @@ -163,10 +176,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, if (vproc == new_vproc) vsram = new_vsram; else - vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); + vsram = max(new_vsram, + vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { + vsram = soc_data->sram_max_volt; /* * If the target Vsram hits the maximum voltage, @@ -197,13 +211,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) { + const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; int ret; if (info->need_voltage_tracking) ret = mtk_cpufreq_voltage_tracking(info, vproc); else ret = regulator_set_voltage(info->proc_reg, vproc, - MAX_VOLT_LIMIT); + soc_data->proc_max_volt); if (!ret) info->pre_vproc = vproc; @@ -583,9 +598,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = { static int mtk_cpufreq_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct mtk_cpu_dvfs_info *info, *tmp; int cpu, ret; + match = dev_get_platdata(&pdev->dev); + if (!match || !match->data) { + dev_err(&pdev->dev, + "failed to get mtk cpufreq platform data\n"); + return -ENODEV; + } + for_each_possible_cpu(cpu) { info = mtk_cpu_dvfs_info_lookup(cpu); if (info) @@ -597,6 +620,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev) goto release_dvfs_info_list; } + info->soc_data = match->data; ret = mtk_cpu_dvfs_info_init(info, cpu); if (ret) { dev_err(&pdev->dev, @@ -632,20 +656,27 @@ static struct platform_driver mtk_cpufreq_platdrv = { .probe = mtk_cpufreq_probe, }; +static const struct mtk_cpufreq_platform_data mt2701_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, + .proc_max_volt = 1150000, + .sram_min_volt = 0, + .sram_max_volt = 1150000, +}; + /* List of machines supported by this driver */ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", }, - { .compatible = "mediatek,mt2712", }, - { .compatible = "mediatek,mt7622", }, - { .compatible = "mediatek,mt7623", }, - { .compatible = "mediatek,mt8167", }, - { .compatible = "mediatek,mt817x", }, - { .compatible = "mediatek,mt8173", }, - { .compatible = "mediatek,mt8176", }, - { .compatible = "mediatek,mt8183", }, - { .compatible = "mediatek,mt8365", }, - { .compatible = "mediatek,mt8516", }, - + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); @@ -654,7 +685,6 @@ static int __init mtk_cpufreq_driver_init(void) { struct device_node *np; const struct of_device_id *match; - struct platform_device *pdev; int err; np = of_find_node_by_path("/"); @@ -678,11 +708,12 @@ static int __init mtk_cpufreq_driver_init(void) * and the device registration codes are put here to handle defer * probing. */ - pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); - if (IS_ERR(pdev)) { + cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, + match, sizeof(*match)); + if (IS_ERR(cpufreq_pdev)) { pr_err("failed to register mtk-cpufreq platform device\n"); platform_driver_unregister(&mtk_cpufreq_platdrv); - return PTR_ERR(pdev); + return PTR_ERR(cpufreq_pdev); } return 0; @@ -691,6 +722,7 @@ module_init(mtk_cpufreq_driver_init) static void __exit mtk_cpufreq_driver_exit(void) { + platform_device_unregister(cpufreq_pdev); platform_driver_unregister(&mtk_cpufreq_platdrv); } module_exit(mtk_cpufreq_driver_exit) From patchwork Wed May 4 13:05:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837900 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41B6EC4321E for ; Wed, 4 May 2022 13:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343688AbiEDNJu (ORCPT ); Wed, 4 May 2022 09:09:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344202AbiEDNJn (ORCPT ); Wed, 4 May 2022 09:09:43 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A23831CB3F; Wed, 4 May 2022 06:05:51 -0700 (PDT) X-UUID: c23191fcedaa4ddfb7a52f89b07961d1-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:b75a05ea-8af4-4f4b-ba0d-e318cb4ce5ff,OB:20,L OB:30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:b75a05ea-8af4-4f4b-ba0d-e318cb4ce5ff,OB:20,LOB :30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:17b32c16-2e53-443e-b81a-655c13977218,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: c23191fcedaa4ddfb7a52f89b07961d1-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 915530431; Wed, 04 May 2022 21:05:42 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:41 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 4/9] cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking() Date: Wed, 4 May 2022 21:05:35 +0800 Message-ID: <20220504130540.5902-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jia-Wei Chang Because the difference of sram and proc should in a range of min_volt_shift and max_volt_shift. We need to adjust the sram and proc step by step. We replace VOLT_TOL (voltage tolerance) with the platform data and update the logic to determine the voltage boundary and invoking regulator_set_voltage. - Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary of sram regulator. - Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the voltage boundary of vproc regulator. Moreover, to prevent infinite loop when tracking voltage, we calculate the maximum value for each platform data. We assume min voltage is 0 and tracking target voltage using min_volt_shift for each iteration. The retry_max is 3 times of expeted iteration count. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++------------------- 1 file changed, 51 insertions(+), 96 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 80a3d4cd49ed..c9f09ddd4428 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,8 +16,6 @@ #include #include -#define VOLT_TOL (10000) - struct mtk_cpufreq_platform_data { int min_volt_shift; int max_volt_shift; @@ -53,6 +52,7 @@ struct mtk_cpu_dvfs_info { unsigned int opp_cpu; unsigned long opp_freq; const struct mtk_cpufreq_platform_data *soc_data; + int vtrack_max; }; static struct platform_device *cpufreq_pdev; @@ -78,6 +78,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, struct regulator *proc_reg = info->proc_reg; struct regulator *sram_reg = info->sram_reg; int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; + int retry = info->vtrack_max; pre_vproc = regulator_get_voltage(proc_reg); if (pre_vproc < 0) { @@ -85,91 +86,44 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, "invalid Vproc value: %d\n", pre_vproc); return pre_vproc; } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + soc_data->min_volt_shift, - soc_data->sram_max_volt); - - if (pre_vproc < new_vproc) { - /* - * When scaling up voltages, Vsram and Vproc scale up step - * by step. At each step, set Vsram to (Vproc + 200mV) first, - * then set Vproc to (Vsram - 100mV). - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { - pre_vsram = regulator_get_voltage(sram_reg); - if (pre_vsram < 0) { - dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", pre_vsram); - return pre_vsram; - } - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } - - vsram = min(new_vsram, - pre_vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { - vsram = soc_data->sram_max_volt; + pre_vsram = regulator_get_voltage(sram_reg); + if (pre_vsram < 0) { + dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); + return pre_vsram; + } - /* - * If the target Vsram hits the maximum voltage, - * try to set the exact voltage value first. - */ - ret = regulator_set_voltage(sram_reg, vsram, - vsram); - if (ret) - ret = regulator_set_voltage(sram_reg, - vsram - VOLT_TOL, - vsram); + new_vsram = clamp(new_vproc + soc_data->min_volt_shift, + soc_data->sram_min_volt, soc_data->sram_max_volt); - vproc = new_vproc; - } else { - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); + do { + if (pre_vproc <= new_vproc) { + vsram = clamp(pre_vproc + soc_data->max_volt_shift, + soc_data->sram_min_volt, new_vsram); + ret = regulator_set_voltage(sram_reg, vsram, + soc_data->sram_max_volt); - vproc = vsram - soc_data->min_volt_shift; - } if (ret) return ret; + if (vsram == soc_data->sram_max_volt || + new_vsram == soc_data->sram_min_volt) + vproc = new_vproc; + else + vproc = vsram - soc_data->min_volt_shift; + ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); + soc_data->proc_max_volt); if (ret) { regulator_set_voltage(sram_reg, pre_vsram, - pre_vsram); + soc_data->sram_max_volt); return ret; } - } while (vproc < new_vproc || vsram < new_vsram); - } else if (pre_vproc > new_vproc) { - /* - * When scaling down voltages, Vsram and Vproc scale down step - * by step. At each step, set Vproc to (Vsram - 200mV) first, - * then set Vproc to (Vproc + 100mV). - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } - pre_vsram = regulator_get_voltage(sram_reg); - if (pre_vsram < 0) { - dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", pre_vsram); - return pre_vsram; - } - + } else if (pre_vproc > new_vproc) { vproc = max(new_vproc, pre_vsram - soc_data->max_volt_shift); ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); + soc_data->proc_max_volt); if (ret) return ret; @@ -179,32 +133,24 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, vsram = max(new_vsram, vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { - vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, - * try to set the exact voltage value first. - */ - ret = regulator_set_voltage(sram_reg, vsram, - vsram); - if (ret) - ret = regulator_set_voltage(sram_reg, - vsram - VOLT_TOL, - vsram); - } else { - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); - } - + ret = regulator_set_voltage(sram_reg, vsram, + soc_data->sram_max_volt); if (ret) { regulator_set_voltage(proc_reg, pre_vproc, - pre_vproc); + soc_data->proc_max_volt); return ret; } - } while (vproc > new_vproc + VOLT_TOL || - vsram > new_vsram + VOLT_TOL); - } + } + + pre_vproc = vproc; + pre_vsram = vsram; + + if (--retry < 0) { + dev_err(info->cpu_dev, + "over loop count, failed to set voltage\n"); + return -EINVAL; + } + } while (vproc != new_vproc || vsram != new_vsram); return 0; } @@ -268,8 +214,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. */ - target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; - if (pre_vproc < target_vproc) { + target_vproc = max(inter_vproc, vproc); + if (pre_vproc <= target_vproc) { ret = mtk_cpufreq_set_voltage(info, target_vproc); if (ret) { dev_err(cpu_dev, @@ -490,6 +436,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) */ info->need_voltage_tracking = (info->sram_reg != NULL); + /* + * We assume min voltage is 0 and tracking target voltage using + * min_volt_shift for each iteration. + * The vtrack_max is 3 times of expeted iteration count. + */ + info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, + info->soc_data->proc_max_volt), + info->soc_data->min_volt_shift); + return 0; out_disable_inter_clock: From patchwork Wed May 4 13:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837899 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8EBBC43217 for ; Wed, 4 May 2022 13:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350202AbiEDNJw (ORCPT ); Wed, 4 May 2022 09:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350200AbiEDNJb (ORCPT ); Wed, 4 May 2022 09:09:31 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2B392DA9B; Wed, 4 May 2022 06:05:52 -0700 (PDT) X-UUID: ad26d81e1d15409196e62563f77b68fc-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:576b7779-7dd4-404c-8ebe-10aa4da612b5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:385e8cb2-56b5-4c9e-8d83-0070b288eb6a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: ad26d81e1d15409196e62563f77b68fc-20220504 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 571115399; Wed, 04 May 2022 21:05:43 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 5/9] cpufreq: mediatek: Link CCI device to CPU Date: Wed, 4 May 2022 21:05:36 +0800 Message-ID: <20220504130540.5902-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In some MediaTek SoCs, like MT8183, CPU and CCI share the same power supplies. Cpufreq needs to check if CCI devfreq exists and wait until CCI devfreq ready before scaling frequency. Before CCI devfreq is ready, we record the voltage when booting to kernel and use the max(cpu target voltage, booting voltage) to prevent cpufreq adjust to the lower voltage which will cause the CCI crash because of high frequency and low voltage. - Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start DVFS when CCI is ready. - Add platform data for MT8183. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Kevin Hilman --- drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index c9f09ddd4428..1a4c95e06b0e 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data { int proc_max_volt; int sram_min_volt; int sram_max_volt; + bool ccifreq_supported; }; /* @@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data { struct mtk_cpu_dvfs_info { struct cpumask cpus; struct device *cpu_dev; + struct device *cci_dev; struct regulator *proc_reg; struct regulator *sram_reg; struct clk *cpu_clk; @@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info { struct list_head list_head; int intermediate_voltage; bool need_voltage_tracking; + int vproc_on_boot; int pre_vproc; /* Avoid race condition for regulators between notify and policy */ struct mutex reg_lock; @@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info { unsigned long opp_freq; const struct mtk_cpufreq_platform_data *soc_data; int vtrack_max; + bool ccifreq_bound; }; static struct platform_device *cpufreq_pdev; @@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) return ret; } +static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) +{ + struct device_link *sup_link; + + if (info->ccifreq_bound) + return true; + + sup_link = device_link_add(info->cpu_dev, info->cci_dev, + DL_FLAG_AUTOREMOVE_CONSUMER); + if (!sup_link) { + dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); + return false; + } + + if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) + return false; + + info->ccifreq_bound = true; + + return true; +} + static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { @@ -210,6 +236,14 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, vproc = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + /* + * If MediaTek cci is supported but is not ready, we will use the value + * of max(target cpu voltage, booting voltage) to prevent high freqeuncy + * low voltage crash. + */ + if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) + vproc = max(vproc, info->vproc_on_boot); + /* * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. @@ -331,6 +365,23 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, return notifier_from_errno(ret); } +static struct device *of_get_cci(struct device *cpu_dev) +{ + struct device_node *np; + struct platform_device *pdev; + + np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); + if (IS_ERR_OR_NULL(np)) + return NULL; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (IS_ERR_OR_NULL(pdev)) + return NULL; + + return &pdev->dev; +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -345,6 +396,16 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) } info->cpu_dev = cpu_dev; + info->ccifreq_bound = false; + if (info->soc_data->ccifreq_supported) { + info->cci_dev = of_get_cci(info->cpu_dev); + if (IS_ERR_OR_NULL(info->cci_dev)) { + ret = PTR_ERR(info->cci_dev); + dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); + return -ENODEV; + } + } + info->cpu_clk = clk_get(cpu_dev, "cpu"); if (IS_ERR(info->cpu_clk)) { ret = PTR_ERR(info->cpu_clk); @@ -408,6 +469,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) if (ret) goto out_disable_mux_clock; + if (info->soc_data->ccifreq_supported) { + info->vproc_on_boot = regulator_get_voltage(info->proc_reg); + if (info->vproc_on_boot < 0) { + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", info->vproc_on_boot); + goto out_disable_inter_clock; + } + } + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(info->inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); @@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = { .proc_max_volt = 1150000, .sram_min_volt = 0, .sram_max_volt = 1150000, + .ccifreq_supported = false, +}; + +static const struct mtk_cpufreq_platform_data mt8183_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, + .proc_max_volt = 1150000, + .sram_min_volt = 0, + .sram_max_volt = 1150000, + .ccifreq_supported = true, }; /* List of machines supported by this driver */ @@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } From patchwork Wed May 4 13:05:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837883 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 435A5C433FE for ; Wed, 4 May 2022 13:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350070AbiEDNJn (ORCPT ); Wed, 4 May 2022 09:09:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346831AbiEDNJ3 (ORCPT ); Wed, 4 May 2022 09:09:29 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5E782E9F7; Wed, 4 May 2022 06:05:49 -0700 (PDT) X-UUID: 1b65d44fdfa94193bd36c75894d52f28-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:1c60cf9d-92a6-4d1c-9255-0143af88f7f9,OB:30,L OB:40,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:1c60cf9d-92a6-4d1c-9255-0143af88f7f9,OB:30,LOB :40,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:fd5d8cb2-56b5-4c9e-8d83-0070b288eb6a,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 1b65d44fdfa94193bd36c75894d52f28-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1491984491; Wed, 04 May 2022 21:05:42 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 6/9] cpufreq: mediatek: Add support for MT8186 Date: Wed, 4 May 2022 21:05:37 +0800 Message-ID: <20220504130540.5902-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jia-Wei Chang The platform data of MT8186 is different from previous MediaTek SoCs, so we add a new compatible and platform data for it. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 1a4c95e06b0e..60d6292ab306 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform_data mt8183_platform_data = { .ccifreq_supported = true, }; +static const struct mtk_cpufreq_platform_data mt8186_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 250000, + .proc_max_volt = 1118750, + .sram_min_volt = 850000, + .sram_max_volt = 1118750, + .ccifreq_supported = true, +}; + /* List of machines supported by this driver */ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, @@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, + { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } From patchwork Wed May 4 13:05:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837901 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C41B2C433F5 for ; Wed, 4 May 2022 13:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350252AbiEDNJw (ORCPT ); Wed, 4 May 2022 09:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243356AbiEDNJn (ORCPT ); Wed, 4 May 2022 09:09:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA9522FFF5; Wed, 4 May 2022 06:05:50 -0700 (PDT) X-UUID: 6d3f87a2db3447d08285122a2463735c-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:33340734-73ed-475c-86c2-12cd454051dc,OB:50,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:33340734-73ed-475c-86c2-12cd454051dc,OB:50,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:52b32c16-2e53-443e-b81a-655c13977218,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 6d3f87a2db3447d08285122a2463735c-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 675211899; Wed, 04 May 2022 21:05:43 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 4 May 2022 21:05:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:42 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen , "Andrew-sh . Cheng" Subject: [PATCH v5 7/9] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq Date: Wed, 4 May 2022 21:05:38 +0800 Message-ID: <20220504130540.5902-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org - Add cpufreq opp table. - Add MediaTek cci opp table. - Add property of opp table and clock fro cpufreq. Signed-off-by: Andrew-sh.Cheng Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270 ++++++++++++++++++++ 2 files changed, 302 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index f3fd3cca23e9..8953dbf84f3e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -412,6 +412,38 @@ }; +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 01e650251928..cecf96b628b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -42,6 +42,244 @@ rdma1 = &rdma1; }; + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + opp0-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + required-opps = <&opp2_00>; + }; + opp0-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <687500>; + required-opps = <&opp2_01>; + }; + opp0-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <718750>; + required-opps = <&opp2_02>; + }; + opp0-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <756250>; + required-opps = <&opp2_03>; + }; + opp0-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp0-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <818750>; + required-opps = <&opp2_05>; + }; + opp0-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp0-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <868750>; + required-opps = <&opp2_07>; + }; + opp0-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <893750>; + required-opps = <&opp2_08>; + }; + opp0-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <906250>; + required-opps = <&opp2_09>; + }; + opp0-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp0-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <943750>; + required-opps = <&opp2_11>; + }; + opp0-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp0-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp0-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp0-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + opp1-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <700000>; + required-opps = <&opp2_00>; + }; + opp1-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <725000>; + required-opps = <&opp2_01>; + }; + opp1-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <750000>; + required-opps = <&opp2_02>; + }; + opp1-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <775000>; + required-opps = <&opp2_03>; + }; + opp1-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp1-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <825000>; + required-opps = <&opp2_05>; + }; + opp1-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp1-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <875000>; + required-opps = <&opp2_07>; + }; + opp1-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <900000>; + required-opps = <&opp2_08>; + }; + opp1-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <912500>; + required-opps = <&opp2_09>; + }; + opp1-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp1-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <950000>; + required-opps = <&opp2_11>; + }; + opp1-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp1-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp1-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp1-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,6 +323,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -96,6 +338,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -107,6 +353,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -118,6 +368,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -129,6 +383,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -140,6 +398,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -151,6 +413,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -162,6 +428,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; From patchwork Wed May 4 13:05:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837881 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C96AAC433FE for ; Wed, 4 May 2022 13:05:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347049AbiEDNJa (ORCPT ); Wed, 4 May 2022 09:09:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350317AbiEDNJ2 (ORCPT ); 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Wed, 04 May 2022 21:05:43 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:42 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen , "Andrew-sh . Cheng" Subject: [PATCH v5 8/9] arm64: dts: mediatek: Add MediaTek CCI node for MT8183 Date: Wed, 4 May 2022 21:05:39 +0800 Message-ID: <20220504130540.5902-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add MediaTek CCI devfreq node for MT8183. Signed-off-by: Andrew-sh.Cheng Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 8953dbf84f3e..7ac9864db9de 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -412,6 +412,10 @@ }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 8d5bf73a9099..b035e06840e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -230,6 +230,10 @@ status = "okay"; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index cecf96b628b7..11caf3dd85cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -280,6 +280,13 @@ }; }; + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; + clock-names = "cci_clock"; + operating-points-v2 = <&cci_opp>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; From patchwork Wed May 4 13:05:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12837885 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D7CDC433FE for ; Wed, 4 May 2022 13:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230337AbiEDNJq (ORCPT ); Wed, 4 May 2022 09:09:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350187AbiEDNJa (ORCPT ); Wed, 4 May 2022 09:09:30 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E26432A246; Wed, 4 May 2022 06:05:51 -0700 (PDT) X-UUID: 3dd8948e5a12483e8e8d547a14062e61-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ef2b04ee-c0e0-4504-9fe4-65e810c6d8ae,OB:40,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:ef2b04ee-c0e0-4504-9fe4-65e810c6d8ae,OB:40,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:375e8cb2-56b5-4c9e-8d83-0070b288eb6a,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 3dd8948e5a12483e8e8d547a14062e61-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 639549240; Wed, 04 May 2022 21:05:43 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 4 May 2022 21:05:42 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:42 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 9/9] arm64: dts: mediatek: Add mediatek,cci property for MT8183 cpufreq Date: Wed, 4 May 2022 21:05:40 +0800 Message-ID: <20220504130540.5902-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add mediatek,cci property to support MediaTek CCI feature. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 11caf3dd85cd..e5d4a8e0c545 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -336,6 +336,7 @@ operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@1 { @@ -351,6 +352,7 @@ operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@2 { @@ -366,6 +368,7 @@ operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@3 { @@ -381,6 +384,7 @@ operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@100 { @@ -396,6 +400,7 @@ operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@101 { @@ -411,6 +416,7 @@ operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@102 { @@ -426,6 +432,7 @@ operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@103 { @@ -441,6 +448,7 @@ operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states {