From patchwork Sat May 7 20:29:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 754E8C43217 for ; Sat, 7 May 2022 20:29:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245448AbiEGUdl (ORCPT ); Sat, 7 May 2022 16:33:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234125AbiEGUdk (ORCPT ); Sat, 7 May 2022 16:33:40 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBD51BC95; Sat, 7 May 2022 13:29:52 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id z2so18549515ejj.3; Sat, 07 May 2022 13:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Tof11gWdZVMZxib9oySvQf9mu+NWMt2gs2nvPMKj0h4=; b=C3ZuLoKoR2iCe5UXuOCY/VW4LgEWX+8cpj5smDSCHQ4HIxFwlin1LDpr07fod8mdxn wzlv2MY2QGIDFPZJ66WpRVOQuqiq1QwIsCZxq612RI9rGUcF4XG2rTUxWlDiRvv1GNjz p6ZOK68mjBiVohcMZTFTwnYaTzod5W6CJCUzyNufehejYA2CeJ6Wwc8jDOWPTZ1ZChf9 /ZkiskxHHwnXLTd6E///2f6IJqaKF0cDDUMpV7Tdcp2VhynpeIz3G68PEx6CZdRwWL6E RgAi4BtoNJz2Cc1b7glnp/0wU314fkJrknE9txUxrgjuxeCX/uebtm4bWMeT+LNKIMfC 32tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Tof11gWdZVMZxib9oySvQf9mu+NWMt2gs2nvPMKj0h4=; b=AMtU0J7cTBAb3gC+izXhw+S2nsLhhTqLT/4FjW1pHAK0Xix9oSEfrqATxV6m3Z3sZz NbgWAWlwq5bdSSHatu4Ez28NWJdzY0U9yQm2o8/88UxGKac37Ugs1i+ktnRFEyF7IB2M ukV1/JXm1Udjy7c7LZofrBxwMaqmnN9Xc4Q/lnz8O2xPeepFEtXXluMS7J6CucSztWrQ BQwjlPWmcAJ6zw94fqc64aw2e5dmKgD5mMTk6BeltM0l5lUPcZaKM6hGOoIgt9/gBAPJ Ly0zr52LNR5Xm854+m8cf2KhIbca/Um7pxjCQIaRJLI92VENVN4hwl/SUQK/0/pFxE9S CEAg== X-Gm-Message-State: AOAM530Y8ZO7+/j7/BiHfmEqDWtq2495EZoZ8yrIkIls7BUlJfxbmz+4 klGJbDPG4ZZEzvWAXCQQIqU= X-Google-Smtp-Source: ABdhPJwBO0kpC+X39nkzexVVOGLumhjhW2iK1jvS8kyu1A/7LVkn+ROZIbfovMRTEgh0n3UkKCAOCg== X-Received: by 2002:a17:906:27cd:b0:6f3:c015:e40d with SMTP id k13-20020a17090627cd00b006f3c015e40dmr8948239ejc.15.1651955391231; Sat, 07 May 2022 13:29:51 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:50 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 01/11] clk: qcom: ipq8074: fix NSS core PLL-s Date: Sat, 7 May 2022 22:29:38 +0200 Message-Id: <20220507202948.397271-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 541016db3c4b..1a5141da7e23 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4772,7 +4799,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { From patchwork Sat May 7 20:29:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 429ADC433FE for ; Sat, 7 May 2022 20:30:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387236AbiEGUdp (ORCPT ); Sat, 7 May 2022 16:33:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387182AbiEGUdn (ORCPT ); Sat, 7 May 2022 16:33:43 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D64BBC95; Sat, 7 May 2022 13:29:54 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id t5so12138635edw.11; Sat, 07 May 2022 13:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dghnijSd8lgtthMZ/SJImobMXWMBJhXwTeRnVajL27E=; b=Sd0f9pL+Ygu7NqDD845vGjqUQO9V0ROI1aXT4DBkeJw63xzBc1tDUQtggUFGJv2cGy zQDIAL+SqwW2Kr+nEzlVRr0I9Q7ip6xe1aSIvYZE9dGHJzB5Al8VVaW1fA+YgFQ5qfw6 BpvX2E1i/Q2hVKlz+FPOhUcn+6B5h+Ki+QaEPeW0f/Cd9vaDS2d+r9T9QQtYdzlmw/E2 M9m0XjizgR+xAlSd1kz1wBdujaobOpV0zurDiQNiYOIQ9N4q2W/ZeeOWlI5GWHuGd4fe nHXURlWtVCKXsqfEGBgp8jKP6QoGHIirIqlEQRNW20gfQtne6NESJB3gttPkOqVQqw6L g5Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dghnijSd8lgtthMZ/SJImobMXWMBJhXwTeRnVajL27E=; b=zDilwQ7SE10s/2zbDgKHz7pINrLdMZWswV4wXWnEEcxVKLmd+V3E9zZIwGGt6rkHcz HzytHCwzeP0mvE2LYDpa01BInndmTQ7hFAQZ1JkobGVeiWUCmDue4omG69XlDiLipyti BefJb4O7J7TntDMIIs+x+GQJTz6ie3++wHGDEavH/dPF2rA3yENX3YYPl0vDsB6Tm69i tuyAT5hIfMhHDX0ULuUbWduLX/qQkEXYh6nMPClg7X6DzL3188tr8aHEAS/Buw6XgTQh iNrMB/K+QxpSg/psaRL9Hk6j7e2OZi5H1vHzb+Yuoeyf6nMsqfqbKaP8bTVHkixEIHhC VhVg== X-Gm-Message-State: AOAM530GIGOxKOdoW2CMrCi1BGvwNwLVEU92u2G2vT3PxSxZdXUhHZ9X DIvfuyVBYge7xwRVO9ukwMA= X-Google-Smtp-Source: ABdhPJwrD4sV3bY7dBOyEXb5y0JCQNB5YHsOYY8Ua3+A99XBNx5tHhDGEO+FNhdz69Nza5+gypGCgw== X-Received: by 2002:a05:6402:d05:b0:425:b7ab:776e with SMTP id eb5-20020a0564020d0500b00425b7ab776emr9975258edb.142.1651955392857; Sat, 07 May 2022 13:29:52 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:52 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 02/11] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock Date: Sat, 7 May 2022 22:29:39 +0200 Message-Id: <20220507202948.397271-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1a5141da7e23..b4291ba53c78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4805,6 +4805,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* SW Workaround for UBI32 Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From patchwork Sat May 7 20:29:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33A61C4332F for ; Sat, 7 May 2022 20:30:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387207AbiEGUdo (ORCPT ); Sat, 7 May 2022 16:33:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387194AbiEGUdn (ORCPT ); Sat, 7 May 2022 16:33:43 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F15B1BC99; Sat, 7 May 2022 13:29:55 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id ba17so12163189edb.5; Sat, 07 May 2022 13:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MVsuzFv9nImFGpDrqebroDd7vxQ+CQ3cbUIBolPZTpE=; b=nTyJjN7cBhOrq/T0R7DQ/2HurtjwJuJVm0LgIkFe3g4pfl7QfeN9zuSG5X93bRihvR LL5gfjRsN5YuqsY0o2ii19nyU24EOZEtx7dWBuudoD9QhO98f28D7c+D+fXzsFW2fElE DEw3pnMzyg+LHerAncpuURMT8DmJzofg7YveSicDfqHD76JsdY0gSKAQjrWfO3Y994NZ Doj/IlWRLvb64F8qHj2914ltUZ2jVtbk8fWixbLTOP0Oa/xGO973vgrFqWfBwmkwUyL+ vF6nIjS89dagMk/a6xWHaS7R+3UCnShL/qhU6yPMwkQuJcOYpTSTCRPdUsGUXPeHlpnU Xu3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MVsuzFv9nImFGpDrqebroDd7vxQ+CQ3cbUIBolPZTpE=; b=7/hz6J+NIeZOPBkSUcc3mCsc+ZIh/dOohdcA9nvjpbpn2+jEAtzRAg0K8th8X+3bIQ eIL0U4ywHicaJGC+gDASJt/YRT35snTZDVb9IAIIG3GNcus02oyPZ0DMbDOh8bpp9PGS 6x1gkAxRTMpWkm4bjtADpQNHBNL4dq429u9Yf9cOA4ZsSvDd8EAg0e4r0Ev5wUdG9CxL hNrivbSWLr3y+8Jqf6JS+hzXzU/tvLVDs6StgqR8LLP63jN/veZ5APInbnVPc1UA3yy3 epEh54KQ+VDe+PD4YVS6ZVJtDUnxJPavPYijzecyDDQ0sZc7k1pKdPyHgDItiHtjt3CH tbOQ== X-Gm-Message-State: AOAM530CnWr0u8jD4cAZ2m9ujWMNGA61JyICPHDIprFvuwQIUjBUhdvm prAFip+unYx0hJLtA3rTw7BAiuQLfo+baA== X-Google-Smtp-Source: ABdhPJxHQU0dvQr9rPl0/XdeFJKsyLibl4dVUb1raUn89rz69rq0Xw5IacLnprtVj6YJFvRyMez64g== X-Received: by 2002:aa7:d416:0:b0:425:f5c7:d633 with SMTP id z22-20020aa7d416000000b00425f5c7d633mr9832309edq.105.1651955394531; Sat, 07 May 2022 13:29:54 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:54 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 03/11] clk: qcom: ipq8074: fix NSS port frequency tables Date: Sat, 7 May 2022 22:29:40 +0200 Message-Id: <20220507202948.397271-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index b4291ba53c78..f1017f2e61bd 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_RX, 5, 0, 0), F(78125000, P_UNIPHY1_RX, 4, 0, 0), F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_RX, 1, 0, 0), F(156250000, P_UNIPHY1_RX, 2, 0, 0), F(312500000, P_UNIPHY1_RX, 1, 0, 0), { } @@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_TX, 5, 0, 0), F(78125000, P_UNIPHY1_TX, 4, 0, 0), F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_TX, 1, 0, 0), F(156250000, P_UNIPHY1_TX, 2, 0, 0), F(312500000, P_UNIPHY1_TX, 1, 0, 0), { } @@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_RX, 5, 0, 0), F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), F(78125000, P_UNIPHY2_RX, 4, 0, 0), + F(125000000, P_UNIPHY2_RX, 1, 0, 0), F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), F(156250000, P_UNIPHY2_RX, 2, 0, 0), F(312500000, P_UNIPHY2_RX, 1, 0, 0), @@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_TX, 5, 0, 0), F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), F(78125000, P_UNIPHY2_TX, 4, 0, 0), + F(125000000, P_UNIPHY2_TX, 1, 0, 0), F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), F(156250000, P_UNIPHY2_TX, 2, 0, 0), F(312500000, P_UNIPHY2_TX, 1, 0, 0), From patchwork Sat May 7 20:29:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD2C4C433EF for ; Sat, 7 May 2022 20:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387287AbiEGUdq (ORCPT ); Sat, 7 May 2022 16:33:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234125AbiEGUdo (ORCPT ); Sat, 7 May 2022 16:33:44 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76BB8BC95; Sat, 7 May 2022 13:29:57 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id m20so20105066ejj.10; Sat, 07 May 2022 13:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=55DAttT0wioJdsCUuVQUMBFRWSPkGrAf7r5fkDcJSFU=; b=QotIbjq4oy5plz50K8j0OCUcC6S5yDKTI3314ifmsZpThiEzZqR7iShyXlCQtaCthX AqEH8kEz8TqpPDe0IIXWRhd/P9Wmj7GS8tmaj2ZqdELTiqO2AL1v4/dydN6j6x2JMLSY l9sx/LYT/Rc4Gh66RntAQsmhWAVN6VZyqCC5Q2C3vpalHCLVvf/GLSryrWAagzUjEkhP +YruJuAYv7V1/P8LQgm14pj8O4OPHt8ytKC31NoQBQZeRGN+rcYC9GIW/yXPPF6zxE+a TfWXLgXlsD4HXJ/HyUPBBgI2Ksje7mz8fXJ+8MrWdUQKAUllUzkF+0xZ3jmc7Ypd/LKf /FJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=55DAttT0wioJdsCUuVQUMBFRWSPkGrAf7r5fkDcJSFU=; b=LVpav7oYRIg1eeNu+DrlpGYVgCw1Z5UNZ4Q4v9pwJHV6TQzawaB0Id3oFJczzUvvLh LF6ebnGlCFyyRW1w8DRgWhYf1bFeNt1P2S8aFBT9m+LXtsG1WFUgVWYx2F5obq9D6jTe 5GnY4uojyGk4nwVmwiFYKtZCBJMUEZHNMQYFZYToD4sNkIo4HjZBLETZNjQuucsT+Uwj Dm6DIpP9HSKiVTN6HPqsKJzhJZ0bTP9p41HrMCLO0wYFndsJLC7JN2qjFciesvs0TsQY Y2AF5inVw/IhiYgp886en7xQWBZz/DUM0OI85MPhLYiPOIpd49fNa7huZ8cxVDzvW9Ww AuOg== X-Gm-Message-State: AOAM531ouCAgiQmwvZM0QyP1cI0TUlHt/FSInHlPvuOFcziFC/6pYrLZ 2KQxGRWUZVXcQ1MCSAm8Oj0= X-Google-Smtp-Source: ABdhPJzPkS27gmX56xEuowGDVfSEWgl/a+9IGyNX3O6Tbbi7v50inMH7Wv7pW1/0eaz7jNHGssBhoQ== X-Received: by 2002:a17:907:2d24:b0:6f4:3152:3d1a with SMTP id gs36-20020a1709072d2400b006f431523d1amr8241676ejc.324.1651955396080; Sat, 07 May 2022 13:29:56 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:55 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 04/11] clk: qcom: ipq8074: add PPE crypto clock Date: Sat, 7 May 2022 22:29:41 +0200 Message-Id: <20220507202948.397271-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko Reported-by: kernel test robot --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index f1017f2e61bd..c964e43ba68a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { From patchwork Sat May 7 20:29:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0AC8C433F5 for ; Sat, 7 May 2022 20:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387351AbiEGUdu (ORCPT ); Sat, 7 May 2022 16:33:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387356AbiEGUdr (ORCPT ); Sat, 7 May 2022 16:33:47 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 598FABC9E; Sat, 7 May 2022 13:29:59 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id gh6so20181465ejb.0; Sat, 07 May 2022 13:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gt1TfdpUx36mpk0knRdW8cvBlw/+WYrsEA+apVijl4c=; b=hs5SdNelpY5YDkiPDiq6fnNM63MQZoQgkjYz3yRTrxktYJk8RSa86tmA5dF6dOE4Rb Bwv/3FMjDPGb7cb5rv5hy/dVhEHpWYBINu422u4yYwgsqaAsHAxJmSXr7GjVW1rVZmGg 2boB7Cg6vcI8oyiai1gwOyUlsqm60Bce4SwDWOu5p3pezc8JIqbuer+BDWhS6APPKAz1 tX8QckdbO/Xqiwn+so20w3+sw7grn45Xs5scEUxt4Let6EEtuHPU5vKd6M3C1ocHVLAg 6Lg0j4KaJB6lbPZfEw4EuvvofoJz2PY9/SfbZhmHo9mJ2kaUsBFtS3oYkU9YwhKp5jG+ I9qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gt1TfdpUx36mpk0knRdW8cvBlw/+WYrsEA+apVijl4c=; b=D6MuniL6d/N5CJeuQKHhJP56RzmgUQ4CmfuDWVhocC9Xtg5QqHptMvfqmK9At9Gcw2 xqHG4IWTfLxdViv3v6ZN9/qyYbU0wXdbP3g5g3PAbgEl6YIFaL36E9wYjQl+8apWdjKw CnzJcuXOI9JDvWRf7ulyvC8Dx+hS23DO0biXYfsBUB31s3QUgijfc1hLPWp03FU/bmf9 MYdiVCdDARK1t30O8gXQ1MXkTGbHvr+vS8/haTYhEXUJFrC5RVsm8gzLW7+csKMax8La dG6+70V4JQJKpo9IzYc70CNG8bkZPkS/QAyhIONlhZl25fTC1MFqvgphVE4rIYCBCFwu 4rLQ== X-Gm-Message-State: AOAM532S3KZSUxPx8a0EZJf1WAIIvzbdOWNd0FQ+19qxLZV46le+vT1B uM9ndZRtbWNtYuJSyhjR2qA45uqYGLefKA== X-Google-Smtp-Source: ABdhPJyyg9+hKxzYmfIDwPamcivFWWy4BzIFJcilsEa2TplJyOinM/dU37wYfeYiJsKSKmwPYPDgZw== X-Received: by 2002:a17:906:9748:b0:6f4:d336:6b94 with SMTP id o8-20020a170906974800b006f4d3366b94mr8471075ejy.471.1651955397924; Sat, 07 May 2022 13:29:57 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:57 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v2 05/11] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock Date: Sat, 7 May 2022 22:29:42 +0200 Message-Id: <20220507202948.397271-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding for the PPE crypto clock in IPQ8074. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..5f0928785d7a 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 From patchwork Sat May 7 20:29:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 826A1C433F5 for ; Sat, 7 May 2022 20:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447063AbiEGUeF (ORCPT ); Sat, 7 May 2022 16:34:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1446940AbiEGUds (ORCPT ); Sat, 7 May 2022 16:33:48 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1BB017048; Sat, 7 May 2022 13:30:00 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id l18so20101395ejc.7; Sat, 07 May 2022 13:30:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZvwpsTuNNY2QM4J9Gfm3Onc86YrwY8xfFuqMd4xZS98=; b=Nd6HniGip2fEmspwZImYlPY0jXyufFZaxWOmTHax7KB0Lv7tMip837MZNUy5Qha52z ijmySf/kZwxYKrgbLwl6Hu5IDWsO9VqlKI6ccSd2siznSwXKRlJ6+qGUhGnh07HQmenx LAFh//BO6/JZir2BhoBkcf4nWDwwCNeqj7sObP9wi9zMHZJuY0LSY/hjGPb7nj8Q1ffs r02uTfv2RY5e0qkoyFGfdDjxuftaZwAyJZXga7Y06PDcSJh6GCHuBcWIjlZvmbaEjGba v0WB8J3IhQrWY7afCDf9FbvHN545SurzCMsyZdIoT7IQfgM0rWSDOXhc9Hx6lqx5tM1c cZWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZvwpsTuNNY2QM4J9Gfm3Onc86YrwY8xfFuqMd4xZS98=; b=6QuakEGtcY3PfUVHT1Ttf4Q5JU4JDT2BadNff9QTwTX8l/Xok61novZtqcw17lslFv mAtSA7L53laaC1rbihnX/auYGiMXcSQSkb2xgdgziQ2GJ3p16J/Dt3FGWnrNS/DvNrK4 CM0J+PBrgDNcfhqqY4E1uCPXrkZYfqNywEH5x2xJBcov+G3XmgGCxXmpGhd3u3sHNhcN pJSFE0qtgvWv/pkBjFtJrGLjbnnofUKVNPGthh6h4XnxbSNRv3PQDcPaTj4eoPKXvspU Er0CzmTbiUxJyH61pVwynxIS4uZWCFxoxB0JwWiFkxRKaB5DOnefTFxkDB2lCrJ2jlEa 6AAg== X-Gm-Message-State: AOAM532q12/TpTN41trm8462mSvedtYgjEchq5a0E9aSSJnpFY8nVsg3 G/11+xR5GNrC/xfxTPNoqMU= X-Google-Smtp-Source: ABdhPJwuL1uV0cmyuv1gxr3r5s91t5zVFDsOvRkDQfcw8KqKS5DCswu7qbKB0JNCa95JlBx1ScR1JQ== X-Received: by 2002:a17:906:314b:b0:6d6:da31:e545 with SMTP id e11-20020a170906314b00b006d6da31e545mr8778513eje.125.1651955399459; Sat, 07 May 2022 13:29:59 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:29:59 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 06/11] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Date: Sat, 7 May 2022 22:29:43 +0200 Message-Id: <20220507202948.397271-6-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index c964e43ba68a..85076c1383c7 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0), From patchwork Sat May 7 20:29:44 2022 Content-Type: text/plain; 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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:30:01 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 07/11] dt-bindings: clocks: qcom,gcc-ipq8074: support power domains Date: Sat, 7 May 2022 22:29:44 +0200 Message-Id: <20220507202948.397271-7-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by: Robert Marko --- .../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 98572b4a9b60..e3e236e4ce7d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -27,6 +27,9 @@ properties: '#reset-cells': const: 1 + '#power-domain-cells': + const: 1 + reg: maxItems: 1 @@ -39,6 +42,7 @@ required: - reg - '#clock-cells' - '#reset-cells' + - '#power-domain-cells' additionalProperties: false @@ -49,5 +53,6 @@ examples: reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; ... 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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:30:03 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 08/11] dt-bindings: clock: qcom: ipq8074: add USB GDSCs Date: Sat, 7 May 2022 22:29:45 +0200 Message-Id: <20220507202948.397271-8-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for the USB GDSCs found in IPQ8074 GCC. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 5f0928785d7a..e4991d303708 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -368,4 +368,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif From patchwork Sat May 7 20:29:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0A9FC4321E for ; Sat, 7 May 2022 20:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447079AbiEGUeI (ORCPT ); Sat, 7 May 2022 16:34:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1447025AbiEGUdx (ORCPT ); Sat, 7 May 2022 16:33:53 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8209E26AC9; Sat, 7 May 2022 13:30:05 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id l18so20101395ejc.7; Sat, 07 May 2022 13:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aekXutU6qQn7TvHCgvb/22PzNCDZUPryxE8p1lpIObE=; b=O312VQIjyYGWWkQQXEOOz2nSJU4st3VhuH2iaBWulF3jINfOKWb2iB5DTUyy8lhI+V qhRLsjtkwS+mqNAUmVDFt8Y8NlEph4DhcC8rRkByryODdxJoHIZri0IUlzVyxvE5pezW sFx3MBDGT3VWgXajWwq0nzZmxE/qdwTP2pLzjpofqPQGQdGp9hWxyLx1a9nOZLsbYhIn MotwiY8yUM+kG+6jPYvx10Yo48MlUeSGF7Rm+pFT+dkCzUi7Y8P/iDD6e6eRrMzK8IAm pZLrHOchoUUca+QXZD3mW+Wek1No+5s8jac3q6LwOiyg44IS8kRXjDsvaOD/kTD31ZVd NAnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aekXutU6qQn7TvHCgvb/22PzNCDZUPryxE8p1lpIObE=; b=WaUEeXpIVlxKJiG3Ufm8tBfoNhP3oUGPC2AvEmA5iW9y3OjW52KZ2j+EfTiySzC7/d XLuNSOqGgBwjgYoALknQBP3VfUd6S6QrK6Nn5olt8pqjjUbvNaNRTKNS+Fbpa4qySScK +KZSBfFZ+ATHXwtfvON4yohBHMUyaPrd+kdfzYDfcts4tF/u+ckYC/4OTZJ3PI7SRC4M gls6hXKSOijX8Yed+g59EouelYw4MRd3ibetU0YR7oxW9RbmhlRsjXyzRL8h8350hYtn L9G5dS+HDGtju18zUZTOm4wSb7Jy49P7RT/wMO0y3qUihP7Lny31AbAGfAyenStXDD3g TYlw== X-Gm-Message-State: AOAM5300hH9HSEZRkgsGRXhvyOker5maEiauB+bZBpBLUt5o7tpiCLX9 tRzFrcC4faUDDHiMVM/dmPY= X-Google-Smtp-Source: ABdhPJxn96hrjW3H8fK0t4I9UtYnFXfiaQynhBu02WS5/w5VtnP2jUBO600opUwpCdx/O/Ks8tx7OA== X-Received: by 2002:a17:906:8806:b0:6f5:15aa:1f40 with SMTP id zh6-20020a170906880600b006f515aa1f40mr8448428ejb.595.1651955404975; Sat, 07 May 2022 13:30:04 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:30:04 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 09/11] clk: qcom: ipq8074: add USB GDSCs Date: Sat, 7 May 2022 22:29:46 +0200 Message-Id: <20220507202948.397271-9-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add GDSC-s for each of the two USB controllers built-in the IPQ8074. Signed-off-by: Robert Marko --- Changes in v2: * Use proper GSDCs instead of raw regmap writes. --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d01436be6d7a..00fe5f066de5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -166,6 +166,7 @@ config IPQ_LCC_806X config IPQ_GCC_8074 tristate "IPQ8074 Global Clock Controller" + select QCOM_GDSC help Support for global clock controller on ipq8074 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 85076c1383c7..3204d550ff76 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -22,6 +22,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -4407,6 +4408,22 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static struct gdsc usb0_gdsc = { + .gdscr = 0x3e078, + .pd = { + .name = "usb0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb1_gdsc = { + .gdscr = 0x3f078, + .pd = { + .name = "usb1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static const struct alpha_pll_config ubi32_pll_config = { .l = 0x4e, .config_ctl_val = 0x200d4aa8, @@ -4810,6 +4827,11 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, }; +static struct gdsc *gcc_ipq8074_gdscs[] = { + [USB0_GDSC] = &usb0_gdsc, + [USB1_GDSC] = &usb1_gdsc, +}; + static const struct of_device_id gcc_ipq8074_match_table[] = { { .compatible = "qcom,gcc-ipq8074" }, { } @@ -4832,6 +4854,8 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), .clk_hws = gcc_ipq8074_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), + .gdscs = gcc_ipq8074_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), }; static int gcc_ipq8074_probe(struct platform_device *pdev) From patchwork Sat May 7 20:29:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4133AC41535 for ; Sat, 7 May 2022 20:30:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447088AbiEGUeK (ORCPT ); Sat, 7 May 2022 16:34:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1447043AbiEGUd4 (ORCPT ); Sat, 7 May 2022 16:33:56 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DDA625EB5; Sat, 7 May 2022 13:30:08 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id l18so20101802ejc.7; Sat, 07 May 2022 13:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y/MeqrmXCbj5O5cIo3EEbFqSYQK/Y93RuZd/E8X+Oe0=; b=KFtJ13nM0n8J9kmnORvAtXybu5snBc45N0KcVqaH+3XHIzAFjCBN68Ah5Di2sb1kz1 bSWqwextI+HpqqH0no45HVmExtfES6VgSLb0Mx6hGZmcE1w3peude+DCDaOqcneJ7HEs RpIctjllQPDuc8vZ3U5U7asrJjJ9PHWn05P6y4j4OUw7lrUVdHw+X+FazHk2oRzCWO/n KBvFqFBeQnBrC7Qp203xXc3EczTg37xMBgBhvcAiU83VNC7vnOM0eF7jE/rzfMGTS0og qQycgXiQNh1byqIze6k56VGe9oE7ZvsEdf/YxPr/gDdvMVdUg1ovVLTFN+MT9VYKHZpD JG2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y/MeqrmXCbj5O5cIo3EEbFqSYQK/Y93RuZd/E8X+Oe0=; b=eoXtjcR+7o9gzx00j2dyHTEmlPmOa2b59CRWr/W5ZUJG3MSJmupReUqa9664QJ9stj OimKzVwdcHFMcG7ICAhlg3Gr/iwx5vPYjcWWbfjAIm8GZ8LdZBGr8ZOe1hvi38Hl+XdS 4PC0/ixT/mCHZi42Rf+vc/FugnEtBQ5/Xfuk+9jNlpwZLFUgdjDAWLD4PP+CRZr2pRZt Nyy8FiB4QBz2gcwFrWYxm/NDE0g+M9BoFmpJp9Mt9PPtE/0kTZ2yqgh1LY/EFPOX8C/I kj3mOp8paRs3nAr0PHaX8ZHOkp5A5/BxxVjMsNYzNCibb2edvUDKWWvd9CJMuBI7UmAW 91wg== X-Gm-Message-State: AOAM531GMY0/S71OArteLuoZvRV+KyUPSN5tOUJEFFQj0XsmRFXZkwMg w8O5bbY5CAB9i7w19P5NjjE= X-Google-Smtp-Source: ABdhPJyJB2RvJcj0X1E8Paez4zQzb4nKvD9ffmkrCPudgEOZBe5EudZp3vBXt+kooHcdnqXVwKX+yA== X-Received: by 2002:a17:907:2cc7:b0:6df:b76d:940d with SMTP id hg7-20020a1709072cc700b006dfb76d940dmr8256800ejc.742.1651955406648; Sat, 07 May 2022 13:30:06 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:30:06 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 10/11] clk: qcom: ipq8074: dont disable gcc_sleep_clk_src Date: Sat, 7 May 2022 22:29:47 +0200 Message-Id: <20220507202948.397271-10-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Once the usb sleep clocks are disabled, clock framework is trying to disable the sleep clock source also. However, it seems that it cannot be disabled and trying to do so produces: [ 245.436390] ------------[ cut here ]------------ [ 245.441233] gcc_sleep_clk_src status stuck at 'on' [ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140 [ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio [ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215 [ 245.463889] Hardware name: Xiaomi AX9000 (DT) [ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 245.474307] pc : clk_branch_wait+0x130/0x140 [ 245.481073] lr : clk_branch_wait+0x130/0x140 [ 245.485588] sp : ffffffc009f2bad0 [ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000 [ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20 [ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0 [ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7 [ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777 [ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129 [ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001 [ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001 [ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027 [ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026 [ 245.557122] Call trace: [ 245.564229] clk_branch_wait+0x130/0x140 [ 245.566490] clk_branch2_disable+0x2c/0x40 [ 245.570656] clk_core_disable+0x60/0xb0 [ 245.574561] clk_core_disable+0x68/0xb0 [ 245.578293] clk_disable+0x30/0x50 [ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom] [ 245.585588] platform_remove+0x28/0x60 [ 245.590361] device_remove+0x4c/0x80 [ 245.594179] device_release_driver_internal+0x1dc/0x230 [ 245.597914] device_driver_detach+0x18/0x30 [ 245.602861] unbind_store+0xec/0x110 [ 245.607027] drv_attr_store+0x24/0x40 [ 245.610847] sysfs_kf_write+0x44/0x60 [ 245.614405] kernfs_fop_write_iter+0x128/0x1c0 [ 245.618052] new_sync_write+0xc0/0x130 [ 245.622391] vfs_write+0x1d4/0x2a0 [ 245.626123] ksys_write+0x58/0xe0 [ 245.629508] __arm64_sys_write+0x1c/0x30 [ 245.632895] invoke_syscall.constprop.0+0x5c/0x110 [ 245.636890] do_el0_svc+0xa0/0x150 [ 245.641488] el0_svc+0x18/0x60 [ 245.644872] el0t_64_sync_handler+0xa4/0x130 [ 245.647914] el0t_64_sync+0x174/0x178 [ 245.652340] ---[ end trace 0000000000000000 ]--- So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try to disable the sleep clock. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 3204d550ff76..42d185fe19c8 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -663,6 +663,7 @@ static struct clk_branch gcc_sleep_clk_src = { }, .num_parents = 1, .ops = &clk_branch2_ops, + .flags = CLK_IS_CRITICAL, }, }, }; From patchwork Sat May 7 20:29:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D3BC433EF for ; Sat, 7 May 2022 20:30:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447094AbiEGUeL (ORCPT ); Sat, 7 May 2022 16:34:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1447045AbiEGUd5 (ORCPT ); Sat, 7 May 2022 16:33:57 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E6EDE029; Sat, 7 May 2022 13:30:09 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id y3so20073641ejo.12; Sat, 07 May 2022 13:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YevJxKBdfoigsdif5cCA3smLmibiaBo4qQ4+jmjct3s=; b=YXdDPcLYZVdWb32UKU3srakoWr7WA9ntHQQvzmWKdrBe3iMhs9bERQHRgsbS14o26U WtEkB1OITwofjg1mIcI+Xpg1kSJEws+cgSQEiwPgnZv3QtmyWI99VV59VMEeWixnu6OL v7Q5EJwXkgwCG8asb2M6pSKMzlP43RLZdyMXU9l9dBbZm1MQH65ZZNSbPlzhvakPg3Qe AhB7rTPgHqDy851rEcit2iTvSyuGA1VZseZEKDdSNP3cZbEqXF9MPZrT2viLnkcCdNIh ToDghiYzKPE7EsqU7ZHYgleuCPpQfJb/w9dVe/8yp+5c6tR2B3k2w6KOXkvnbXFVGdfc 9J3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YevJxKBdfoigsdif5cCA3smLmibiaBo4qQ4+jmjct3s=; b=j0c3nYiUpPfGvZCDYCXuvR+RKMoir1Jr8maCsw3oe4K4vBy47zSJy9BFl8uBlEqjnl i55QuRk9uLT/jS7fSq3eYi+1U1SvoWfB+TbmoCjUtwvh6DY59COL/9djVSkQEn1AyySC BA18yYW+SzHsTImKhKJw4+b4ulrbrmieEHy7AtdrxFLjwHsA5qiD4tdr7pmYYswh8X9r ekt5GA+NmuKsCLPixwsEewQD0K2hnTgAd8vGc3ggdTh6o48lL9701/kkcw4vsuJp7PoM MLEaIX4LMCvTNPIMQZmSqz/te8c1hvSQ9AqtFKEfPw/4SwrL6s0DX/IZpu6pmDah9rtP /2dg== X-Gm-Message-State: AOAM532/uNcD8rlmjNi2fxWoWWfWeRdTgq/pcYc8Zuw2J39UlcQBCvN1 tJ7nKX3x99EKqdvhmYjeUgI= X-Google-Smtp-Source: ABdhPJwWEwvo7gjqTDNM3W9LQKAqdTg7wgHpFKC42vZNvYsaCpycjwzNmMQlKYZeThABz5GruG01lg== X-Received: by 2002:a17:906:6a1c:b0:6f4:b0e0:2827 with SMTP id qw28-20020a1709066a1c00b006f4b0e02827mr8011138ejc.249.1651955408140; Sat, 07 May 2022 13:30:08 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id k11-20020a056402048b00b0042617ba6383sm3900777edv.13.2022.05.07.13.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:30:07 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 11/11] arm64: dts: ipq8074: add USB power domains Date: Sat, 7 May 2022 22:29:48 +0200 Message-Id: <20220507202948.397271-11-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507202948.397271-1-robimarko@gmail.com> References: <20220507202948.397271-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add USB power domains provided by GCC GDSCs. Add the required #power-domain-cells to the GCC as well. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index ba81c510dd39..0bc21b0c177f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -383,6 +383,7 @@ gcc: gcc@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <0x1>; #reset-cells = <0x1>; + #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { @@ -610,6 +611,8 @@ usb_0: usb@8af8800 { <133330000>, <19200000>; + power-domains = <&gcc USB0_GDSC>; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -650,6 +653,8 @@ usb_1: usb@8cf8800 { <133330000>, <19200000>; + power-domains = <&gcc USB1_GDSC>; + resets = <&gcc GCC_USB1_BCR>; status = "disabled";