From patchwork Wed Aug 8 03:12:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559435 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B276514E5 for ; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A259D26255 for ; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 96212256E6; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F12D256E6 for ; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73C206E0EF; Wed, 8 Aug 2018 03:12:44 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C5E86E00A; Wed, 8 Aug 2018 03:12:43 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5AD4960B1A; Wed, 8 Aug 2018 03:12:43 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5836460AD8; Wed, 8 Aug 2018 03:12:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5836460AD8 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 01/13] drm/msm/dpu: remove scalar config definitions Date: Tue, 7 Aug 2018 20:12:28 -0700 Message-Id: <1533697956-29686-2-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP cleans up left out scalar config definitions from headers changes in v2: - none changes in v3: - none Change-Id: Id824dd5075c666f97b964573c97215bb786eac75 Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index e87109e..0e9aafa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -164,7 +164,6 @@ struct dpu_crtc_frame_event { * @cur_perf : current performance committed to clock/bandwidth driver * @rp_lock : serialization lock for resource pool * @rp_head : list of active resource pool - * @scl3_cfg_lut : qseed3 lut config */ struct dpu_crtc { struct drm_crtc base; @@ -175,7 +174,6 @@ struct dpu_crtc { u32 num_mixers; bool mixers_swapped; struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; - struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg; struct drm_pending_vblank_event *event; u32 vsync_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 1240f50..c5c8f60 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg { struct dpu_hw_scaler3_de_cfg de; }; -struct dpu_hw_scaler3_lut_cfg { - bool is_configured; - u32 *dir_lut; - size_t dir_len; - u32 *cir_lut; - size_t cir_len; - u32 *sep_lut; - size_t sep_len; -}; - /** * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure * @num_ext_pxls_lr: Number of total horizontal pixels From patchwork Wed Aug 8 03:12:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17DEF13BB for ; Wed, 8 Aug 2018 03:12:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 075B0256E6 for ; Wed, 8 Aug 2018 03:12:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F01282640A; Wed, 8 Aug 2018 03:12:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4CB46256E6 for ; Wed, 8 Aug 2018 03:12:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4AD46E4A5; Wed, 8 Aug 2018 03:12:48 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id A29AD6E13D; Wed, 8 Aug 2018 03:12:44 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7BD1060B83; Wed, 8 Aug 2018 03:12:44 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5A66960AD8; Wed, 8 Aug 2018 03:12:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5A66960AD8 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 02/13] drm/msm/dpu: remove resource pool manager Date: Tue, 7 Aug 2018 20:12:29 -0700 Message-Id: <1533697956-29686-3-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP resource pool manager utility was introduced to manage rotator sessions. Removing the support as the rotator feature doesn't exist. changes in v2: - none changes in v3: - rebase on [1] [1] https://gitlab.freedesktop.org/seanpaul/dpu-staging/commits/for-next Change-Id: Ib045f1c66269be650bce5896c459f59e1047a53f Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 ------------------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 56 --------- 2 files changed, 261 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 80cbf75..1f2d223 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -99,187 +99,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc, bool enable) return 0; } -/** - * _dpu_crtc_rp_to_crtc - get crtc from resource pool object - * @rp: Pointer to resource pool - * return: Pointer to drm crtc if success; null otherwise - */ -static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp) -{ - if (!rp) - return NULL; - - return container_of(rp, struct dpu_crtc_state, rp)->base.crtc; -} - -/** - * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool - * @rp: Pointer to resource pool - * @force: True to reclaim all resources; otherwise, reclaim only unused ones - * return: None - */ -static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force) -{ - struct dpu_crtc_res *res, *next; - struct drm_crtc *crtc; - - crtc = _dpu_crtc_rp_to_crtc(rp); - if (!crtc) { - DPU_ERROR("invalid crtc\n"); - return; - } - - DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id, - force ? "destroy" : "free_unused"); - - list_for_each_entry_safe(res, next, &rp->res_list, list) { - if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE)) - continue; - DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n", - crtc->base.id, rp->sequence_id, - res->type, res->tag, res->val, - atomic_read(&res->refcount)); - list_del(&res->list); - if (res->ops.put) - res->ops.put(res->val); - kfree(res); - } -} - -/** - * _dpu_crtc_rp_free_unused - free unused resource in pool - * @rp: Pointer to resource pool - * return: none - */ -static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp) -{ - mutex_lock(rp->rp_lock); - _dpu_crtc_rp_reclaim(rp, false); - mutex_unlock(rp->rp_lock); -} - -/** - * _dpu_crtc_rp_destroy - destroy resource pool - * @rp: Pointer to resource pool - * return: None - */ -static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp) -{ - mutex_lock(rp->rp_lock); - list_del_init(&rp->rp_list); - _dpu_crtc_rp_reclaim(rp, true); - mutex_unlock(rp->rp_lock); -} - -/** - * _dpu_crtc_hw_blk_get - get callback for hardware block - * @val: Resource handle - * @type: Resource type - * @tag: Search tag for given resource - * return: Resource handle - */ -static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag) -{ - DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val); - return dpu_hw_blk_get(val, type, tag); -} - -/** - * _dpu_crtc_hw_blk_put - put callback for hardware block - * @val: Resource handle - * return: None - */ -static void _dpu_crtc_hw_blk_put(void *val) -{ - DPU_DEBUG("res://%pK\n", val); - dpu_hw_blk_put(val); -} - -/** - * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count - * @rp: Pointer to original resource pool - * @dup_rp: Pointer to duplicated resource pool - * return: None - */ -static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp, - struct dpu_crtc_respool *dup_rp) -{ - struct dpu_crtc_res *res, *dup_res; - struct drm_crtc *crtc; - - if (!rp || !dup_rp || !rp->rp_head) { - DPU_ERROR("invalid resource pool\n"); - return; - } - - crtc = _dpu_crtc_rp_to_crtc(rp); - if (!crtc) { - DPU_ERROR("invalid crtc\n"); - return; - } - - DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id); - - mutex_lock(rp->rp_lock); - dup_rp->sequence_id = rp->sequence_id + 1; - INIT_LIST_HEAD(&dup_rp->res_list); - dup_rp->ops = rp->ops; - list_for_each_entry(res, &rp->res_list, list) { - dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL); - if (!dup_res) { - mutex_unlock(rp->rp_lock); - return; - } - INIT_LIST_HEAD(&dup_res->list); - atomic_set(&dup_res->refcount, 0); - dup_res->type = res->type; - dup_res->tag = res->tag; - dup_res->val = res->val; - dup_res->ops = res->ops; - dup_res->flags = DPU_CRTC_RES_FLAG_FREE; - DPU_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n", - crtc->base.id, dup_rp->sequence_id, - dup_res->type, dup_res->tag, dup_res->val, - atomic_read(&dup_res->refcount)); - list_add_tail(&dup_res->list, &dup_rp->res_list); - if (dup_res->ops.get) - dup_res->ops.get(dup_res->val, 0, -1); - } - - dup_rp->rp_lock = rp->rp_lock; - dup_rp->rp_head = rp->rp_head; - INIT_LIST_HEAD(&dup_rp->rp_list); - list_add_tail(&dup_rp->rp_list, rp->rp_head); - mutex_unlock(rp->rp_lock); -} - -/** - * _dpu_crtc_rp_reset - reset resource pool after allocation - * @rp: Pointer to original resource pool - * @rp_lock: Pointer to serialization resource pool lock - * @rp_head: Pointer to crtc resource pool head - * return: None - */ -static void _dpu_crtc_rp_reset(struct dpu_crtc_respool *rp, - struct mutex *rp_lock, struct list_head *rp_head) -{ - if (!rp || !rp_lock || !rp_head) { - DPU_ERROR("invalid resource pool\n"); - return; - } - - mutex_lock(rp_lock); - rp->rp_lock = rp_lock; - rp->rp_head = rp_head; - INIT_LIST_HEAD(&rp->rp_list); - rp->sequence_id = 0; - INIT_LIST_HEAD(&rp->res_list); - rp->ops.get = _dpu_crtc_hw_blk_get; - rp->ops.put = _dpu_crtc_hw_blk_put; - list_add_tail(&rp->rp_list, rp->rp_head); - mutex_unlock(rp_lock); -} - static void dpu_crtc_destroy(struct drm_crtc *crtc) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); @@ -951,8 +770,6 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc, DPU_DEBUG("crtc%d\n", crtc->base.id); - _dpu_crtc_rp_destroy(&cstate->rp); - __drm_atomic_helper_crtc_destroy_state(state); kfree(cstate); @@ -1206,8 +1023,6 @@ static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) /* duplicate base helper */ __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); - _dpu_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp); - return &cstate->base; } @@ -1244,9 +1059,6 @@ static void dpu_crtc_reset(struct drm_crtc *crtc) return; } - _dpu_crtc_rp_reset(&cstate->rp, &dpu_crtc->rp_lock, - &dpu_crtc->rp_head); - cstate->base.crtc = crtc; crtc->state = &cstate->base; } @@ -1679,7 +1491,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } end: - _dpu_crtc_rp_free_unused(&cstate->rp); kfree(pstates); return rc; } @@ -1955,8 +1766,6 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) { struct drm_crtc *crtc = (struct drm_crtc *) s->private; struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - struct dpu_crtc_res *res; - struct dpu_crtc_respool *rp; int i; seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); @@ -1973,17 +1782,6 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) dpu_crtc->cur_perf.max_per_pipe_ib[i]); } - mutex_lock(&dpu_crtc->rp_lock); - list_for_each_entry(rp, &dpu_crtc->rp_head, rp_list) { - seq_printf(s, "rp.%d: ", rp->sequence_id); - list_for_each_entry(res, &rp->res_list, list) - seq_printf(s, "0x%x/0x%llx/%pK/%d ", - res->type, res->tag, res->val, - atomic_read(&res->refcount)); - seq_puts(s, "\n"); - } - mutex_unlock(&dpu_crtc->rp_lock); - return 0; } DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); @@ -2104,9 +1902,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane) spin_lock_init(&dpu_crtc->spin_lock); atomic_set(&dpu_crtc->frame_pending, 0); - mutex_init(&dpu_crtc->rp_lock); - INIT_LIST_HEAD(&dpu_crtc->rp_head); - init_completion(&dpu_crtc->frame_done_comp); INIT_LIST_HEAD(&dpu_crtc->frame_event_list); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 0e9aafa..e84da78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -162,8 +162,6 @@ struct dpu_crtc_frame_event { * @phandle: Pointer to power handler * @power_event : registered power event handle * @cur_perf : current performance committed to clock/bandwidth driver - * @rp_lock : serialization lock for resource pool - * @rp_head : list of active resource pool */ struct dpu_crtc { struct drm_crtc base; @@ -213,65 +211,12 @@ struct dpu_crtc { struct dpu_core_perf_params cur_perf; - struct mutex rp_lock; - struct list_head rp_head; - struct dpu_crtc_smmu_state_data smmu_state; }; #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base) /** - * struct dpu_crtc_res_ops - common operations for crtc resources - * @get: get given resource - * @put: put given resource - */ -struct dpu_crtc_res_ops { - void *(*get)(void *val, u32 type, u64 tag); - void (*put)(void *val); -}; - -#define DPU_CRTC_RES_FLAG_FREE BIT(0) - -/** - * struct dpu_crtc_res - definition of crtc resources - * @list: list of crtc resource - * @type: crtc resource type - * @tag: unique identifier per type - * @refcount: reference/usage count - * @ops: callback operations - * @val: resource handle associated with type/tag - * @flags: customization flags - */ -struct dpu_crtc_res { - struct list_head list; - u32 type; - u64 tag; - atomic_t refcount; - struct dpu_crtc_res_ops ops; - void *val; - u32 flags; -}; - -/** - * dpu_crtc_respool - crtc resource pool - * @rp_lock: pointer to serialization lock - * @rp_head: pointer to head of active resource pools of this crtc - * @rp_list: list of crtc resource pool - * @sequence_id: sequence identifier, incremented per state duplication - * @res_list: list of resource managed by this resource pool - * @ops: resource operations for parent resource pool - */ -struct dpu_crtc_respool { - struct mutex *rp_lock; - struct list_head *rp_head; - struct list_head rp_list; - u32 sequence_id; - struct list_head res_list; - struct dpu_crtc_res_ops ops; -}; - -/** * struct dpu_crtc_state - dpu container for atomic crtc state * @base: Base drm crtc state structure * @is_ppsplit : Whether current topology requires PPSplit special handling @@ -296,7 +241,6 @@ struct dpu_crtc_state { uint64_t input_fence_timeout_ns; struct dpu_core_perf_params new_perf; - struct dpu_crtc_respool rp; }; #define to_dpu_crtc_state(x) \ From patchwork Wed Aug 8 03:12:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CF0A14E5 for ; Wed, 8 Aug 2018 03:12:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BA8A256E6 for ; Wed, 8 Aug 2018 03:12:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4F7472640A; Wed, 8 Aug 2018 03:12:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 07B51256E6 for ; Wed, 8 Aug 2018 03:12:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 718FE6E13D; Wed, 8 Aug 2018 03:12:47 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC2366E1EF; Wed, 8 Aug 2018 03:12:45 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C076960115; Wed, 8 Aug 2018 03:12:45 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 55C1660B7E; Wed, 8 Aug 2018 03:12:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 55C1660B7E From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 03/13] drm/msm/dpu: remove ping pong split topology variables Date: Tue, 7 Aug 2018 20:12:30 -0700 Message-Id: <1533697956-29686-4-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP removes left out variables of previous ping pong split topology cleanup. changes in v2: - none changes in v3: - none Change-Id: I1bf9d242039ce7cfd271233fa27840e83184fb95 Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index e84da78..e632651 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -219,7 +219,6 @@ struct dpu_crtc { /** * struct dpu_crtc_state - dpu container for atomic crtc state * @base: Base drm crtc state structure - * @is_ppsplit : Whether current topology requires PPSplit special handling * @bw_control : true if bw/clk controlled by core bw/clk properties * @bw_split_vote : true if bw controlled by llcc/dram bw properties * @lm_bounds : LM boundaries based on current mode full resolution, no ROI. @@ -234,8 +233,6 @@ struct dpu_crtc_state { bool bw_control; bool bw_split_vote; - - bool is_ppsplit; struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; uint64_t input_fence_timeout_ns; From patchwork Wed Aug 8 03:12:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E43713BB for ; Wed, 8 Aug 2018 03:13:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DE9D256E6 for ; Wed, 8 Aug 2018 03:13:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 427432640A; Wed, 8 Aug 2018 03:13:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E2BF3256E6 for ; Wed, 8 Aug 2018 03:13:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 88FFE6E4B0; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1C726E13D; Wed, 8 Aug 2018 03:12:46 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CAB0160BF5; Wed, 8 Aug 2018 03:12:46 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 59C8C60BE8; Wed, 8 Aug 2018 03:12:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 59C8C60BE8 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 04/13] drm/msm/dpu: program master-slave encoders explicitly Date: Tue, 7 Aug 2018 20:12:31 -0700 Message-Id: <1533697956-29686-5-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Identify slave-master encoders and program them explicitly. changes in v2: - none changes in v3: - none Change-Id: I0ebfada05bd7f8437f842ad860490a678aa8f4cd Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 ++++++++++++++++++----------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1b4de34..a0ced79 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -184,6 +184,7 @@ struct dpu_encoder_virt { unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; struct dpu_encoder_phys *cur_master; + struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; bool intfs_swapped; @@ -1153,6 +1154,7 @@ void dpu_encoder_virt_restore(struct drm_encoder *drm_enc) static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc = NULL; + struct dpu_encoder_phys *phys = NULL; int i, ret = 0; struct drm_display_mode *cur_mode = NULL; @@ -1160,6 +1162,7 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) DPU_ERROR("invalid encoder\n"); return; } + dpu_enc = to_dpu_encoder_virt(drm_enc); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; @@ -1167,21 +1170,36 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) cur_mode->vdisplay); dpu_enc->cur_master = NULL; + dpu_enc->cur_slave = NULL; for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + phys = dpu_enc->phys_encs[i]; + + if (!phys || !phys->ops.is_master) + continue; - if (phys && phys->ops.is_master && phys->ops.is_master(phys)) { - DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i); + if (phys->ops.is_master(phys)) { + DPU_DEBUG_ENC(dpu_enc, "master is at idx %d\n", i); dpu_enc->cur_master = phys; - break; + } else { + DPU_DEBUG_ENC(dpu_enc, "slave is at idx %d\n", i); + dpu_enc->cur_slave = phys; } } if (!dpu_enc->cur_master) { - DPU_ERROR("virt encoder has no master! num_phys %d\n", i); + DPU_ERROR("virt encoder has no master identified\n"); return; } + /* always enable slave encoder before master */ + phys = dpu_enc->cur_slave; + if (phys && phys->ops.enable) + phys->ops.enable(phys); + + phys = dpu_enc->cur_master; + if (phys && phys->ops.enable) + phys->ops.enable(phys); + ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); if (ret) { DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", @@ -1190,25 +1208,16 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) } for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - + phys = dpu_enc->phys_encs[i]; if (!phys) continue; - if (phys != dpu_enc->cur_master) { - if (phys->ops.enable) - phys->ops.enable(phys); - } - if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities & MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr) phys->ops.setup_misr(phys, true, dpu_enc->misr_frame_count); } - if (dpu_enc->cur_master->ops.enable) - dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); - _dpu_encoder_virt_enable_helper(drm_enc); } From patchwork Wed Aug 8 03:12:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6872A174A for ; Wed, 8 Aug 2018 03:12:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57706256E6 for ; Wed, 8 Aug 2018 03:12:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4BC5F2640A; Wed, 8 Aug 2018 03:12:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 02465256E6 for ; Wed, 8 Aug 2018 03:12:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A2AB6E4AE; Wed, 8 Aug 2018 03:12:50 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD5BF6E4A0; Wed, 8 Aug 2018 03:12:47 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A01F360BDE; Wed, 8 Aug 2018 03:12:47 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 52F1960B7A; Wed, 8 Aug 2018 03:12:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 52F1960B7A From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 05/13] drm/msm/dpu: use kms stored hw mdp block Date: Tue, 7 Aug 2018 20:12:32 -0700 Message-Id: <1533697956-29686-6-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Avoid querying RM for hw mdp block. Use the one stored in KMS during initialization. changes in v2: - none changes in v3: - none Change-Id: I52129b96bd561a5547507d7f567bcaa3dbe554aa Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 +----------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +-------- 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 3084675..c8c4612 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -823,7 +823,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( { struct dpu_encoder_phys *phys_enc = NULL; struct dpu_encoder_phys_cmd *cmd_enc = NULL; - struct dpu_hw_mdp *hw_mdp; struct dpu_encoder_irq *irq; int i, ret = 0; @@ -836,14 +835,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( goto fail; } phys_enc = &cmd_enc->base; - - hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm); - if (IS_ERR_OR_NULL(hw_mdp)) { - ret = PTR_ERR(hw_mdp); - DPU_ERROR("failed to get mdptop\n"); - goto fail_mdp_init; - } - phys_enc->hw_mdptop = hw_mdp; + phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; phys_enc->intf_idx = p->intf_idx; dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); @@ -898,8 +890,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( return phys_enc; -fail_mdp_init: - kfree(cmd_enc); fail: return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 14fc7c2..57ece03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -829,7 +829,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( struct dpu_encoder_phys *phys_enc = NULL; struct dpu_encoder_phys_vid *vid_enc = NULL; struct dpu_rm_hw_iter iter; - struct dpu_hw_mdp *hw_mdp; struct dpu_encoder_irq *irq; int i, ret = 0; @@ -846,13 +845,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( phys_enc = &vid_enc->base; - hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm); - if (IS_ERR_OR_NULL(hw_mdp)) { - ret = PTR_ERR(hw_mdp); - DPU_ERROR("failed to get mdptop\n"); - goto fail; - } - phys_enc->hw_mdptop = hw_mdp; + phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; phys_enc->intf_idx = p->intf_idx; /** From patchwork Wed Aug 8 03:12:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559453 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0927D13BB for ; Wed, 8 Aug 2018 03:13:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EAEA0256E6 for ; Wed, 8 Aug 2018 03:13:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD5732640A; Wed, 8 Aug 2018 03:13:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 748A2256E6 for ; Wed, 8 Aug 2018 03:13:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 771966E4B4; Wed, 8 Aug 2018 03:12:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C24B6E4AD; Wed, 8 Aug 2018 03:12:50 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 066FA60C61; Wed, 8 Aug 2018 03:12:48 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 571C160C4E; Wed, 8 Aug 2018 03:12:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 571C160C4E From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 06/13] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder Date: Tue, 7 Aug 2018 20:12:33 -0700 Message-Id: <1533697956-29686-7-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of iterating for hw ctrl per physical encoder, this patch moves the iterations and assignment to the virtual encoder. changes in v2: - none changes in v3: - none Change-Id: I896a8c36d6353986582e9d0fe3da9b2293579d4b Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 22 ++++++++++++++++++++-- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 19 ------------------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 19 ------------------- 3 files changed, 20 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index a0ced79..7b82e2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1017,9 +1017,11 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_kms *dpu_kms; struct list_head *connector_list; struct drm_connector *conn = NULL, *conn_iter; - struct dpu_rm_hw_iter pp_iter; + struct dpu_rm_hw_iter pp_iter, ctl_iter; struct msm_display_topology topology; enum dpu_rm_topology_name topology_name; + struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC]; + int i = 0, ret; if (!drm_enc) { @@ -1067,6 +1069,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw; } + dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL); + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { + hw_ctl[i] = NULL; + if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter)) + break; + hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw; + } + topology_name = dpu_rm_get_topology_name(topology); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; @@ -1074,10 +1084,18 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, if (phys) { if (!dpu_enc->hw_pp[i]) { DPU_ERROR_ENC(dpu_enc, - "invalid pingpong block for the encoder\n"); + "no pp block assigned at idx: %d\n", i); return; } phys->hw_pp = dpu_enc->hw_pp[i]; + + if (!hw_ctl[i]) { + DPU_ERROR_ENC(dpu_enc, + "no ctl block assigned at idx: %d\n", i); + return; + } + phys->hw_ctl = hw_ctl[i]; + phys->connector = conn->state->connector; phys->topology_name = topology_name; if (phys->ops.mode_set) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index c8c4612..5c89868 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -196,9 +196,6 @@ static void dpu_encoder_phys_cmd_mode_set( { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - struct dpu_rm *rm = &phys_enc->dpu_kms->rm; - struct dpu_rm_hw_iter iter; - int i, instance; if (!phys_enc || !mode || !adj_mode) { DPU_ERROR("invalid args\n"); @@ -208,22 +205,6 @@ static void dpu_encoder_phys_cmd_mode_set( DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n"); drm_mode_debug_printmodeline(adj_mode); - instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0; - - /* Retrieve previously allocated HW Resources. Shouldn't fail */ - dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL); - for (i = 0; i <= instance; i++) { - if (dpu_rm_get_hw(rm, &iter)) - phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw; - } - - if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { - DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n", - PTR_ERR(phys_enc->hw_ctl)); - phys_enc->hw_ctl = NULL; - return; - } - _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 57ece03..c0221cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -395,9 +395,6 @@ static void dpu_encoder_phys_vid_mode_set( struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { - struct dpu_rm *rm; - struct dpu_rm_hw_iter iter; - int i, instance; struct dpu_encoder_phys_vid *vid_enc; if (!phys_enc || !phys_enc->dpu_kms) { @@ -405,7 +402,6 @@ static void dpu_encoder_phys_vid_mode_set( return; } - rm = &phys_enc->dpu_kms->rm; vid_enc = to_dpu_encoder_phys_vid(phys_enc); if (adj_mode) { @@ -414,21 +410,6 @@ static void dpu_encoder_phys_vid_mode_set( DPU_DEBUG_VIDENC(vid_enc, "caching mode:\n"); } - instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0; - - /* Retrieve previously allocated HW Resources. Shouldn't fail */ - dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL); - for (i = 0; i <= instance; i++) { - if (dpu_rm_get_hw(rm, &iter)) - phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw; - } - if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { - DPU_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n", - PTR_ERR(phys_enc->hw_ctl)); - phys_enc->hw_ctl = NULL; - return; - } - _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc); } From patchwork Wed Aug 8 03:12:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C24214E5 for ; Wed, 8 Aug 2018 03:13:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 192AF2A308 for ; Wed, 8 Aug 2018 03:13:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0B7C42A30E; Wed, 8 Aug 2018 03:13:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A35B02A308 for ; Wed, 8 Aug 2018 03:13:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 629926E4B9; Wed, 8 Aug 2018 03:12:58 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8A9A6E4B4; Wed, 8 Aug 2018 03:12:52 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5443160C8B; Wed, 8 Aug 2018 03:12:49 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 618E460C4B; Wed, 8 Aug 2018 03:12:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 618E460C4B From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 07/13] drm/msm/dpu: avoid querying for hw intf before assignment Date: Tue, 7 Aug 2018 20:12:34 -0700 Message-Id: <1533697956-29686-8-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP hw intf blocks are needed only during encoder enable to program timing engines(for video panels). encoder->enable is triggered only after atomic_modeset at which point we assign the resources for the display pipeline. This patch defers the hw_intf look-up until encoder enable. changes in v2: - none changes in v3: - none Change-Id: Ib0a2253431468151355e50cbad7b91e2b77b6e54 Signed-off-by: Jeykumar Sankaran --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 53 +++++++--------------- 1 file changed, 16 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index c0221cc..a0b3744 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -462,7 +462,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) { struct msm_drm_private *priv; struct dpu_encoder_phys_vid *vid_enc; - struct dpu_hw_intf *intf; + struct dpu_rm_hw_iter iter; struct dpu_hw_ctl *ctl; u32 flush_mask = 0; @@ -474,11 +474,20 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) priv = phys_enc->parent->dev->dev_private; vid_enc = to_dpu_encoder_phys_vid(phys_enc); - intf = vid_enc->hw_intf; ctl = phys_enc->hw_ctl; - if (!vid_enc->hw_intf || !phys_enc->hw_ctl) { - DPU_ERROR("invalid hw_intf %d hw_ctl %d\n", - vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0); + + dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF); + while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) { + struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw; + + if (hw_intf->idx == phys_enc->intf_idx) { + vid_enc->hw_intf = hw_intf; + break; + } + } + + if (!vid_enc->hw_intf) { + DPU_ERROR("hw_intf not assigned\n"); return; } @@ -500,7 +509,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) !dpu_encoder_phys_vid_is_master(phys_enc)) goto skip_flush; - ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx); + ctl->ops.get_bitmask_intf(ctl, &flush_mask, vid_enc->hw_intf->idx); ctl->ops.update_pending_flush(ctl, flush_mask); skip_flush: @@ -531,22 +540,13 @@ static void dpu_encoder_phys_vid_get_hw_resources( struct dpu_encoder_hw_resources *hw_res, struct drm_connector_state *conn_state) { - struct dpu_encoder_phys_vid *vid_enc; - if (!phys_enc || !hw_res) { DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n", phys_enc != 0, hw_res != 0, conn_state != 0); return; } - vid_enc = to_dpu_encoder_phys_vid(phys_enc); - if (!vid_enc->hw_intf) { - DPU_ERROR("invalid arg(s), hw_intf\n"); - return; - } - - DPU_DEBUG_VIDENC(vid_enc, "\n"); - hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO; + hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; } static int _dpu_encoder_phys_vid_wait_for_vblank( @@ -809,7 +809,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( { struct dpu_encoder_phys *phys_enc = NULL; struct dpu_encoder_phys_vid *vid_enc = NULL; - struct dpu_rm_hw_iter iter; struct dpu_encoder_irq *irq; int i, ret = 0; @@ -829,26 +828,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; phys_enc->intf_idx = p->intf_idx; - /** - * hw_intf resource permanently assigned to this encoder - * Other resources allocated at atomic commit time by use case - */ - dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_INTF); - while (dpu_rm_get_hw(&p->dpu_kms->rm, &iter)) { - struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw; - - if (hw_intf->idx == p->intf_idx) { - vid_enc->hw_intf = hw_intf; - break; - } - } - - if (!vid_enc->hw_intf) { - ret = -EINVAL; - DPU_ERROR("failed to get hw_intf\n"); - goto fail; - } - DPU_DEBUG_VIDENC(vid_enc, "\n"); dpu_encoder_phys_vid_init_ops(&phys_enc->ops); From patchwork Wed Aug 8 03:12:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E81413BB for ; Wed, 8 Aug 2018 03:13:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89421256E6 for ; Wed, 8 Aug 2018 03:13:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7D77F2640A; Wed, 8 Aug 2018 03:13:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BBE0D256E6 for ; Wed, 8 Aug 2018 03:13:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C216D6E4B7; Wed, 8 Aug 2018 03:12:57 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id E35526E4B7; Wed, 8 Aug 2018 03:12:56 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7934960B23; Wed, 8 Aug 2018 03:12:51 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6030B60B22; Wed, 8 Aug 2018 03:12:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6030B60B22 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 08/13] drm/msm/dpu: move hw resource tracking to crtc state Date: Tue, 7 Aug 2018 20:12:35 -0700 Message-Id: <1533697956-29686-9-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Prep changes for state based resource management. Moves all the hw block tracking for the crtc to the state object. changes in v2: - none changes in v3: - none Change-Id: I2816e9e28b27f1126b477d62eb3858a30a652747 Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 77 +++++++++++++++++--------------- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 25 +++++------ 2 files changed, 54 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1f2d223..515b0e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -136,9 +136,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) crtc_state = to_dpu_crtc_state(crtc->state); lm_horiz_position = 0; - for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) { + for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; - struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm; + struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; struct dpu_hw_mixer_cfg cfg; if (!lm_roi || !drm_rect_visible(lm_roi)) @@ -219,7 +219,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, fb ? fb->modifier : 0); /* blend config update */ - for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) { + for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate); mixer[lm_idx].flush_mask |= flush_mask; @@ -242,7 +242,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) { struct dpu_crtc *dpu_crtc; - struct dpu_crtc_state *dpu_crtc_state; + struct dpu_crtc_state *cstate; struct dpu_crtc_mixer *mixer; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; @@ -253,17 +253,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) return; dpu_crtc = to_dpu_crtc(crtc); - dpu_crtc_state = to_dpu_crtc_state(crtc->state); - mixer = dpu_crtc->mixers; + cstate = to_dpu_crtc_state(crtc->state); + mixer = cstate->mixers; DPU_DEBUG("%s\n", dpu_crtc->name); - if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) { - DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers); + if (cstate->num_mixers > CRTC_DUAL_MIXERS) { + DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers); return; } - for (i = 0; i < dpu_crtc->num_mixers; i++) { + for (i = 0; i < cstate->num_mixers; i++) { if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { DPU_ERROR("invalid lm or ctl assigned to mixer\n"); return; @@ -280,7 +280,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); - for (i = 0; i < dpu_crtc->num_mixers; i++) { + for (i = 0; i < cstate->num_mixers; i++) { ctl = mixer[i].hw_ctl; lm = mixer[i].hw_lm; @@ -502,7 +502,7 @@ static void _dpu_crtc_setup_mixer_for_encoder( struct drm_crtc *crtc, struct drm_encoder *enc) { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); + struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); struct dpu_rm *rm = &dpu_kms->rm; struct dpu_crtc_mixer *mixer; @@ -514,8 +514,8 @@ static void _dpu_crtc_setup_mixer_for_encoder( dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL); /* Set up all the mixers and ctls reserved by this encoder */ - for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) { - mixer = &dpu_crtc->mixers[i]; + for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) { + mixer = &cstate->mixers[i]; if (!dpu_rm_get_hw(rm, &lm_iter)) break; @@ -540,7 +540,7 @@ static void _dpu_crtc_setup_mixer_for_encoder( mixer->encoder = enc; - dpu_crtc->num_mixers++; + cstate->num_mixers++; DPU_DEBUG("setup mixer %d: lm %d\n", i, mixer->hw_lm->idx - LM_0); DPU_DEBUG("setup mixer %d: ctl %d\n", @@ -551,11 +551,11 @@ static void _dpu_crtc_setup_mixer_for_encoder( static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); + struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); struct drm_encoder *enc; - dpu_crtc->num_mixers = 0; - dpu_crtc->mixers_swapped = false; - memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers)); + cstate->num_mixers = 0; + memset(cstate->mixers, 0, sizeof(cstate->mixers)); mutex_lock(&dpu_crtc->crtc_lock); /* Check for mixers on all encoders attached to this crtc */ @@ -589,7 +589,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, adj_mode = &state->adjusted_mode; crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode); - for (i = 0; i < dpu_crtc->num_mixers; i++) { + for (i = 0; i < cstate->num_mixers; i++) { struct drm_rect *r = &cstate->lm_bounds[i]; r->x1 = crtc_split_width * i; r->y1 = 0; @@ -606,6 +606,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { struct dpu_crtc *dpu_crtc; + struct dpu_crtc_state *cstate; struct drm_encoder *encoder; struct drm_device *dev; unsigned long flags; @@ -625,10 +626,11 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, DPU_DEBUG("crtc%d\n", crtc->base.id); dpu_crtc = to_dpu_crtc(crtc); + cstate = to_dpu_crtc_state(crtc->state); dev = crtc->dev; smmu_state = &dpu_crtc->smmu_state; - if (!dpu_crtc->num_mixers) { + if (!cstate->num_mixers) { _dpu_crtc_setup_mixers(crtc); _dpu_crtc_setup_lm_bounds(crtc, crtc->state); } @@ -655,7 +657,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, * it means we are trying to flush a CRTC whose state is disabled: * nothing else needs to be done. */ - if (unlikely(!dpu_crtc->num_mixers)) + if (unlikely(!cstate->num_mixers)) return; _dpu_crtc_blend_setup(crtc); @@ -719,7 +721,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, * it means we are trying to flush a CRTC whose state is disabled: * nothing else needs to be done. */ - if (unlikely(!dpu_crtc->num_mixers)) + if (unlikely(!cstate->num_mixers)) return; /* @@ -834,7 +836,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) * it means we are trying to start a CRTC whose state is disabled: * nothing else needs to be done. */ - if (unlikely(!dpu_crtc->num_mixers)) + if (unlikely(!cstate->num_mixers)) return; DPU_ATRACE_BEGIN("crtc_commit"); @@ -1069,6 +1071,7 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) struct dpu_crtc *dpu_crtc; struct drm_encoder *encoder; struct dpu_crtc_mixer *m; + struct dpu_crtc_state *cstate; u32 i, misr_status; if (!crtc) { @@ -1076,6 +1079,7 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) return; } dpu_crtc = to_dpu_crtc(crtc); + cstate = to_dpu_crtc_state(dpu_crtc->base.state); mutex_lock(&dpu_crtc->crtc_lock); @@ -1091,8 +1095,8 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) dpu_encoder_virt_restore(encoder); } - for (i = 0; i < dpu_crtc->num_mixers; ++i) { - m = &dpu_crtc->mixers[i]; + for (i = 0; i < cstate->num_mixers; ++i) { + m = &cstate->mixers[i]; if (!m->hw_lm || !m->hw_lm->ops.setup_misr || !dpu_crtc->misr_enable) continue; @@ -1102,8 +1106,8 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) } break; case DPU_POWER_EVENT_PRE_DISABLE: - for (i = 0; i < dpu_crtc->num_mixers; ++i) { - m = &dpu_crtc->mixers[i]; + for (i = 0; i < cstate->num_mixers; ++i) { + m = &cstate->mixers[i]; if (!m->hw_lm || !m->hw_lm->ops.collect_misr || !dpu_crtc->misr_enable) continue; @@ -1191,9 +1195,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) dpu_power_handle_unregister_event(dpu_crtc->phandle, dpu_crtc->power_event); - memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers)); - dpu_crtc->num_mixers = 0; - dpu_crtc->mixers_swapped = false; + memset(cstate->mixers, 0, sizeof(cstate->mixers)); + cstate->num_mixers = 0; /* disable clk & bw control until clk & bw properties are set */ cstate->bw_control = false; @@ -1552,8 +1555,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_puts(s, "\n"); - for (i = 0; i < dpu_crtc->num_mixers; ++i) { - m = &dpu_crtc->mixers[i]; + for (i = 0; i < cstate->num_mixers; ++i) { + m = &cstate->mixers[i]; if (!m->hw_lm) seq_printf(s, "\tmixer[%d] has no lm\n", i); else if (!m->hw_ctl) @@ -1646,6 +1649,7 @@ static ssize_t _dpu_crtc_misr_setup(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { struct dpu_crtc *dpu_crtc; + struct dpu_crtc_state *cstate; struct dpu_crtc_mixer *m; int i = 0, rc; char buf[MISR_BUFF_SIZE + 1]; @@ -1656,6 +1660,7 @@ static ssize_t _dpu_crtc_misr_setup(struct file *file, return -EINVAL; dpu_crtc = file->private_data; + cstate = to_dpu_crtc_state(dpu_crtc->base.state); buff_copy = min_t(size_t, count, MISR_BUFF_SIZE); if (copy_from_user(buf, user_buf, buff_copy)) { DPU_ERROR("buffer copy failed\n"); @@ -1674,9 +1679,9 @@ static ssize_t _dpu_crtc_misr_setup(struct file *file, mutex_lock(&dpu_crtc->crtc_lock); dpu_crtc->misr_enable = enable; dpu_crtc->misr_frame_count = frame_count; - for (i = 0; i < dpu_crtc->num_mixers; ++i) { + for (i = 0; i < cstate->num_mixers; ++i) { dpu_crtc->misr_data[i] = 0; - m = &dpu_crtc->mixers[i]; + m = &cstate->mixers[i]; if (!m->hw_lm || !m->hw_lm->ops.setup_misr) continue; @@ -1692,6 +1697,7 @@ static ssize_t _dpu_crtc_misr_read(struct file *file, char __user *user_buff, size_t count, loff_t *ppos) { struct dpu_crtc *dpu_crtc; + struct dpu_crtc_state *cstate; struct dpu_crtc_mixer *m; int i = 0, rc; u32 misr_status; @@ -1705,6 +1711,7 @@ static ssize_t _dpu_crtc_misr_read(struct file *file, return -EINVAL; dpu_crtc = file->private_data; + cstate = to_dpu_crtc_state(dpu_crtc->base.state); rc = _dpu_crtc_power_enable(dpu_crtc, true); if (rc) return rc; @@ -1716,8 +1723,8 @@ static ssize_t _dpu_crtc_misr_read(struct file *file, goto buff_check; } - for (i = 0; i < dpu_crtc->num_mixers; ++i) { - m = &dpu_crtc->mixers[i]; + for (i = 0; i < cstate->num_mixers; ++i) { + m = &cstate->mixers[i]; if (!m->hw_lm || !m->hw_lm->ops.collect_misr) continue; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index e632651..9177ee6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -121,11 +121,6 @@ struct dpu_crtc_frame_event { * struct dpu_crtc - virtualized CRTC data structure * @base : Base drm crtc structure * @name : ASCII description of this crtc - * @num_ctls : Number of ctl paths in use - * @num_mixers : Number of mixers in use - * @mixers_swapped: Whether the mixers have been swapped for left/right update - * especially in the case of DSC Merge. - * @mixers : List of active mixers * @event : Pointer to last received drm vblank event. If there is a * pending vblank event, this will be non-null. * @vsync_count : Running count of received vsync events @@ -167,12 +162,6 @@ struct dpu_crtc { struct drm_crtc base; char name[DPU_CRTC_NAME_SIZE]; - /* HW Resources reserved for the crtc */ - u32 num_ctls; - u32 num_mixers; - bool mixers_swapped; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; - struct drm_pending_vblank_event *event; u32 vsync_count; @@ -227,6 +216,10 @@ struct dpu_crtc { * @property_values: Current crtc property values * @input_fence_timeout_ns : Cached input fence timeout, in ns * @new_perf: new performance state being requested + * @num_mixers : Number of mixers in use + * @mixers : List of active mixers + * @num_ctls : Number of ctl paths in use + * @hw_ctls : List of activel ctl paths */ struct dpu_crtc_state { struct drm_crtc_state base; @@ -236,8 +229,14 @@ struct dpu_crtc_state { struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; uint64_t input_fence_timeout_ns; - struct dpu_core_perf_params new_perf; + + /* HW Resources reserved for the crtc */ + u32 num_mixers; + struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + + u32 num_ctls; + struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; }; #define to_dpu_crtc_state(x) \ @@ -255,7 +254,7 @@ static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc, if (!dpu_crtc || !cstate || !mode) return 0; - mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ? + mixer_width = (cstate->num_mixers == CRTC_DUAL_MIXERS ? mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay); return mixer_width; From patchwork Wed Aug 8 03:12:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CA4E13BB for ; Wed, 8 Aug 2018 03:13:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B9352A30A for ; Wed, 8 Aug 2018 03:13:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FEB92A310; Wed, 8 Aug 2018 03:13:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A70362A30A for ; Wed, 8 Aug 2018 03:13:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D4DF7891C3; Wed, 8 Aug 2018 03:13:09 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E330891A1; Wed, 8 Aug 2018 03:13:08 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AA54060BE8; Wed, 8 Aug 2018 03:12:52 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7CDDF60C7F; Wed, 8 Aug 2018 03:12:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7CDDF60C7F From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 09/13] drm/msm/dpu: rename hw_ctl to lm_ctl Date: Tue, 7 Aug 2018 20:12:36 -0700 Message-Id: <1533697956-29686-10-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> References: <1533697956-29686-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Prep change for state based resource management. Rename hw_ctl to lm_ctl to mean the ctl associated with the hw layer mixer block. changes in v2: - none changes in v3: - none Change-Id: If6e6249e089b89225cdfafe9158f66667509e97b Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +++++++++++++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 ++-- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 515b0e6..0eb369c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -175,7 +175,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, return; } - ctl = mixer->hw_ctl; + ctl = mixer->lm_ctl; lm = mixer->hw_lm; stage_cfg = &dpu_crtc->stage_cfg; cstate = to_dpu_crtc_state(crtc->state); @@ -264,15 +264,15 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } for (i = 0; i < cstate->num_mixers; i++) { - if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { + if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { DPU_ERROR("invalid lm or ctl assigned to mixer\n"); return; } mixer[i].mixer_op_mode = 0; mixer[i].flush_mask = 0; - if (mixer[i].hw_ctl->ops.clear_all_blendstages) - mixer[i].hw_ctl->ops.clear_all_blendstages( - mixer[i].hw_ctl); + if (mixer[i].lm_ctl->ops.clear_all_blendstages) + mixer[i].lm_ctl->ops.clear_all_blendstages( + mixer[i].lm_ctl); } /* initialize stage cfg */ @@ -281,7 +281,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); for (i = 0; i < cstate->num_mixers; i++) { - ctl = mixer[i].hw_ctl; + ctl = mixer[i].lm_ctl; lm = mixer[i].hw_lm; lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); @@ -525,14 +525,14 @@ static void _dpu_crtc_setup_mixer_for_encoder( if (!dpu_rm_get_hw(rm, &ctl_iter)) { DPU_DEBUG("no ctl assigned to lm %d, using previous\n", mixer->hw_lm->idx - LM_0); - mixer->hw_ctl = last_valid_ctl; + mixer->lm_ctl = last_valid_ctl; } else { - mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; - last_valid_ctl = mixer->hw_ctl; + mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; + last_valid_ctl = mixer->lm_ctl; } /* Shouldn't happen, mixers are always >= ctls */ - if (!mixer->hw_ctl) { + if (!mixer->lm_ctl) { DPU_ERROR("no valid ctls found for lm %d\n", mixer->hw_lm->idx - LM_0); return; @@ -544,7 +544,7 @@ static void _dpu_crtc_setup_mixer_for_encoder( DPU_DEBUG("setup mixer %d: lm %d\n", i, mixer->hw_lm->idx - LM_0); DPU_DEBUG("setup mixer %d: ctl %d\n", - i, mixer->hw_ctl->idx - CTL_0); + i, mixer->lm_ctl->idx - CTL_0); } } @@ -1559,11 +1559,11 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) m = &cstate->mixers[i]; if (!m->hw_lm) seq_printf(s, "\tmixer[%d] has no lm\n", i); - else if (!m->hw_ctl) + else if (!m->lm_ctl) seq_printf(s, "\tmixer[%d] has no ctl\n", i); else seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", - m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0, + m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, out_width, mode->vdisplay); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 9177ee6..5b85ca8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -83,14 +83,14 @@ struct dpu_crtc_smmu_state_data { /** * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC * @hw_lm: LM HW Driver context - * @hw_ctl: CTL Path HW driver context + * @lm_ctl: CTL Path HW driver context * @encoder: Encoder attached to this lm & ctl * @mixer_op_mode: mixer blending operation mode * @flush_mask: mixer flush mask for ctl, mixer and pipe */ struct dpu_crtc_mixer { struct dpu_hw_mixer *hw_lm; - struct dpu_hw_ctl *hw_ctl; + struct dpu_hw_ctl *lm_ctl; struct drm_encoder *encoder; u32 mixer_op_mode; u32 flush_mask; From patchwork Wed Aug 8 03:20:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559467 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89984174A for ; Wed, 8 Aug 2018 03:20:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 78D5F29359 for ; Wed, 8 Aug 2018 03:20:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D0EC2A412; Wed, 8 Aug 2018 03:20:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F10612A3F1 for ; Wed, 8 Aug 2018 03:20:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 254EB6E0A6; Wed, 8 Aug 2018 03:20:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id E91F76E03C; Wed, 8 Aug 2018 03:20:30 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D012960B73; Wed, 8 Aug 2018 03:20:30 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6E1D4606FC; Wed, 8 Aug 2018 03:20:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6E1D4606FC From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 10/13] drm/msm/dpu: remove topology name Date: Tue, 7 Aug 2018 20:20:08 -0700 Message-Id: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Strip down the support for topology enums. It can be replaced with simple hw count checks. changes in v2: - none changes in v3: - none Change-Id: If9b2a4db5bbdf8545b99b6d90825e256d014382d Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 ++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12 ------------ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 9 --------- 5 files changed, 10 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 7b82e2d..58647ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1019,7 +1019,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct drm_connector *conn = NULL, *conn_iter; struct dpu_rm_hw_iter pp_iter, ctl_iter; struct msm_display_topology topology; - enum dpu_rm_topology_name topology_name; struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC]; int i = 0, ret; @@ -1077,7 +1076,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw; } - topology_name = dpu_rm_get_topology_name(topology); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; @@ -1097,7 +1095,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, phys->hw_ctl = hw_ctl[i]; phys->connector = conn->state->connector; - phys->topology_name = topology_name; if (phys->ops.mode_set) phys->ops.mode_set(phys, mode, adj_mode); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index c7df8aa..d08b5d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -24,6 +24,7 @@ #include "dpu_hw_top.h" #include "dpu_hw_cdm.h" #include "dpu_encoder.h" +#include "dpu_crtc.h" #define DPU_ENCODER_NAME_MAX 16 @@ -219,7 +220,6 @@ struct dpu_encoder_irq { * @split_role: Role to play in a split-panel configuration * @intf_mode: Interface mode * @intf_idx: Interface index on dpu hardware - * @topology_name: topology selected for the display * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes * @enable_state: Enable state tracking * @vblank_refcount: Reference count of vblank request @@ -249,7 +249,6 @@ struct dpu_encoder_phys { enum dpu_enc_split_role split_role; enum dpu_intf_mode intf_mode; enum dpu_intf intf_idx; - enum dpu_rm_topology_name topology_name; spinlock_t *enc_spinlock; enum dpu_enc_enable_state enable_state; atomic_t vblank_refcount; @@ -367,11 +366,15 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( struct dpu_encoder_phys *phys_enc) { + struct dpu_crtc_state *dpu_cstate; + if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) return BLEND_3D_NONE; + dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); + if (phys_enc->split_role == ENC_ROLE_SOLO && - phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE) + (dpu_cstate->num_mixers == 2)) return BLEND_3D_H_ROW_INT; return BLEND_3D_NONE; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index a0b3744..88867c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -355,13 +355,14 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc) { + struct dpu_crtc_state *dpu_cstate; + if (!phys_enc) return false; - if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE) - return true; + dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); - return false; + return (dpu_cstate->num_ctls > 1); } static bool dpu_encoder_phys_vid_needs_single_flush( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 13c0a36..1457ae5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -146,18 +146,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm) return rm->hw_mdp; } -enum dpu_rm_topology_name -dpu_rm_get_topology_name(struct msm_display_topology topology) -{ - int i; - - for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) - if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology)) - return g_top_table[i].top_name; - - return DPU_RM_TOPOLOGY_NONE; -} - void dpu_rm_init_hw_iter( struct dpu_rm_hw_iter *iter, uint32_t enc_id, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index ffd1841..de52c03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -187,13 +187,4 @@ void dpu_rm_init_hw_iter( */ int dpu_rm_check_property_topctl(uint64_t val); -/** - * dpu_rm_get_topology_name - returns the name of the the given topology - * definition - * @topology: topology definition - * @Return: name of the topology - */ -enum dpu_rm_topology_name -dpu_rm_get_topology_name(struct msm_display_topology topology); - #endif /* __DPU_RM_H__ */ From patchwork Wed Aug 8 03:20:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559469 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C10F2139A for ; Wed, 8 Aug 2018 03:20:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B083A29359 for ; Wed, 8 Aug 2018 03:20:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A512D2A412; Wed, 8 Aug 2018 03:20:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5131E29359 for ; Wed, 8 Aug 2018 03:20:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53EC36E48C; Wed, 8 Aug 2018 03:20:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08E1B6E04F; Wed, 8 Aug 2018 03:20:32 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E76E560B22; Wed, 8 Aug 2018 03:20:31 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CC80360B23; Wed, 8 Aug 2018 03:20:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CC80360B23 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 11/13] drm/msm/dpu: remove display H_TILE from encoder Date: Tue, 7 Aug 2018 20:20:09 -0700 Message-Id: <1533698411-29819-2-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> References: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Encoder H_TILE values are not used for allocating the hw blocks. no. of hw_intf blocks provides the info. changes in v2: - none changes in v3: - none Change-Id: I1c1c13e9b9f608fbaa8c5897f9f1892029107ac5 Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 11 +++++------ 3 files changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 58647ed..fe0b563 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -179,8 +179,6 @@ struct dpu_encoder_virt { spinlock_t enc_spinlock; uint32_t bus_scaling_client; - uint32_t display_num_of_h_tiles; - unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; struct dpu_encoder_phys *cur_master; @@ -461,7 +459,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, /* Query resources used by phys encs, expected to be without overlap */ memset(hw_res, 0, sizeof(*hw_res)); - hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles; for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; @@ -2268,8 +2265,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, WARN_ON(disp_info->num_of_h_tiles < 1); - dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles; - DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 60f809f..e453271 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -33,14 +33,10 @@ * Encoder functions and data types * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused * @needs_cdm: Encoder requests a CDM based on pixel format conversion needs - * @display_num_of_h_tiles: Number of horizontal tiles in case of split - * interface - * @topology: Topology of the display */ struct dpu_encoder_hw_resources { enum dpu_intf_mode intfs[INTF_MAX]; bool needs_cdm; - u32 display_num_of_h_tiles; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 1457ae5..3444469 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -817,12 +817,11 @@ static int _dpu_rm_populate_requirements( conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS); - DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl, - reqs->hw_res.display_num_of_h_tiles); - DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n", - reqs->topology->num_lm, reqs->topology->num_ctl, - reqs->topology->top_name, - reqs->topology->needs_split_display); + DPU_DEBUG("top_ctrl: 0x%llX\n", reqs->top_ctrl); + DPU_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n", + reqs->topology->num_lm, reqs->topology->num_ctl, + reqs->topology->top_name, + reqs->topology->needs_split_display); return 0; } From patchwork Wed Aug 8 03:20:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559471 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 86C9D139A for ; Wed, 8 Aug 2018 03:20:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7627529359 for ; Wed, 8 Aug 2018 03:20:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6A9982A412; Wed, 8 Aug 2018 03:20:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 119E52A3F1 for ; Wed, 8 Aug 2018 03:20:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4FBF6E4A0; Wed, 8 Aug 2018 03:20:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 01BA16E1EF; Wed, 8 Aug 2018 03:20:32 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E30BF60BDE; Wed, 8 Aug 2018 03:20:32 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DFED960B7D; Wed, 8 Aug 2018 03:20:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DFED960B7D From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 12/13] drm/msm/dpu: add atomic private object to dpu kms Date: Tue, 7 Aug 2018 20:20:10 -0700 Message-Id: <1533698411-29819-3-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> References: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Subclass drm private state for DPU for handling driver specific data. Adds atomic private object and private object lock to dpu kms. Provides helper function to retrieve DPU private data from current atomic state. changes in v2: - none changes in v3: - rebase on [1] [1] https://gitlab.freedesktop.org/seanpaul/dpu-staging/commits/for-next Change-Id: Iaab32badff224ffed024e6ef6576efc8b3af3aec Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 61 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 15 ++++++++ 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 7dd6bd2..5e87b9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1168,10 +1168,59 @@ static int dpu_kms_hw_init(struct msm_kms *kms) return rc; } +struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state *state) +{ + struct msm_drm_private *priv = state->dev->dev_private; + struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); + struct drm_private_state *priv_state; + int rc = 0; + + rc = drm_modeset_lock(&dpu_kms->priv_obj_lock, state->acquire_ctx); + if (rc) + return ERR_PTR(rc); + + priv_state = drm_atomic_get_private_obj_state(state, + &dpu_kms->priv_obj); + if (IS_ERR(priv_state)) + return ERR_PTR(-ENOMEM); + + return to_dpu_private_state(priv_state); +} + +static struct drm_private_state * +dpu_private_obj_duplicate_state(struct drm_private_obj *obj) +{ + struct dpu_private_state *dpu_priv_state; + + dpu_priv_state = kmemdup(obj->state, + sizeof(*dpu_priv_state), GFP_KERNEL); + if (!dpu_priv_state) + return NULL; + + __drm_atomic_helper_private_obj_duplicate_state(obj, + &dpu_priv_state->base); + + return &dpu_priv_state->base; +} + +static void dpu_private_obj_destroy_state(struct drm_private_obj *obj, + struct drm_private_state *state) +{ + struct dpu_private_state *dpu_priv_state = to_dpu_private_state(state); + + kfree(dpu_priv_state); +} + +static const struct drm_private_state_funcs priv_obj_funcs = { + .atomic_duplicate_state = dpu_private_obj_duplicate_state, + .atomic_destroy_state = dpu_private_obj_destroy_state, +}; + struct msm_kms *dpu_kms_init(struct drm_device *dev) { struct msm_drm_private *priv; struct dpu_kms *dpu_kms; + struct dpu_private_state *dpu_priv_state; int irq; if (!dev || !dev->dev_private) { @@ -1189,6 +1238,18 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev) } dpu_kms->base.irq = irq; + /* Initialize private obj's */ + drm_modeset_lock_init(&dpu_kms->priv_obj_lock); + + dpu_priv_state = kzalloc(sizeof(*dpu_priv_state), GFP_KERNEL); + if (!dpu_priv_state) + return ERR_PTR(-ENOMEM); + + + drm_atomic_private_obj_init(&dpu_kms->priv_obj, + &dpu_priv_state->base, + &priv_obj_funcs); + return &dpu_kms->base; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 66d4666..2579c983 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -145,6 +145,9 @@ struct dpu_kms { struct dpu_hw_vbif *hw_vbif[VBIF_MAX]; struct dpu_hw_mdp *hw_mdp; + struct drm_modeset_lock priv_obj_lock; + struct drm_private_obj priv_obj; + bool has_danger_ctrl; struct platform_device *pdev; @@ -152,12 +155,24 @@ struct dpu_kms { struct dss_module_power mp; }; +struct dpu_private_state { + struct drm_private_state base; +}; + struct vsync_info { u32 frame_count; u32 line_count; }; #define to_dpu_kms(x) container_of(x, struct dpu_kms, base) +#define to_dpu_private_state(x) container_of(x, struct dpu_private_state, base) + +/** + * dpu_get_private_state - get dpu private state from atomic state + * @state: drm atomic state + * Return: pointer to dpu private state object + */ +struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state *state); /* get struct msm_kms * from drm_device * */ #define ddev_to_msm_kms(D) ((D) && (D)->dev_private ? \ From patchwork Wed Aug 8 03:20:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10559475 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82E3413B4 for ; Wed, 8 Aug 2018 03:20:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D9D32A3F1 for ; Wed, 8 Aug 2018 03:20:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 615002A413; Wed, 8 Aug 2018 03:20:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D8F52A3F1 for ; Wed, 8 Aug 2018 03:20:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02ADB6E4AB; Wed, 8 Aug 2018 03:20:44 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE07C6E4A8; Wed, 8 Aug 2018 03:20:42 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7843C60B7F; Wed, 8 Aug 2018 03:20:38 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DD63060BE1; Wed, 8 Aug 2018 03:20:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DD63060BE1 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 13/13] drm/msm/dpu: use private obj to track hw resources Date: Tue, 7 Aug 2018 20:20:11 -0700 Message-Id: <1533698411-29819-4-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> References: <1533698411-29819-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Switch to state based resource management. This patch overhauls the resource manager and HW allocation methods by maintaining the global resource pool and allocated hw blocks in respective drm component states. Global resource manager(RM) is tracked in private object. Allocation strategy is switched from single point allocation of HW resources for the display pipeline to per component based allocation, where each drm component allocates HW blocks mapped to it's domain and tracks them in their respective state objects. Fix resource contention due to race conditions between user space and display thread by reserving resources only in atomic check. changes in v2: - none changes in v3: - rebased on [1] - fix control path bug in split LM topology [1] https://gitlab.freedesktop.org/seanpaul/dpu-staging/commits/for-next Change-Id: Ie9d42eb3e93257816daf3d36c444a335645d65c6 Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 165 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 32 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 133 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 783 ++++++--------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 140 ++-- 9 files changed, 451 insertions(+), 853 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 0eb369c..dbff870 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -48,6 +48,8 @@ #define RIGHT_MIXER 1 #define MISR_BUFF_SIZE 256 +#define MAX_VDISPLAY_SPLIT 1080 + static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) { @@ -258,16 +260,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) DPU_DEBUG("%s\n", dpu_crtc->name); - if (cstate->num_mixers > CRTC_DUAL_MIXERS) { - DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers); - return; - } - for (i = 0; i < cstate->num_mixers; i++) { - if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { - DPU_ERROR("invalid lm or ctl assigned to mixer\n"); - return; - } mixer[i].mixer_op_mode = 0; mixer[i].flush_mask = 0; if (mixer[i].lm_ctl->ops.clear_all_blendstages) @@ -498,75 +491,33 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc, trace_dpu_crtc_complete_commit(DRMID(crtc)); } -static void _dpu_crtc_setup_mixer_for_encoder( - struct drm_crtc *crtc, - struct drm_encoder *enc) +static void _dpu_crtc_setup_mixers(struct drm_crtc_state *crtc_state) { - struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); - struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); - struct dpu_rm *rm = &dpu_kms->rm; + struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); struct dpu_crtc_mixer *mixer; - struct dpu_hw_ctl *last_valid_ctl = NULL; - int i; - struct dpu_rm_hw_iter lm_iter, ctl_iter; - - dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM); - dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL); + int i = 0, j = 0; - /* Set up all the mixers and ctls reserved by this encoder */ - for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) { - mixer = &cstate->mixers[i]; - - if (!dpu_rm_get_hw(rm, &lm_iter)) - break; - mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw; - - /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ - if (!dpu_rm_get_hw(rm, &ctl_iter)) { - DPU_DEBUG("no ctl assigned to lm %d, using previous\n", - mixer->hw_lm->idx - LM_0); - mixer->lm_ctl = last_valid_ctl; - } else { - mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; - last_valid_ctl = mixer->lm_ctl; - } - - /* Shouldn't happen, mixers are always >= ctls */ - if (!mixer->lm_ctl) { - DPU_ERROR("no valid ctls found for lm %d\n", - mixer->hw_lm->idx - LM_0); - return; - } - - mixer->encoder = enc; - - cstate->num_mixers++; - DPU_DEBUG("setup mixer %d: lm %d\n", - i, mixer->hw_lm->idx - LM_0); - DPU_DEBUG("setup mixer %d: ctl %d\n", - i, mixer->lm_ctl->idx - CTL_0); + if (cstate->num_mixers < cstate->num_ctls) { + DPU_ERROR( + "lm count(%d) < ctl count(%d). No support for such topologies\n", + cstate->num_mixers, + cstate->num_ctls); + return; } -} -static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) -{ - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); - struct drm_encoder *enc; - - cstate->num_mixers = 0; - memset(cstate->mixers, 0, sizeof(cstate->mixers)); + /* Set up all the mixers and ctls reserved by this encoder */ + for (i = 0; i < cstate->num_mixers; i++) { + /* 3D merge topology can have num_mixers > num_ctls */ + if (i < cstate->num_ctls) + j = i; - mutex_lock(&dpu_crtc->crtc_lock); - /* Check for mixers on all encoders attached to this crtc */ - list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { - if (enc->crtc != crtc) - continue; + cstate->mixers[i].lm_ctl = cstate->hw_ctls[j]; + mixer = &cstate->mixers[i]; - _dpu_crtc_setup_mixer_for_encoder(crtc, enc); + DPU_DEBUG("setup mixer %d: lm(%d) - ctl(%d)\n", + i, mixer->hw_lm->idx - LM_0, + mixer->lm_ctl->idx - CTL_0); } - - mutex_unlock(&dpu_crtc->crtc_lock); } static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, @@ -606,7 +557,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { struct dpu_crtc *dpu_crtc; - struct dpu_crtc_state *cstate; + struct dpu_crtc_state *new_cstate; struct drm_encoder *encoder; struct drm_device *dev; unsigned long flags; @@ -626,14 +577,11 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, DPU_DEBUG("crtc%d\n", crtc->base.id); dpu_crtc = to_dpu_crtc(crtc); - cstate = to_dpu_crtc_state(crtc->state); + new_cstate = to_dpu_crtc_state(crtc->state); dev = crtc->dev; smmu_state = &dpu_crtc->smmu_state; - if (!cstate->num_mixers) { - _dpu_crtc_setup_mixers(crtc); - _dpu_crtc_setup_lm_bounds(crtc, crtc->state); - } + _dpu_crtc_setup_lm_bounds(crtc, crtc->state); if (dpu_crtc->event) { WARN_ON(dpu_crtc->event); @@ -657,7 +605,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, * it means we are trying to flush a CRTC whose state is disabled: * nothing else needs to be done. */ - if (unlikely(!cstate->num_mixers)) + if (unlikely(!new_cstate->num_mixers)) return; _dpu_crtc_blend_setup(crtc); @@ -1069,9 +1017,9 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) { struct drm_crtc *crtc = arg; struct dpu_crtc *dpu_crtc; + struct dpu_crtc_state *cstate; struct drm_encoder *encoder; struct dpu_crtc_mixer *m; - struct dpu_crtc_state *cstate; u32 i, misr_status; if (!crtc) { @@ -1079,7 +1027,7 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg) return; } dpu_crtc = to_dpu_crtc(crtc); - cstate = to_dpu_crtc_state(dpu_crtc->base.state); + cstate = to_dpu_crtc_state(crtc->state); mutex_lock(&dpu_crtc->crtc_lock); @@ -1138,6 +1086,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) struct drm_display_mode *mode; struct drm_encoder *encoder; struct msm_drm_private *priv; + struct dpu_private_state *dpu_priv_state; + struct dpu_kms *dpu_kms; int ret; unsigned long flags; @@ -1149,6 +1099,10 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) cstate = to_dpu_crtc_state(crtc->state); mode = &cstate->base.adjusted_mode; priv = crtc->dev->dev_private; + dpu_kms = to_dpu_kms(priv->kms); + + /* accessing after swap state. piv_obj.state is the current state */ + dpu_priv_state = to_dpu_private_state(dpu_kms->priv_obj.state); DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); @@ -1195,13 +1149,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) dpu_power_handle_unregister_event(dpu_crtc->phandle, dpu_crtc->power_event); - memset(cstate->mixers, 0, sizeof(cstate->mixers)); - cstate->num_mixers = 0; - /* disable clk & bw control until clk & bw properties are set */ cstate->bw_control = false; cstate->bw_split_vote = false; + ret = dpu_rm_release_crtc_res(&dpu_priv_state->rm, cstate); + if (ret) + DPU_ERROR("error in releasing crtc resources\n"); + mutex_unlock(&dpu_crtc->crtc_lock); if (crtc->state->event && !crtc->state->active) { @@ -1260,6 +1215,31 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, } +static struct dpu_crtc_topology +dpu_crtc_get_topology(struct dpu_crtc_state *cstate, + struct drm_display_mode *mode) +{ + struct dpu_crtc_topology topology; + + memset(&topology, 0, sizeof(topology)); + + /* Use split topology for width > 1080 */ + topology.num_lms = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1; + topology.num_ctls = cstate->num_intfs; + + topology.needs_realloc = (topology.num_lms != cstate->num_mixers) || + (topology.num_ctls != cstate->num_ctls); + + if (topology.needs_realloc) + DPU_DEBUG( + "crtc %d needs hw reallocation. lm (%d - %d) ctl(%d - %d)\n", + get_crtc_id(cstate), + cstate->num_mixers, topology.num_lms, + cstate->num_ctls, topology.num_ctls); + + return topology; +} + struct plane_state { struct dpu_plane_state *dpu_pstate; const struct drm_plane_state *drm_pstate; @@ -1277,6 +1257,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, const struct drm_plane_state *pstate; struct drm_plane *plane; struct drm_display_mode *mode; + struct dpu_crtc_topology topology; + struct dpu_private_state *dpu_priv_state; int cnt = 0, rc = 0, mixer_width, i, z_pos; @@ -1493,6 +1475,25 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } + /* Resource allocation */ + dpu_priv_state = dpu_get_private_state(state->state); + if (IS_ERR(dpu_priv_state)) + goto end; + + topology = dpu_crtc_get_topology(cstate, &state->adjusted_mode); + if (!topology.needs_realloc) + goto end; + + dpu_rm_release_crtc_res(&dpu_priv_state->rm, cstate); + rc = dpu_rm_reserve_crtc_res(&dpu_priv_state->rm, cstate, &topology); + if (rc) { + DPU_ERROR("failed to allocate resources for crtc: %d\n", + crtc->base.id); + goto end; + } + + _dpu_crtc_setup_mixers(state); + end: kfree(pstates); return rc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 5b85ca8..15c30a9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -30,6 +30,8 @@ /* define the maximum number of in-flight frame events */ #define DPU_CRTC_FRAME_EVENT_SIZE 4 +struct dpu_kms; + /** * enum dpu_crtc_client_type: crtc client type * @RT_CLIENT: RealTime client like video/cmd mode display @@ -83,15 +85,15 @@ struct dpu_crtc_smmu_state_data { /** * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC * @hw_lm: LM HW Driver context - * @lm_ctl: CTL Path HW driver context - * @encoder: Encoder attached to this lm & ctl + * @lm_ctl: CTL path for associated LM HW + * @hw_pp: Pingpong HW driver context * @mixer_op_mode: mixer blending operation mode * @flush_mask: mixer flush mask for ctl, mixer and pipe */ struct dpu_crtc_mixer { struct dpu_hw_mixer *hw_lm; struct dpu_hw_ctl *lm_ctl; - struct drm_encoder *encoder; + struct dpu_hw_pingpong *hw_pp; u32 mixer_op_mode; u32 flush_mask; }; @@ -117,6 +119,13 @@ struct dpu_crtc_frame_event { */ #define DPU_CRTC_MAX_EVENT_COUNT 16 +struct dpu_crtc_topology { + bool needs_realloc; + int num_ctls; + int num_lms; + int num_intfs; +}; + /** * struct dpu_crtc - virtualized CRTC data structure * @base : Base drm crtc structure @@ -220,6 +229,8 @@ struct dpu_crtc { * @mixers : List of active mixers * @num_ctls : Number of ctl paths in use * @hw_ctls : List of activel ctl paths + * @num_intf : Numeer of interfaces in uses + * @hw_intfs : List of interfaces in use */ struct dpu_crtc_state { struct drm_crtc_state base; @@ -237,11 +248,26 @@ struct dpu_crtc_state { u32 num_ctls; struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + + /** + * as drm encoders doesn't have dedicates state objects + * and drm connectors are not owned by DPU, maintain + * HW interface and other interface related blocks + * in crtc state + * + * TODO: No support for clone mode yet where a crtc + * can be attached with more than one encoder/connector. + */ + u32 num_intfs; + struct dpu_hw_intf *hw_intfs[CRTC_DUAL_MIXERS]; }; #define to_dpu_crtc_state(x) \ container_of(x, struct dpu_crtc_state, base) +/* get crtc id from dpu crtc state*/ +#define get_crtc_id(x) ((x->base.crtc)->base.id) + /** * dpu_crtc_get_mixer_width - get the mixer width * Mixer width will be same as panel width(/2 for split) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index fe0b563..9f5f59f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -69,8 +69,6 @@ #define IDLE_SHORT_TIMEOUT 1 -#define MAX_VDISPLAY_SPLIT 1080 - /** * enum dpu_enc_rc_events - events for resource control state machine * @DPU_ENC_RC_EVENT_KICKOFF: @@ -572,25 +570,32 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector, } } -static struct msm_display_topology dpu_encoder_get_topology( +static struct dpu_crtc_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, - struct dpu_kms *dpu_kms, - struct drm_display_mode *mode) + struct dpu_crtc_state *cstate) { - struct msm_display_topology topology; + struct dpu_crtc_topology topology; int i, intf_count = 0; + memset(&topology, 0, sizeof(topology)); + for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) if (dpu_enc->phys_encs[i]) intf_count++; - /* User split topology for width > 1080 */ - topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1; - topology.num_enc = 0; - topology.num_intf = intf_count; + topology.num_intfs = intf_count; + + topology.needs_realloc = (cstate->num_intfs != topology.num_intfs); + + if (topology.needs_realloc) + DPU_DEBUG_ENC(dpu_enc, + "crtc %d needs hw reallocation. intf (%d - %d)\n", + get_crtc_id(cstate), + cstate->num_intfs, topology.num_intfs); return topology; } + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, @@ -601,7 +606,10 @@ static int dpu_encoder_virt_atomic_check( struct dpu_kms *dpu_kms; const struct drm_display_mode *mode; struct drm_display_mode *adj_mode; - struct msm_display_topology topology; + struct dpu_crtc_topology topology; + struct dpu_crtc_state *dpu_cstate; + struct dpu_private_state *dpu_priv_state; + struct dpu_encoder_hw_resources enc_hw_res; int i = 0; int ret = 0; @@ -618,6 +626,7 @@ static int dpu_encoder_virt_atomic_check( dpu_kms = to_dpu_kms(priv->kms); mode = &crtc_state->mode; adj_mode = &crtc_state->adjusted_mode; + dpu_cstate = to_dpu_crtc_state(crtc_state); trace_dpu_enc_atomic_check(DRMID(drm_enc)); /* @@ -647,28 +656,35 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); + if (ret) + goto end; - /* Reserve dynamic resources now. Indicating AtomicTest phase */ - if (!ret) { - /* - * Avoid reserving resources when mode set is pending. Topology - * info may not be available to complete reservation. - */ - if (drm_atomic_crtc_needs_modeset(crtc_state) - && dpu_enc->mode_set_complete) { - ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state, - conn_state, topology, true); - dpu_enc->mode_set_complete = false; - } + /* hw resource allocation */ + dpu_encoder_get_hw_resources(drm_enc, &enc_hw_res, conn_state); + + dpu_priv_state = dpu_get_private_state(crtc_state->state); + if (IS_ERR(dpu_priv_state)) + goto end; + + topology = dpu_encoder_get_topology(dpu_enc, dpu_cstate); + if (!topology.needs_realloc) + goto end; + + dpu_rm_release_encoder_res(&dpu_priv_state->rm, dpu_cstate); + ret = dpu_rm_reserve_encoder_res(&dpu_priv_state->rm, + dpu_cstate, &enc_hw_res); + if (ret) { + DPU_ERROR_ENC(dpu_enc, + "failed to allocate hw resources\n"); + goto end; } - if (!ret) - drm_mode_set_crtcinfo(adj_mode, 0); + drm_mode_set_crtcinfo(adj_mode, 0); trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags); +end: return ret; } @@ -1014,11 +1030,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_kms *dpu_kms; struct list_head *connector_list; struct drm_connector *conn = NULL, *conn_iter; - struct dpu_rm_hw_iter pp_iter, ctl_iter; - struct msm_display_topology topology; - struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC]; - - int i = 0, ret; + struct dpu_crtc_state *dpu_cstate; + int i = 0; if (!drm_enc) { DPU_ERROR("invalid encoder\n"); @@ -1046,52 +1059,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, return; } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); - - /* Reserve dynamic resources now. Indicating non-AtomicTest phase */ - ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state, - conn->state, topology, false); - if (ret) { - DPU_ERROR_ENC(dpu_enc, - "failed to reserve hw resources, %d\n", ret); - return; - } - - dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { - dpu_enc->hw_pp[i] = NULL; - if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter)) - break; - dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw; - } - - dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { - hw_ctl[i] = NULL; - if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter)) - break; - hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw; - } + dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; if (phys) { - if (!dpu_enc->hw_pp[i]) { - DPU_ERROR_ENC(dpu_enc, - "no pp block assigned at idx: %d\n", i); - return; - } - phys->hw_pp = dpu_enc->hw_pp[i]; - - if (!hw_ctl[i]) { - DPU_ERROR_ENC(dpu_enc, - "no ctl block assigned at idx: %d\n", i); - return; - } - phys->hw_ctl = hw_ctl[i]; - + dpu_enc->hw_pp[i] = dpu_cstate->mixers[i].hw_pp; + phys->hw_pp = dpu_cstate->mixers[i].hw_pp; phys->connector = conn->state->connector; + phys->hw_ctl = dpu_cstate->mixers[i].lm_ctl; if (phys->ops.mode_set) phys->ops.mode_set(phys, mode, adj_mode); } @@ -1239,7 +1216,9 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) struct msm_drm_private *priv; struct dpu_kms *dpu_kms; struct drm_display_mode *mode; - int i = 0; + struct dpu_private_state *dpu_priv_state; + struct dpu_crtc_state *cstate; + int rc, i = 0; if (!drm_enc) { DPU_ERROR("invalid encoder\n"); @@ -1253,6 +1232,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) } mode = &drm_enc->crtc->state->adjusted_mode; + cstate = to_dpu_crtc_state(drm_enc->crtc->state); dpu_enc = to_dpu_encoder_virt(drm_enc); DPU_DEBUG_ENC(dpu_enc, "\n"); @@ -1260,6 +1240,9 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); + /* accessing after swap state. piv_obj.state is the current state */ + dpu_priv_state = to_dpu_private_state(dpu_kms->priv_obj.state); + trace_dpu_enc_disable(DRMID(drm_enc)); /* wait for idle */ @@ -1289,9 +1272,11 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) dpu_enc->cur_master = NULL; - DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); + rc = dpu_rm_release_encoder_res(&dpu_priv_state->rm, cstate); + if (rc) + DPU_ERROR("error in releasing encoder resources\n"); - dpu_rm_release(&dpu_kms->rm, drm_enc); + DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); } static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index d08b5d5..1bee60b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -374,7 +374,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); if (phys_enc->split_role == ENC_ROLE_SOLO && - (dpu_cstate->num_mixers == 2)) + (dpu_cstate->num_mixers == 2)) return BLEND_3D_H_ROW_INT; return BLEND_3D_NONE; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 88867c3..0db0d27 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -461,35 +461,25 @@ static int dpu_encoder_phys_vid_control_vblank_irq( static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) { - struct msm_drm_private *priv; struct dpu_encoder_phys_vid *vid_enc; - struct dpu_rm_hw_iter iter; struct dpu_hw_ctl *ctl; - u32 flush_mask = 0; + struct dpu_crtc_state *cstate; + u32 i, flush_mask = 0; if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev || !phys_enc->parent->dev->dev_private) { DPU_ERROR("invalid encoder/device\n"); return; } - priv = phys_enc->parent->dev->dev_private; - vid_enc = to_dpu_encoder_phys_vid(phys_enc); ctl = phys_enc->hw_ctl; - dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF); - while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) { - struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw; + cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); + for (i = 0; i < cstate->num_intfs; i++) { + struct dpu_hw_intf *hw_intf = cstate->hw_intfs[i]; - if (hw_intf->idx == phys_enc->intf_idx) { + if (hw_intf && (hw_intf->idx == phys_enc->intf_idx)) vid_enc->hw_intf = hw_intf; - break; - } - } - - if (!vid_enc->hw_intf) { - DPU_ERROR("hw_intf not assigned\n"); - return; } DPU_DEBUG_VIDENC(vid_enc, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 5e87b9d..5892b6c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -630,6 +630,7 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) { struct drm_device *dev; + struct dpu_private_state *dpu_priv_state; int i; dev = dpu_kms->dev; @@ -657,9 +658,12 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) } } - if (dpu_kms->rm_init) - dpu_rm_destroy(&dpu_kms->rm); - dpu_kms->rm_init = false; + dpu_priv_state = to_dpu_private_state(dpu_kms->priv_obj.state); + if (dpu_priv_state) { + if (dpu_priv_state->rm_init) + dpu_rm_destroy(&dpu_priv_state->rm); + dpu_priv_state->rm_init = false; + } if (dpu_kms->catalog) dpu_hw_catalog_deinit(dpu_kms->catalog); @@ -965,6 +969,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) struct dpu_kms *dpu_kms; struct drm_device *dev; struct msm_drm_private *priv; + struct dpu_private_state *dpu_priv_state; int i, rc = -EINVAL; if (!kms) { @@ -1065,16 +1070,16 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto power_error; } - rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio, - dpu_kms->dev); + dpu_priv_state = to_dpu_private_state(dpu_kms->priv_obj.state); + rc = dpu_rm_init(&dpu_priv_state->rm, dpu_kms->catalog, dpu_kms->mmio); if (rc) { DPU_ERROR("rm init failed: %d\n", rc); goto power_error; } - dpu_kms->rm_init = true; + dpu_priv_state->rm_init = true; - dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_kms->rm); + dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_priv_state->rm); if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) { rc = PTR_ERR(dpu_kms->hw_mdp); if (!dpu_kms->hw_mdp) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 2579c983..d24582a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -29,10 +29,10 @@ #include "dpu_hw_lm.h" #include "dpu_hw_interrupts.h" #include "dpu_hw_top.h" -#include "dpu_rm.h" #include "dpu_power_handle.h" #include "dpu_irq.h" #include "dpu_core_perf.h" +#include "dpu_rm.h" #define DRMID(x) ((x) ? (x)->base.id : -1) @@ -139,9 +139,6 @@ struct dpu_kms { struct drm_atomic_state *suspend_state; bool suspend_block; - struct dpu_rm rm; - bool rm_init; - struct dpu_hw_vbif *hw_vbif[VBIF_MAX]; struct dpu_hw_mdp *hw_mdp; @@ -157,6 +154,9 @@ struct dpu_kms { struct dpu_private_state { struct drm_private_state base; + + struct dpu_rm rm; + bool rm_init; }; struct vsync_info { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 3444469..e4d8fac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -21,124 +21,59 @@ #include "dpu_hw_intf.h" #include "dpu_encoder.h" #include "dpu_trace.h" - -#define RESERVED_BY_OTHER(h, r) \ - ((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) - -#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_LOCK)) -#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_CLEAR)) -#define RM_RQ_DS(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_DS)) -#define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \ - (t).num_comp_enc == (r).num_enc && \ - (t).num_intf == (r).num_intf) - -struct dpu_rm_topology_def { - enum dpu_rm_topology_name top_name; - int num_lm; - int num_comp_enc; - int num_intf; - int num_ctl; - int needs_split_display; -}; - -static const struct dpu_rm_topology_def g_top_table[] = { - { DPU_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false }, - { DPU_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false }, - { DPU_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true }, - { DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false }, -}; - -/** - * struct dpu_rm_requirements - Reservation requirements parameter bundle - * @top_ctrl: topology control preference from kernel client - * @top: selected topology for the display - * @hw_res: Hardware resources required as reported by the encoders - */ -struct dpu_rm_requirements { - uint64_t top_ctrl; - const struct dpu_rm_topology_def *topology; - struct dpu_encoder_hw_resources hw_res; -}; - -/** - * struct dpu_rm_rsvp - Use Case Reservation tagging structure - * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain - * By using as a tag, rather than lists of pointers to HW blocks used - * we can avoid some list management since we don't know how many blocks - * of each type a given use case may require. - * @list: List head for list of all reservations - * @seq: Global RSVP sequence number for debugging, especially for - * differentiating differenct allocations for same encoder. - * @enc_id: Reservations are tracked by Encoder DRM object ID. - * CRTCs may be connected to multiple Encoders. - * An encoder or connector id identifies the display path. - * @topology DRM<->HW topology use case - */ -struct dpu_rm_rsvp { - struct list_head list; - uint32_t seq; - uint32_t enc_id; - enum dpu_rm_topology_name topology; -}; +#include "dpu_rm.h" /** * struct dpu_rm_hw_blk - hardware block tracking list member - * @list: List head for list of all hardware blocks tracking items - * @rsvp: Pointer to use case reservation if reserved by a client - * @rsvp_nxt: Temporary pointer used during reservation to the incoming - * request. Will be swapped into rsvp if proposal is accepted * @type: Type of hardware block this structure tracks + * @drm_id: DRM component ID associated with the HW block * @id: Hardware ID number, within it's own space, ie. LM_X - * @catalog: Pointer to the hardware catalog entry for this block * @hw: Pointer to the hardware register access object for this block */ struct dpu_rm_hw_blk { - struct list_head list; - struct dpu_rm_rsvp *rsvp; - struct dpu_rm_rsvp *rsvp_nxt; enum dpu_hw_blk_type type; uint32_t id; + uint32_t rm_id; struct dpu_hw_blk *hw; }; -/** - * dpu_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging - */ -enum dpu_rm_dbg_rsvp_stage { - DPU_RM_STAGE_BEGIN, - DPU_RM_STAGE_AFTER_CLEAR, - DPU_RM_STAGE_AFTER_RSVPNEXT, - DPU_RM_STAGE_FINAL +static char *blk_name[DPU_HW_BLK_MAX] = { + "HW_TOP", + "HW_SSPP", + "HW_LM", + "HW_CTL", + "HW_CDM", + "HW_PINGPONG", + "HW_INTF", + "HW_WB" }; -static void _dpu_rm_print_rsvps( - struct dpu_rm *rm, - enum dpu_rm_dbg_rsvp_stage stage) +void dpu_rm_print_state(struct dpu_rm *rm) { - struct dpu_rm_rsvp *rsvp; - struct dpu_rm_hw_blk *blk; - enum dpu_hw_blk_type type; + int i; + + mutex_lock(&rm->rm_lock); - DPU_DEBUG("%d\n", stage); + DPU_ERROR("DPU RM state:\n"); + for (i = 0; i < DPU_HW_BLK_MAX; i++) { + int blk_len = rm->hw_blks_len[i]; + int *drm_map = rm->hw_drm_map[i]; + int j; - list_for_each_entry(rsvp, &rm->rsvps, list) { - DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq, - rsvp->enc_id, rsvp->topology); - } + if (!blk_len) + continue; - for (type = 0; type < DPU_HW_BLK_MAX; type++) { - list_for_each_entry(blk, &rm->hw_blks[type], list) { - if (!blk->rsvp && !blk->rsvp_nxt) + DPU_ERROR("%s\ttotal: %d\n", blk_name[i], blk_len); + + for (j = 0; j < blk_len; j++) { + if (!drm_map[j]) continue; - DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage, - (blk->rsvp) ? blk->rsvp->seq : 0, - (blk->rsvp) ? blk->rsvp->enc_id : 0, - (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0, - (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0, - blk->type, blk->id); + DPU_ERROR("\tidx:%d drm_id: %d\n", j, drm_map[j]); } } + + mutex_unlock(&rm->rm_lock); } struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm) @@ -148,17 +83,19 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm) void dpu_rm_init_hw_iter( struct dpu_rm_hw_iter *iter, - uint32_t enc_id, + uint32_t drm_id, enum dpu_hw_blk_type type) { memset(iter, 0, sizeof(*iter)); - iter->enc_id = enc_id; + iter->drm_id = drm_id; iter->type = type; } static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i) { - struct list_head *blk_list; + struct dpu_rm_hw_blk **blk_list; + uint32_t blk_len, index; + uint32_t *drm_map; if (!rm || !i || i->type >= DPU_HW_BLK_MAX) { DPU_ERROR("invalid rm\n"); @@ -166,33 +103,30 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i) } i->hw = NULL; - blk_list = &rm->hw_blks[i->type]; - - if (i->blk && (&i->blk->list == blk_list)) { - DPU_DEBUG("attempt resume iteration past last\n"); - return false; - } - - i->blk = list_prepare_entry(i->blk, blk_list, list); + blk_list = rm->hw_blks[i->type]; + blk_len = rm->hw_blks_len[i->type]; + drm_map = rm->hw_drm_map[i->type]; - list_for_each_entry_continue(i->blk, blk_list, list) { - struct dpu_rm_rsvp *rsvp = i->blk->rsvp; + for (index = i->index; index < blk_len; index++) { + struct dpu_rm_hw_blk *blk = blk_list[index]; - if (i->blk->type != i->type) { - DPU_ERROR("found incorrect block type %d on %d list\n", - i->blk->type, i->type); + if (!blk) { + DPU_ERROR("invalid block. index: %d type: %d\n", + index, i->type); return false; } - if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) { - i->hw = i->blk->hw; + if (drm_map[index] == i->drm_id) { + i->hw = blk->hw; + i->index = index + 1; + i->blk = blk; DPU_DEBUG("found type %d id %d for enc %d\n", - i->type, i->blk->id, i->enc_id); + i->type, blk->id, i->drm_id); return true; } } - DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id); + DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->drm_id); return false; } @@ -217,9 +151,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw) case DPU_HW_BLK_CTL: dpu_hw_ctl_destroy(hw); break; - case DPU_HW_BLK_CDM: - dpu_hw_cdm_destroy(hw); - break; case DPU_HW_BLK_PINGPONG: dpu_hw_pingpong_destroy(hw); break; @@ -239,26 +170,25 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw) int dpu_rm_destroy(struct dpu_rm *rm) { - - struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt; - struct dpu_rm_hw_blk *hw_cur, *hw_nxt; enum dpu_hw_blk_type type; + uint32_t i; if (!rm) { DPU_ERROR("invalid rm\n"); return -EINVAL; } - list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) { - list_del(&rsvp_cur->list); - kfree(rsvp_cur); - } + for (type = 0; type < DPU_HW_BLK_MAX; type++) { + uint32_t hw_blk_len = rm->hw_blks_len[type]; + for (i = 0; i < hw_blk_len; i++) { + struct dpu_rm_hw_blk *hw_cur = rm->hw_blks[type][i]; - for (type = 0; type < DPU_HW_BLK_MAX; type++) { - list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type], - list) { - list_del(&hw_cur->list); + if (!hw_cur) { + DPU_ERROR("Invalid hw block. type:%d i: %d\n", + type, i); + return -EINVAL; + } _dpu_rm_hw_destroy(hw_cur->type, hw_cur->hw); kfree(hw_cur); } @@ -293,9 +223,6 @@ static int _dpu_rm_hw_blk_create( case DPU_HW_BLK_CTL: hw = dpu_hw_ctl_init(id, mmio, cat); break; - case DPU_HW_BLK_CDM: - hw = dpu_hw_cdm_init(id, mmio, cat, hw_mdp); - break; case DPU_HW_BLK_PINGPONG: hw = dpu_hw_pingpong_init(id, mmio, cat); break; @@ -327,35 +254,24 @@ static int _dpu_rm_hw_blk_create( blk->type = type; blk->id = id; blk->hw = hw; - list_add_tail(&blk->list, &rm->hw_blks[type]); + blk->rm_id = rm->hw_blks_len[type]; + + rm->hw_blks[type][rm->hw_blks_len[type]++] = blk; return 0; } int dpu_rm_init(struct dpu_rm *rm, struct dpu_mdss_cfg *cat, - void __iomem *mmio, - struct drm_device *dev) + void __iomem *mmio) { int rc, i; - enum dpu_hw_blk_type type; - - if (!rm || !cat || !mmio || !dev) { - DPU_ERROR("invalid kms\n"); - return -EINVAL; - } /* Clear, setup lists */ memset(rm, 0, sizeof(*rm)); mutex_init(&rm->rm_lock); - INIT_LIST_HEAD(&rm->rsvps); - for (type = 0; type < DPU_HW_BLK_MAX; type++) - INIT_LIST_HEAD(&rm->hw_blks[type]); - - rm->dev = dev; - /* Some of the sub-blocks require an mdptop to be created */ rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat); if (IS_ERR_OR_NULL(rm->hw_mdp)) { @@ -380,18 +296,6 @@ int dpu_rm_init(struct dpu_rm *rm, DPU_ERROR("failed: lm hw not available\n"); goto fail; } - - if (!rm->lm_max_width) { - rm->lm_max_width = lm->sblk->maxwidth; - } else if (rm->lm_max_width != lm->sblk->maxwidth) { - /* - * Don't expect to have hw where lm max widths differ. - * If found, take the min. - */ - DPU_ERROR("unsupported: lm maxwidth differs\n"); - if (rm->lm_max_width > lm->sblk->maxwidth) - rm->lm_max_width = lm->sblk->maxwidth; - } } for (i = 0; i < cat->pingpong_count; i++) { @@ -426,15 +330,6 @@ int dpu_rm_init(struct dpu_rm *rm, } } - for (i = 0; i < cat->cdm_count; i++) { - rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_CDM, - cat->cdm[i].id, &cat->cdm[i]); - if (rc) { - DPU_ERROR("failed: cdm hw not available\n"); - goto fail; - } - } - return 0; fail: @@ -448,8 +343,7 @@ int dpu_rm_init(struct dpu_rm *rm, * proposed use case requirements, incl. hardwired dependent blocks like * pingpong * @rm: dpu resource manager handle - * @rsvp: reservation currently being created - * @reqs: proposed use case requirements + * @state: dpu crtc state handle * @lm: proposed layer mixer, function checks if lm, and all other hardwired * blocks connected to the lm (pp) is available and appropriate * @pp: output parameter, pingpong block attached to the layer mixer. @@ -460,8 +354,7 @@ int dpu_rm_init(struct dpu_rm *rm, */ static bool _dpu_rm_check_lm_and_get_connected_blks( struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - struct dpu_rm_requirements *reqs, + struct dpu_crtc_state *state, struct dpu_rm_hw_blk *lm, struct dpu_rm_hw_blk **pp, struct dpu_rm_hw_blk *primary_lm) @@ -486,12 +379,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks( } } - /* Already reserved? */ - if (RESERVED_BY_OTHER(lm, rsvp)) { - DPU_DEBUG("lm %d already reserved\n", lm_cfg->id); - return false; - } - dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG); while (_dpu_rm_get_hw_locked(rm, &iter)) { if (iter.blk->id == lm_cfg->pingpong) { @@ -505,35 +392,24 @@ static bool _dpu_rm_check_lm_and_get_connected_blks( return false; } - if (RESERVED_BY_OTHER(*pp, rsvp)) { - DPU_DEBUG("lm %d pp %d already reserved\n", lm->id, - (*pp)->id); - return false; - } - return true; } static int _dpu_rm_reserve_lms( - struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - struct dpu_rm_requirements *reqs) - + struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_crtc_topology *topology) { struct dpu_rm_hw_blk *lm[MAX_BLOCKS]; struct dpu_rm_hw_blk *pp[MAX_BLOCKS]; struct dpu_rm_hw_iter iter_i, iter_j; int lm_count = 0; - int i, rc = 0; - - if (!reqs->topology->num_lm) { - DPU_ERROR("invalid number of lm: %d\n", reqs->topology->num_lm); - return -EINVAL; - } + int i, drm_id = get_crtc_id(state); + int *lm_drm_map = rm->hw_drm_map[DPU_HW_BLK_LM]; + int *pp_drm_map = rm->hw_drm_map[DPU_HW_BLK_PINGPONG]; /* Find a primary mixer */ dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM); - while (lm_count != reqs->topology->num_lm && + while (lm_count != topology->num_lms && _dpu_rm_get_hw_locked(rm, &iter_i)) { memset(&lm, 0, sizeof(lm)); memset(&pp, 0, sizeof(pp)); @@ -542,8 +418,7 @@ static int _dpu_rm_reserve_lms( lm[lm_count] = iter_i.blk; if (!_dpu_rm_check_lm_and_get_connected_blks( - rm, rsvp, reqs, lm[lm_count], - &pp[lm_count], NULL)) + rm, state, lm[lm_count], &pp[lm_count], NULL)) continue; ++lm_count; @@ -551,14 +426,14 @@ static int _dpu_rm_reserve_lms( /* Valid primary mixer found, find matching peers */ dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM); - while (lm_count != reqs->topology->num_lm && + while (lm_count != topology->num_lms && _dpu_rm_get_hw_locked(rm, &iter_j)) { if (iter_i.blk == iter_j.blk) continue; if (!_dpu_rm_check_lm_and_get_connected_blks( - rm, rsvp, reqs, iter_j.blk, - &pp[lm_count], iter_i.blk)) + rm, state, iter_j.blk, + &pp[lm_count], iter_i.blk)) continue; lm[lm_count] = iter_j.blk; @@ -566,7 +441,7 @@ static int _dpu_rm_reserve_lms( } } - if (lm_count != reqs->topology->num_lm) { + if (lm_count != topology->num_lms) { DPU_DEBUG("unable to find appropriate mixers\n"); return -ENAVAIL; } @@ -575,492 +450,264 @@ static int _dpu_rm_reserve_lms( if (!lm[i]) break; - lm[i]->rsvp_nxt = rsvp; - pp[i]->rsvp_nxt = rsvp; + lm_drm_map[lm[i]->rm_id] = drm_id; + pp_drm_map[pp[i]->rm_id] = drm_id; - trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id, - pp[i]->id); + state->mixers[i].hw_lm = (struct dpu_hw_mixer *)lm[i]->hw; + state->mixers[i].hw_pp = (struct dpu_hw_pingpong *)pp[i]->hw; } - return rc; + state->num_mixers = topology->num_lms; + + return 0; } static int _dpu_rm_reserve_ctls( - struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - const struct dpu_rm_topology_def *top) + struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_crtc_topology *topology) { struct dpu_rm_hw_blk *ctls[MAX_BLOCKS]; struct dpu_rm_hw_iter iter; - int i = 0; + bool needs_split_display; + int i = 0, drm_id = get_crtc_id(state); + int *ctl_drm_map = rm->hw_drm_map[DPU_HW_BLK_CTL]; memset(&ctls, 0, sizeof(ctls)); + needs_split_display = (topology->num_ctls == 2); + dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL); while (_dpu_rm_get_hw_locked(rm, &iter)) { const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw); unsigned long features = ctl->caps->features; bool has_split_display; - if (RESERVED_BY_OTHER(iter.blk, rsvp)) - continue; - has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features; DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features); - if (top->needs_split_display != has_split_display) + if (needs_split_display != has_split_display) continue; ctls[i] = iter.blk; DPU_DEBUG("ctl %d match\n", iter.blk->id); - if (++i == top->num_ctl) + if (++i == topology->num_ctls) break; } - if (i != top->num_ctl) - return -ENAVAIL; - - for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) { - ctls[i]->rsvp_nxt = rsvp; - trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type, - rsvp->enc_id); - } - - return 0; -} - -static int _dpu_rm_reserve_cdm( - struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - uint32_t id, - enum dpu_hw_blk_type type) -{ - struct dpu_rm_hw_iter iter; - - DRM_DEBUG_KMS("type %d id %d\n", type, id); - - dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM); - while (_dpu_rm_get_hw_locked(rm, &iter)) { - const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw); - const struct dpu_cdm_cfg *caps = cdm->caps; - bool match = false; - - if (RESERVED_BY_OTHER(iter.blk, rsvp)) - continue; - - if (type == DPU_HW_BLK_INTF && id != INTF_MAX) - match = test_bit(id, &caps->intf_connect); - - DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n", - iter.blk->type, iter.blk->id, rsvp->enc_id, - caps->intf_connect, match); + if (i != topology->num_ctls) + return -EINVAL; - if (!match) - continue; + for (i = 0; i < ARRAY_SIZE(ctls) && i < topology->num_ctls; i++) { + ctl_drm_map[ctls[i]->rm_id] = drm_id; + state->hw_ctls[i] = (struct dpu_hw_ctl *)ctls[i]->hw; - trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type, - rsvp->enc_id); - iter.blk->rsvp_nxt = rsvp; - break; + trace_dpu_rm_reserve_ctls(ctls[i]->type, + get_crtc_id(state), ctls[i]->id); } - if (!iter.hw) { - DPU_ERROR("couldn't reserve cdm for type %d id %d\n", type, id); - return -ENAVAIL; - } + state->num_ctls = topology->num_ctls; return 0; } -static int _dpu_rm_reserve_intf( +static struct dpu_rm_hw_blk *_dpu_rm_get_hw_id( struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, uint32_t id, - enum dpu_hw_blk_type type, - bool needs_cdm) + enum dpu_hw_blk_type type) { struct dpu_rm_hw_iter iter; - int ret = 0; /* Find the block entry in the rm, and note the reservation */ dpu_rm_init_hw_iter(&iter, 0, type); while (_dpu_rm_get_hw_locked(rm, &iter)) { if (iter.blk->id != id) continue; - - if (RESERVED_BY_OTHER(iter.blk, rsvp)) { - DPU_ERROR("type %d id %d already reserved\n", type, id); - return -ENAVAIL; - } - - iter.blk->rsvp_nxt = rsvp; - trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type, - rsvp->enc_id); break; } - /* Shouldn't happen since intfs are fixed at probe */ if (!iter.hw) { DPU_ERROR("couldn't find type %d id %d\n", type, id); - return -EINVAL; + return NULL; } - if (needs_cdm) - ret = _dpu_rm_reserve_cdm(rm, rsvp, id, type); - - return ret; + return iter.blk; } static int _dpu_rm_reserve_intf_related_hw( struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, + struct dpu_crtc_state *state, struct dpu_encoder_hw_resources *hw_res) { - int i, ret = 0; - u32 id; + struct dpu_rm_hw_blk *intf[INTF_MAX] = {}; + u32 i, id, intf_count = 0; + u32 drm_id = get_crtc_id(state); + int *intf_drm_map = rm->hw_drm_map[DPU_HW_BLK_INTF]; for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) { if (hw_res->intfs[i] == INTF_MODE_NONE) continue; - id = i + INTF_0; - ret = _dpu_rm_reserve_intf(rm, rsvp, id, - DPU_HW_BLK_INTF, hw_res->needs_cdm); - if (ret) - return ret; - } - - return ret; -} -static int _dpu_rm_make_next_rsvp( - struct dpu_rm *rm, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - struct dpu_rm_rsvp *rsvp, - struct dpu_rm_requirements *reqs) -{ - int ret; - struct dpu_rm_topology_def topology; - - /* Create reservation info, tag reserved blocks with it as we go */ - rsvp->seq = ++rm->rsvp_next_seq; - rsvp->enc_id = enc->base.id; - rsvp->topology = reqs->topology->top_name; - list_add_tail(&rsvp->list, &rm->rsvps); - - ret = _dpu_rm_reserve_lms(rm, rsvp, reqs); - if (ret) { - DPU_ERROR("unable to find appropriate mixers\n"); - return ret; - } + id = i + INTF_0; + intf[i] = _dpu_rm_get_hw_id(rm, id, DPU_HW_BLK_INTF); + if (!intf[i]) + return -EINVAL; - /* - * Do assignment preferring to give away low-resource CTLs first: - * - Check mixers without Split Display - * - Only then allow to grab from CTLs with split display capability - */ - _dpu_rm_reserve_ctls(rm, rsvp, reqs->topology); - if (ret && !reqs->topology->needs_split_display) { - memcpy(&topology, reqs->topology, sizeof(topology)); - topology.needs_split_display = true; - _dpu_rm_reserve_ctls(rm, rsvp, &topology); + /* Reserve other INTF related blocks if needed */ } - if (ret) { - DPU_ERROR("unable to find appropriate CTL\n"); - return ret; - } - - /* Assign INTFs and blks whose usage is tied to them: CTL & CDM */ - ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res); - if (ret) - return ret; - - return ret; -} - -static int _dpu_rm_populate_requirements( - struct dpu_rm *rm, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - struct dpu_rm_requirements *reqs, - struct msm_display_topology req_topology) -{ - int i; - memset(reqs, 0, sizeof(*reqs)); - - dpu_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state); - - for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) { - if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], - req_topology)) { - reqs->topology = &g_top_table[i]; - break; - } - } + for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) { + if (!intf[i]) + continue; - if (!reqs->topology) { - DPU_ERROR("invalid topology for the display\n"); - return -EINVAL; + intf_drm_map[intf[i]->rm_id] = drm_id; + state->hw_intfs[intf_count++] = + (struct dpu_hw_intf *)intf[i]->hw; } - /** - * Set the requirement based on caps if not set from user space - * This will ensure to select LM tied with DS blocks - * Currently, DS blocks are tied with LM 0 and LM 1 (primary display) - */ - if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler && - conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) - reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS); - - DPU_DEBUG("top_ctrl: 0x%llX\n", reqs->top_ctrl); - DPU_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n", - reqs->topology->num_lm, reqs->topology->num_ctl, - reqs->topology->top_name, - reqs->topology->needs_split_display); + state->num_intfs = intf_count; return 0; } -static struct dpu_rm_rsvp *_dpu_rm_get_rsvp( +static int _dpu_rm_release_hw_blk( struct dpu_rm *rm, - struct drm_encoder *enc) + struct dpu_crtc_state *state, + enum dpu_hw_blk_type type) { - struct dpu_rm_rsvp *i; + struct dpu_rm_hw_iter iter; + int drm_id = get_crtc_id(state); + int num_released = 0; + int *drm_map = rm->hw_drm_map[type]; - if (!rm || !enc) { - DPU_ERROR("invalid params\n"); - return NULL; + dpu_rm_init_hw_iter(&iter, drm_id, type); + while (_dpu_rm_get_hw_locked(rm, &iter)) { + drm_map[iter.blk->rm_id] = 0; + num_released++; } - if (list_empty(&rm->rsvps)) - return NULL; - - list_for_each_entry(i, &rm->rsvps, list) - if (i->enc_id == enc->base.id) - return i; - - return NULL; + return num_released; } -static struct drm_connector *_dpu_rm_get_connector( - struct drm_encoder *enc) +static int _dpu_rm_release_lms(struct dpu_rm *rm, struct dpu_crtc_state *state) { - struct drm_connector *conn = NULL; - struct list_head *connector_list = - &enc->dev->mode_config.connector_list; + int num_lm, num_pp; - list_for_each_entry(conn, connector_list, head) - if (conn->encoder == enc) - return conn; + /* Release LM blocks */ + num_lm = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_LM); + + /* Rlease ping pong blocks */ + num_pp = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_PINGPONG); + if (num_pp != num_lm) { + DPU_ERROR("lm chain count mismatch lm: %d pp:%d\n", + num_lm, num_pp); + return 0; + } - return NULL; + return num_lm; } -/** - * _dpu_rm_release_rsvp - release resources and release a reservation - * @rm: KMS handle - * @rsvp: RSVP pointer to release and release resources for - */ -static void _dpu_rm_release_rsvp( - struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - struct drm_connector *conn) +int dpu_rm_reserve_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_crtc_topology *topology) { - struct dpu_rm_rsvp *rsvp_c, *rsvp_n; - struct dpu_rm_hw_blk *blk; - enum dpu_hw_blk_type type; - - if (!rsvp) - return; + int rc = 0; - DPU_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id); + mutex_lock(&rm->rm_lock); - list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) { - if (rsvp == rsvp_c) { - list_del(&rsvp_c->list); - break; - } + rc = _dpu_rm_reserve_lms(rm, state, topology); + if (rc) { + DPU_ERROR("unable to allocate lm for crtc: %d\n", + get_crtc_id(state)); + goto reserve_done; } - for (type = 0; type < DPU_HW_BLK_MAX; type++) { - list_for_each_entry(blk, &rm->hw_blks[type], list) { - if (blk->rsvp == rsvp) { - blk->rsvp = NULL; - DPU_DEBUG("rel rsvp %d enc %d %d %d\n", - rsvp->seq, rsvp->enc_id, - blk->type, blk->id); - } - if (blk->rsvp_nxt == rsvp) { - blk->rsvp_nxt = NULL; - DPU_DEBUG("rel rsvp_nxt %d enc %d %d %d\n", - rsvp->seq, rsvp->enc_id, - blk->type, blk->id); - } - } + rc = _dpu_rm_reserve_ctls(rm, state, topology); + if (rc) { + DPU_ERROR("unable to allocate ctl for crtc: %d\n", + get_crtc_id(state)); + goto reserve_done; } - kfree(rsvp); +reserve_done: + mutex_unlock(&rm->rm_lock); + + return 0; } -void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc) -{ - struct dpu_rm_rsvp *rsvp; - struct drm_connector *conn; - if (!rm || !enc) { - DPU_ERROR("invalid params\n"); - return; - } +int dpu_rm_release_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state) +{ + int rc = 0, num_released; mutex_lock(&rm->rm_lock); - rsvp = _dpu_rm_get_rsvp(rm, enc); - if (!rsvp) { - DPU_ERROR("failed to find rsvp for enc %d\n", enc->base.id); - goto end; + num_released = _dpu_rm_release_lms(rm, state); + if (num_released != state->num_mixers) { + DPU_ERROR( + "lm release count doesn't match for crtc: %d (%d != %d)\n", + get_crtc_id(state), num_released, state->num_mixers); + rc = -EINVAL; + goto release_done; } - conn = _dpu_rm_get_connector(enc); - if (!conn) { - DPU_ERROR("failed to get connector for enc %d\n", enc->base.id); - goto end; + num_released = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_CTL); + if (num_released != state->num_ctls) { + DPU_ERROR( + "lm release count doesn't match for crtc: %d (%d != %d)\n", + get_crtc_id(state), num_released, state->num_ctls); + rc = -EINVAL; + goto release_done; } - - _dpu_rm_release_rsvp(rm, rsvp, conn); -end: + release_done: mutex_unlock(&rm->rm_lock); -} - -static int _dpu_rm_commit_rsvp( - struct dpu_rm *rm, - struct dpu_rm_rsvp *rsvp, - struct drm_connector_state *conn_state) -{ - struct dpu_rm_hw_blk *blk; - enum dpu_hw_blk_type type; - int ret = 0; - - /* Swap next rsvp to be the active */ - for (type = 0; type < DPU_HW_BLK_MAX; type++) { - list_for_each_entry(blk, &rm->hw_blks[type], list) { - if (blk->rsvp_nxt) { - blk->rsvp = blk->rsvp_nxt; - blk->rsvp_nxt = NULL; - } - } - } - if (!ret) - DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id, - rsvp->topology); + state->num_mixers = 0; + state->num_ctls = 0; + memset(&state->mixers, 0, sizeof(state->mixers)); + memset(&state->hw_ctls, 0, sizeof(state->hw_ctls)); - return ret; + return rc; } -int dpu_rm_reserve( - struct dpu_rm *rm, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - struct msm_display_topology topology, - bool test_only) +int dpu_rm_reserve_encoder_res( + struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_encoder_hw_resources *hw_res) { - struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt; - struct dpu_rm_requirements reqs; - int ret; - - if (!rm || !enc || !crtc_state || !conn_state) { - DPU_ERROR("invalid arguments\n"); - return -EINVAL; - } - - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - - DRM_DEBUG_KMS("reserving hw for conn %d enc %d crtc %d test_only %d\n", - conn_state->connector->base.id, enc->base.id, - crtc_state->crtc->base.id, test_only); + int rc = 0; mutex_lock(&rm->rm_lock); - _dpu_rm_print_rsvps(rm, DPU_RM_STAGE_BEGIN); + rc = _dpu_rm_reserve_intf_related_hw(rm, state, hw_res); + if (rc) + DPU_ERROR("unable to allocate intf for crtc: %d\n", + get_crtc_id(state)); - ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, - conn_state, &reqs, topology); - if (ret) { - DPU_ERROR("failed to populate hw requirements\n"); - goto end; - } + mutex_unlock(&rm->rm_lock); - /* - * We only support one active reservation per-hw-block. But to implement - * transactional semantics for test-only, and for allowing failure while - * modifying your existing reservation, over the course of this - * function we can have two reservations: - * Current: Existing reservation - * Next: Proposed reservation. The proposed reservation may fail, or may - * be discarded if in test-only mode. - * If reservation is successful, and we're not in test-only, then we - * replace the current with the next. - */ - rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL); - if (!rsvp_nxt) { - ret = -ENOMEM; - goto end; - } + return rc; +} - rsvp_cur = _dpu_rm_get_rsvp(rm, enc); - - /* - * User can request that we clear out any reservation during the - * atomic_check phase by using this CLEAR bit - */ - if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) { - DPU_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n", - rsvp_cur->seq, rsvp_cur->enc_id); - _dpu_rm_release_rsvp(rm, rsvp_cur, conn_state->connector); - rsvp_cur = NULL; - _dpu_rm_print_rsvps(rm, DPU_RM_STAGE_AFTER_CLEAR); - } +int dpu_rm_release_encoder_res(struct dpu_rm *rm, struct dpu_crtc_state *state) +{ + int num_released; + int rc = 0; - /* Check the proposed reservation, store it in hw's "next" field */ - ret = _dpu_rm_make_next_rsvp(rm, enc, crtc_state, conn_state, - rsvp_nxt, &reqs); - - _dpu_rm_print_rsvps(rm, DPU_RM_STAGE_AFTER_RSVPNEXT); - - if (ret) { - DPU_ERROR("failed to reserve hw resources: %d\n", ret); - _dpu_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector); - } else if (test_only && !RM_RQ_LOCK(&reqs)) { - /* - * Normally, if test_only, test the reservation and then undo - * However, if the user requests LOCK, then keep the reservation - * made during the atomic_check phase. - */ - DPU_DEBUG("test_only: discard test rsvp[s%de%d]\n", - rsvp_nxt->seq, rsvp_nxt->enc_id); - _dpu_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector); - } else { - if (test_only && RM_RQ_LOCK(&reqs)) - DPU_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n", - rsvp_nxt->seq, rsvp_nxt->enc_id); - - _dpu_rm_release_rsvp(rm, rsvp_cur, conn_state->connector); - - ret = _dpu_rm_commit_rsvp(rm, rsvp_nxt, conn_state); - } + mutex_lock(&rm->rm_lock); - _dpu_rm_print_rsvps(rm, DPU_RM_STAGE_FINAL); + num_released = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_INTF); + if (num_released != state->num_intfs) { + DPU_ERROR( + "intf release count doesn't match for crtc: %d (%d != %d)\n", + get_crtc_id(state), num_released, state->num_intfs); + rc = -EINVAL; + } -end: mutex_unlock(&rm->rm_lock); - return ret; + state->num_intfs = 0; + memset(&state->hw_intfs, 0, sizeof(state->hw_intfs)); + + return rc; } + diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index de52c03..3e1fc7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -16,61 +16,28 @@ #define __DPU_RM_H__ #include - #include "msm_kms.h" #include "dpu_hw_top.h" +#include "dpu_encoder.h" -/** - * enum dpu_rm_topology_name - HW resource use case in use by connector - * @DPU_RM_TOPOLOGY_NONE: No topology in use currently - * @DPU_RM_TOPOLOGY_SINGLEPIPE: 1 LM, 1 PP, 1 INTF/WB - * @DPU_RM_TOPOLOGY_DUALPIPE: 2 LM, 2 PP, 2 INTF/WB - * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE: 2 LM, 2 PP, 3DMux, 1 INTF/WB - */ -enum dpu_rm_topology_name { - DPU_RM_TOPOLOGY_NONE = 0, - DPU_RM_TOPOLOGY_SINGLEPIPE, - DPU_RM_TOPOLOGY_DUALPIPE, - DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE, - DPU_RM_TOPOLOGY_MAX, -}; - -/** - * enum dpu_rm_topology_control - HW resource use case in use by connector - * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful - * test, reserve the resources for this display. - * Normal behavior would not impact the reservation - * list during the AtomicTest phase. - * @DPU_RM_TOPCTL_RESERVE_CLEAR: If set, in AtomicTest phase, before testing, - * release any reservation held by this display. - * Normal behavior would not impact the - * reservation list during the AtomicTest phase. - * @DPU_RM_TOPCTL_DS : Require layer mixers with DS capabilities - */ -enum dpu_rm_topology_control { - DPU_RM_TOPCTL_RESERVE_LOCK, - DPU_RM_TOPCTL_RESERVE_CLEAR, - DPU_RM_TOPCTL_DS, -}; +struct dpu_crtc_state; +struct dpu_crtc_topology; /** * struct dpu_rm - DPU dynamic hardware resource manager - * @dev: device handle for event logging purposes - * @rsvps: list of hardware reservations by each crtc->encoder->connector + * @hw_blks_len - number of hw blocks per type * @hw_blks: array of lists of hardware resources present in the system, one * list per type of hardware block + * @hw_drm_map - array to track each hw block type assignments * @hw_mdp: hardware object for mdp_top * @lm_max_width: cached layer mixer maximum width - * @rsvp_next_seq: sequence number for next reservation for debugging purposes * @rm_lock: resource manager mutex */ struct dpu_rm { - struct drm_device *dev; - struct list_head rsvps; - struct list_head hw_blks[DPU_HW_BLK_MAX]; + uint32_t hw_blks_len[DPU_HW_BLK_MAX]; + struct dpu_rm_hw_blk *hw_blks[DPU_HW_BLK_MAX][MAX_BLOCKS]; + int hw_drm_map[DPU_HW_BLK_MAX][MAX_BLOCKS]; struct dpu_hw_mdp *hw_mdp; - uint32_t lm_max_width; - uint32_t rsvp_next_seq; struct mutex rm_lock; }; @@ -90,23 +57,28 @@ struct dpu_rm { struct dpu_rm_hw_iter { void *hw; struct dpu_rm_hw_blk *blk; - uint32_t enc_id; + uint32_t drm_id; enum dpu_hw_blk_type type; + uint32_t index; }; /** + * dpu_rm_print_state - prints current RM state on resource pool + * @rm: DPU Resource Manager handle + */ +void dpu_rm_print_state(struct dpu_rm *rm); + +/** * dpu_rm_init - Read hardware catalog and create reservation tracking objects * for all HW blocks. * @rm: DPU Resource Manager handle * @cat: Pointer to hardware catalog * @mmio: mapped register io address of MDP - * @dev: device handle for event logging purposes * @Return: 0 on Success otherwise -ERROR */ int dpu_rm_init(struct dpu_rm *rm, struct dpu_mdss_cfg *cat, - void __iomem *mmio, - struct drm_device *dev); + void *mmio); /** * dpu_rm_destroy - Free all memory allocated by dpu_rm_init @@ -116,75 +88,47 @@ int dpu_rm_init(struct dpu_rm *rm, int dpu_rm_destroy(struct dpu_rm *rm); /** - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze - * the use connections and user requirements, specified through related - * topology control properties, and reserve hardware blocks to that - * display chain. - * HW blocks can then be accessed through dpu_rm_get_* functions. - * HW Reservations should be released via dpu_rm_release_hw. + * dpu_rm_reserve_crtc_res - Reserve HW blocks for CRTC * @rm: DPU Resource Manager handle - * @drm_enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle - * @conn_state: Proposed Atomic DRM Connector State handle - * @topology: Pointer to topology info for the display - * @test_only: Atomic-Test phase, discard results (unless property overrides) - * @Return: 0 on Success otherwise -ERROR + * @state: DPU CRTC state to cache HW block handles + * @topology: topology requirement for the display + * @Return: 0 on Success otherwise - ERROR */ -int dpu_rm_reserve(struct dpu_rm *rm, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - struct msm_display_topology topology, - bool test_only); +int dpu_rm_reserve_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_crtc_topology *topology); /** - * dpu_rm_reserve - Given the encoder for the display chain, release any - * HW blocks previously reserved for that use case. + * dpu_rm_release_crtc_res - Release HW blocks of the CRTC * @rm: DPU Resource Manager handle - * @enc: DRM Encoder handle - * @Return: 0 on Success otherwise -ERROR + * @state: DPU CRTC state to cache HW block handles + * @Return: 0 on Success otherwise - ERROR */ -void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc); +int dpu_rm_release_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state); /** - * dpu_rm_get_mdp - Retrieve HW block for MDP TOP. - * This is never reserved, and is usable by any display. + * dpu_rm_reserve_encoder_res - Reserve HW blocks for Encoder/Connector * @rm: DPU Resource Manager handle - * @Return: Pointer to hw block or NULL + * @state: DPU CRTC state to cache HW block handles + * @hw_res: interface block related info + * @Return: 0 on Success otherwise - ERROR */ -struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm); +int dpu_rm_reserve_encoder_res(struct dpu_rm *rm, struct dpu_crtc_state *state, + struct dpu_encoder_hw_resources *hw_res); /** - * dpu_rm_init_hw_iter - setup given iterator for new iteration over hw list - * using dpu_rm_get_hw - * @iter: iter object to initialize - * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder - * @type: Hardware Block Type client wishes to search for. - */ -void dpu_rm_init_hw_iter( - struct dpu_rm_hw_iter *iter, - uint32_t enc_id, - enum dpu_hw_blk_type type); -/** - * dpu_rm_get_hw - retrieve reserved hw object given encoder and hw type - * Meant to do a single pass through the hardware list to iteratively - * retrieve hardware blocks of a given type for a given encoder. - * Initialize an iterator object. - * Set hw block type of interest. Set encoder id of interest, 0 for any. - * Function returns first hw of type for that encoder. - * Subsequent calls will return the next reserved hw of that type in-order. - * Iterator HW pointer will be null on failure to find hw. + * dpu_rm_release_encoder_res - Release HW blocks of the Encoder/Connector * @rm: DPU Resource Manager handle - * @iter: iterator object - * @Return: true on match found, false on no match found + * @state: DPU CRTC state to cache HW block handles + * @Return: 0 on Success otherwise - ERROR */ -bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter); +int dpu_rm_release_encoder_res(struct dpu_rm *rm, struct dpu_crtc_state *state); /** - * dpu_rm_check_property_topctl - validate property bitmask before it is set - * @val: user's proposed topology control bitmask - * @Return: 0 on success or error + * dpu_rm_get_mdp - Retrieve HW block for MDP TOP. + * This is never reserved, and is usable by any display. + * @rm: DPU Resource Manager handle + * @Return: Pointer to hw block or NULL */ -int dpu_rm_check_property_topctl(uint64_t val); +struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm); #endif /* __DPU_RM_H__ */