From patchwork Tue May 10 18:33:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 12845431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E9BAC433EF for ; Tue, 10 May 2022 18:33:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD7B110E04C; Tue, 10 May 2022 18:33:34 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7FD9610E04C; Tue, 10 May 2022 18:33:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207613; x=1683743613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SupVKfeAI9Ku9MN/lddJrVkPyfH+dTXOv8pFD6CAfis=; b=TvdGvJt3c8yxsWSb4gsXzTnGJ5M49rA9xGmZvHS+ckJxFEaoPMFz0ryz nR9UcQmUynaUeKUeCmJ4WV53WvsS5aATjPaTWbyozUTiWXoaBNBNDoIzU fkAT9sdUwiyvdN93fjEvsFQoYVGVQ+QFsEMfe0oDw+ZmRbEM0TUDFgrfn OkbmzFdGza1WKHyhVYchtcchMTtPMczx4TdGW14c4wrFXAs3wL4p007BR wFlDaa0zgAtgxtjNP0tLPej0c65licD5E6Hum0b7k6005ESN/oCb9MPtd sBui2elze9UruoQjC7oPnbRYVv7N/UcFwMdwiJqHf2agUPEfmjVZzjFHB Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="267058473" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="267058473" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:33 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="593673573" Received: from lengdahl-mobl.ger.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.220.119]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:30 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Tue, 10 May 2022 21:33:11 +0300 Message-Id: <20220510183313.1046628-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183313.1046628-1-jouni.hogander@intel.com> References: <20220510183313.1046628-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v3 1/3] drm/print: Add drm_debug_once* macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Pearson , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add drm_debug_once* macros to allow printing out one time debug messages which can be still controlled via drm.debug parameter. Cc: José Roberto de Souza Cc: Mika Kahola Cc: Mark Pearson Signed-off-by: Jouni Högander Reviewed-by: José Roberto de Souza --- include/drm/drm_print.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h index 22fabdeed297..e339f47eeb6d 100644 --- a/include/drm/drm_print.h +++ b/include/drm/drm_print.h @@ -476,6 +476,35 @@ void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, #define drm_dbg_drmres(drm, fmt, ...) \ drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRMRES, fmt, ##__VA_ARGS__) +#define drm_dev_dbg_once(dev, cat, fmt, ...) \ +({ \ + static bool __print_once __read_mostly; \ + if (!__print_once) { \ + __print_once = true; \ + drm_dev_dbg(dev, cat, fmt, ##__VA_ARGS__); \ + } \ +}) + +#define drm_dbg_once_core(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_CORE, fmt, ##__VA_ARGS__) +#define drm_dbg_once(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) +#define drm_dbg_once_kms(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_KMS, fmt, ##__VA_ARGS__) +#define drm_dbg_once_prime(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_PRIME, fmt, ##__VA_ARGS__) +#define drm_dbg_once_atomic(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) +#define drm_dbg_once_vbl(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_VBL, fmt, ##__VA_ARGS__) +#define drm_dbg_once_state(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_STATE, fmt, ##__VA_ARGS__) +#define drm_dbg_once_lease(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_LEASE, fmt, ##__VA_ARGS__) +#define drm_dbg_once_dp(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) +#define drm_dbg_once_drmres(drm, fmt, ...) \ + drm_dev_dbg_once((drm) ? (drm)->dev : NULL, DRM_UT_DRMRES, fmt, ##__VA_ARGS__) /* * printk based logging From patchwork Tue May 10 18:33:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 12845432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD1FBC433F5 for ; Tue, 10 May 2022 18:33:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B37D210E1DE; Tue, 10 May 2022 18:33:37 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87FDE10E206; Tue, 10 May 2022 18:33:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207616; x=1683743616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AaHo4EhGB7NnUHsYKKbQNBVdt2CLsogT4iu2l1iyg44=; b=JB3bAeIce6C98T287YDYBtN/JhDvbQlyVqtiWijepKO2y23WBTCg7MkQ ZFKFaNylXFk9nZpjFmUi7YywyqD+P/1hkZeSaVGqmnkGD76fHwB/+K65k l0oGqBvvbS60cykRd/nKfq6nK9jw3PycLCX3yIb59uTanEfRBj0UD7Web rIcqDJDzUmoP17gviGQOVxF7RuPwGJM5ACd++eoIzjmjBcpk8F81wqg8N YKN2eqKDjKEymc/ZJwuqn6Sy/v+M9/2qaPZMfIipyQQgyIC74g3nbiIXn 13PiLv09f/mBT1ptFdMsaTxV5kIsx+Qw/qbupeTxbEaWi9MKrm0lvOsBv A==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="267058483" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="267058483" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:36 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="593673582" Received: from lengdahl-mobl.ger.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.220.119]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:34 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Tue, 10 May 2022 21:33:12 +0300 Message-Id: <20220510183313.1046628-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183313.1046628-1-jouni.hogander@intel.com> References: <20220510183313.1046628-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v3 2/3] drm/i915/psr: Use full update In case of area calculation fails X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Pearson , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we have some corner cases where area calculation fails. For these sel fetch area calculation ends up having update area as y1 = 0, y2 = 4. Instead of these values safer option is full update. One of such for example is big fb with offset. We don't have usable offset in psr2_sel_fetch_update. Currently it's open what is the proper way to fix this corner case. Use full update for now. v2: Commit message modified v3: Print out debug info once when area calculation fails Cc: José Roberto de Souza Cc: Mika Kahola Cc: Mark Pearson Signed-off-by: Jouni Högander Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 06db407e2749..3561c218cfb1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; struct intel_plane_state *new_plane_state, *old_plane_state; @@ -1770,6 +1771,17 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, clip_area_update(&pipe_clip, &damaged_area); } + /* + * TODO: For now we are just using full update in case + * selective fetch area calculation fails. To optimize this we + * should identify cases where this happens and fix the area + * calculation for those. + */ + if (pipe_clip.y1 == -1) { + drm_dbg_once_kms(&dev_priv->drm, "No selective fetch area, using full update"); + full_update = true; + } + if (full_update) goto skip_sel_fetch_set_loop; From patchwork Tue May 10 18:33:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 12845433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BA37C433FE for ; Tue, 10 May 2022 18:33:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 60B7E10E20D; Tue, 10 May 2022 18:33:41 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3A5110E20D; Tue, 10 May 2022 18:33:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207619; x=1683743619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=azreIronrxfuJvXhjQsXTuvqbQKAG1bIAKH0qaMlaFQ=; b=VBjOoflVnxWr5FEzbw/qAP0H82U1GjE6IiQKnYazpxmIE8PEhBPq81+T DtjuhdrP3vLSgkjy8EUvoccVGTOphsLaE+vt3BgesJYtjouy9rUQTXS7W LRzuoOJ1iUgakOMv1hplzbuhHNyFaHA4z+WX/uEgYiHIrn5cqNkB4xNcP ixiQKSmlNxwJYOzFr1Fe3K2x/sGtYIc2ygYgwyKaJg1+F+FrGZNkBXDIn Hx96YpG1gY/A3BQBa750prhrfdJI2iXV4BiJIc4gwgI2M+a0j3SLz3bjL mJWiSF2tblz84JMotms9QrWlsOxPi7HLEQhGjDfAyPNA4o9QQE0sF7u6C w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="267058503" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="267058503" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:39 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="593673600" Received: from lengdahl-mobl.ger.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.220.119]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:33:37 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Tue, 10 May 2022 21:33:13 +0300 Message-Id: <20220510183313.1046628-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183313.1046628-1-jouni.hogander@intel.com> References: <20220510183313.1046628-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915: Ensure damage clip area is within pipe area X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Pearson , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Current update area calculation is not handling situation where e.g. cursor plane is fully or partially outside pipe area. Fix this by checking damage area against pipe_src area using drm_rect_intersect. v2: Set x1 and x2 in damaged_area initialization v3: Move drm_rect_intersect into clip_area_update Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440 Cc: José Roberto de Souza Cc: Mika Kahola Cc: Mark Pearson Signed-off-by: Jouni Högander Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3561c218cfb1..f4b4c1c83d2b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1618,8 +1618,12 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, } static void clip_area_update(struct drm_rect *overlap_damage_area, - struct drm_rect *damage_area) + struct drm_rect *damage_area, + struct drm_rect *draw_area) { + if (!drm_rect_intersect(damage_area, draw_area)) + return; + if (overlap_damage_area->y1 == -1) { overlap_damage_area->y1 = damage_area->y1; overlap_damage_area->y2 = damage_area->y2; @@ -1709,7 +1713,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, */ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { - struct drm_rect src, damaged_area = { .y1 = -1 }; + struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, + .x2 = INT_MAX }; struct drm_atomic_helper_damage_iter iter; struct drm_rect clip; @@ -1736,20 +1741,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (old_plane_state->uapi.visible) { damaged_area.y1 = old_plane_state->uapi.dst.y1; damaged_area.y2 = old_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + clip_area_update(&pipe_clip, &damaged_area, + &crtc_state->pipe_src); } if (new_plane_state->uapi.visible) { damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + clip_area_update(&pipe_clip, &damaged_area, + &crtc_state->pipe_src); } continue; } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { /* If alpha changed mark the whole plane area as damaged */ damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + clip_area_update(&pipe_clip, &damaged_area, + &crtc_state->pipe_src); continue; } @@ -1760,7 +1768,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, &new_plane_state->uapi); drm_atomic_for_each_plane_damage(&iter, &clip) { if (drm_rect_intersect(&clip, &src)) - clip_area_update(&damaged_area, &clip); + clip_area_update(&damaged_area, &clip, + &crtc_state->pipe_src); } if (damaged_area.y1 == -1) @@ -1768,7 +1777,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; - clip_area_update(&pipe_clip, &damaged_area); + + clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); } /*