From patchwork Wed May 11 13:59:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= X-Patchwork-Id: 12846229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA9EDC433F5 for ; Wed, 11 May 2022 14:00:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.326899.549561 (Exim 4.92) (envelope-from ) id 1nomsX-0005rq-Lq; Wed, 11 May 2022 13:59:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 326899.549561; Wed, 11 May 2022 13:59:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nomsX-0005rj-J1; Wed, 11 May 2022 13:59:49 +0000 Received: by outflank-mailman (input) for mailman id 326899; Wed, 11 May 2022 13:59:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nomsX-0005rd-1y for xen-devel@lists.xenproject.org; Wed, 11 May 2022 13:59:49 +0000 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9d40c74b-d132-11ec-8fc4-03012f2f19d4; Wed, 11 May 2022 15:59:47 +0200 (CEST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id F3B80320096F; Wed, 11 May 2022 09:59:43 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Wed, 11 May 2022 09:59:44 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 11 May 2022 09:59:41 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9d40c74b-d132-11ec-8fc4-03012f2f19d4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1652277583; x=1652363983; bh=Lexwo3wAboDXzqe+46X7nnMk4/mtVtLozIW S6x7/VRo=; b=WLHZwkFadLKiZX167D+7OwsLV5K5hv4LjBYyFqyfLsOhhrc9czw 0QD7U6oGOzNaTOZSMOgWPGTeTtNU+NNK5UrLpNCx91OEotqyawBDPi6sRaklL92W Slj6S4S5Lw2n644xEsry82kk3dYNdbhUdAlvn9w+s8UgutmWJNVjejwfgX0g+nfk ouaRVBnJEoerD/ed1gEh41jhP5qHo5ZcRhGzt3AnB0Fc2VC1Ijhx+mFNUCXA0X/V ovsqpC2W3c9LHrd82cWYXePjjRBOdsw/K6frzRp3ZY811vMuJY2c8IQVrjm8VOlL ika9XVu+/AR4I5NI+GVm9DgVWmidvIlAWJg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrgeehgdeikecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffogggtgfesthekredtredtjeenucfhrhhomhepofgrrhgvkhcu ofgrrhgtiiihkhhofihskhhiqdfikphrvggtkhhiuceomhgrrhhmrghrvghksehinhhvih hsihgslhgvthhhihhnghhslhgrsgdrtghomheqnecuggftrfgrthhtvghrnhepleekhfdu leetleelleetteevfeefteffkeetteejheelgfegkeelgeehhfdthedvnecuvehluhhsth gvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmhgrrhhmrghrvghksehi nhhvihhsihgslhgvthhhihhnghhslhgrsgdrtghomh X-ME-Proxy: From: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Date: Wed, 11 May 2022 15:59:28 +0200 Message-Id: <20220511135929.1823116-1-marmarek@invisiblethingslab.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared by the PCI Local Bus Specification Revision 3.0 (from 2004) as "unknown"/"no connection". Fallback to poll mode in this case. The 0xff handling is x86-specific, the surrounding code is guarded with CONFIG_X86 anyway. Signed-off-by: Marek Marczykowski-Górecki Reviewed-by: Roger Pau Monné --- Changes in v4: - adjust log message, change it from WARNING to INFO - re-add x86 reference in the commit message Changes in v3: - change back to checking 0xff explicitly - adjust commit message, include spec reference - change warning to match the above Changes in v2: - add log message - extend commit message - code style fix --- xen/drivers/char/ns16550.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index fb75cee4a13a..c0d65cff62fe 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1238,6 +1238,13 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) pci_conf_read8(PCI_SBDF(0, b, d, f), PCI_INTERRUPT_LINE) : 0; + if ( uart->irq == 0xff ) + uart->irq = 0; + if ( !uart->irq ) + printk(XENLOG_INFO + "ns16550: %pp no legacy IRQ %d, using poll mode\n", + &PCI_SBDF(0, b, d, f), uart->irq); + return 0; } } From patchwork Wed May 11 13:59:29 2022 Content-Type: text/plain; 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Signed-off-by: Marek Marczykowski-Górecki Acked-by: Andrew Cooper --- Changes in v2: - new patch, adding more IDs to the patch that went in already --- xen/drivers/char/ns16550.c | 80 +++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index c0d65cff62fe..66b397391e3c 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1077,12 +1077,90 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x0358, .param = param_exar_xr17v358 }, - /* Intel Corp. TGL-LP LPSS PCI */ + /* Intel Corp. TGL-LP LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #2 */ { .vendor_id = PCI_VENDOR_ID_INTEL, .dev_id = 0xa0c7, .param = param_intel_lpss }, + /* Intel Corp. TGL-H LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51c7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51da, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7afe, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7adc, + .param = param_intel_lpss + }, }; static int __init