From patchwork Sun May 15 01:39:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 12849957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DF4CC433EF for ; Sun, 15 May 2022 01:41:36 +0000 (UTC) Received: from localhost ([::1]:33848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq3GJ-0005Ng-4a for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 21:41:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq3F0-0003JT-G0 for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:19 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:42911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nq3Ey-0002fU-QU for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:14 -0400 Received: by mail-pf1-x42a.google.com with SMTP id x23so10997143pff.9 for ; Sat, 14 May 2022 18:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D8CeNai5hoihLKkHUXkY+f/fMIbV4YMBEU8bGlpc+0s=; b=ZxVu/cWR+IvYjKbtcVhkX6CgIMce0aOWzjalwL2wGshyORidy66P6+Bjc0EHaLxZQX zWJs0Us8zRmxjs8KbEqS3wFXA/hxIXoFOddIxK3QalwddUI540zMCbV7god0uIISGdcI UrO73R5eVF6XkvfU/5GDhd5+jbvgF+/QK9h0Y/Ot2PolWUFN5sZ1nZBxrmtnkdjenH6r E7By7Bemwhq6vXXohRwHH+E9g/B2I4tdxJqMrgpaTlRLxPlX8Qav/yZp9JLKtmpbL1EG ZgKQTDGOeXOHlg9JrrxDL0TjMDSw6zu15qdGi0PWYFAT+7i9GfNvx+zLx+89uArvtxaM WaGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D8CeNai5hoihLKkHUXkY+f/fMIbV4YMBEU8bGlpc+0s=; b=ajKsiqEzCmoxNBJkoo2g37fHpWuJGFZk+rpO8Hj4Ah9fxY89Q6xA8hAiuY2YpWY1lX aO3B181k6Zeu9hOUTzoxBbDfUzc+OB9vOFj8A7kx9S7ggxmW3RQAJFyQv7+9hbc35Qu1 /jRrr3o/sH79ncEEZHNcvIb4pl+32E+ibLwOmg/y4rf6VvTElZz2eh4f+mVxoV76TlYH YWInfsOe/i6FJLHGSD8aAFdttbR1yuUXOMJhhv0gcFvL7cFQQIk3Jrb+gmxWc/vSIdzL 5rdbB3cmhP1wzzVRLJGSeeKGwTiIjpP/bnK6mD7eWEnh5jIXFGni5URu3h2UYuPBWfJt JcTw== X-Gm-Message-State: AOAM532Af97sHS1lRYgeosqxirNK02w86ICn90EgEAKL2RHerGfeIqPW Fx6aQoQP6e2pidpPUzebLsc8CehxgCc= X-Google-Smtp-Source: ABdhPJwqXroJ2r/qacIRI05lBh2vA9pp8s++Pd8zOjIilPil/xXH6iwHXu35zzRJtYFlCWjOpVn9fg== X-Received: by 2002:a05:6a00:134f:b0:50e:10e0:ef82 with SMTP id k15-20020a056a00134f00b0050e10e0ef82mr11597338pfu.45.1652578810890; Sat, 14 May 2022 18:40:10 -0700 (PDT) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id n26-20020a056a00213a00b00510749ae412sm4193425pfj.48.2022.05.14.18.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 18:40:10 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Openrisc , "Jason A. Donenfeld" , Stafford Horne , Peter Maydell , Jia Liu Subject: [PULL 1/4] hw/openrisc: page-align FDT address Date: Sun, 15 May 2022 10:39:45 +0900 Message-Id: <20220515013948.2993495-2-shorne@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220515013948.2993495-1-shorne@gmail.com> References: <20220515013948.2993495-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=shorne@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Jason A. Donenfeld" The QEMU-provided FDT was only being recognized by the kernel when it was used in conjunction with -initrd. Without it, the magic bytes wouldn't be there and the kernel couldn't load it. This patch fixes the issue by page aligning the provided FDT. Cc: Stafford Horne Cc: Peter Maydell Signed-off-by: Jason A. Donenfeld Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 8184caa60b..99b14940f4 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -356,7 +356,7 @@ static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start, } /* We put fdt right after the kernel and/or initrd. */ - fdt_addr = ROUND_UP(load_start, 4); + fdt_addr = TARGET_PAGE_ALIGN(load_start); ret = fdt_pack(fdt); /* Should only fail if we've built a corrupted tree */ From patchwork Sun May 15 01:39:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 12849959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5217C433F5 for ; Sun, 15 May 2022 01:43:35 +0000 (UTC) Received: from localhost ([::1]:38990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq3IE-0000Mt-NW for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 21:43:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq3F3-0003JW-Ds for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:19 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:38828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nq3F1-0002g7-Jg for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:17 -0400 Received: by mail-pj1-x1036.google.com with SMTP id o13-20020a17090a9f8d00b001df3fc52ea7so217050pjp.3 for ; Sat, 14 May 2022 18:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c+Kt0PArB3y+ijbSsfSsEw1SqbmDMmpC2y/OF67/b6Y=; b=ZFiVVPs+OoE2OHjiQwhQhNhC7syET1O/VDwbAFK9kRbQufA9FCzG3ohkNH6waAus/k PO4tfyRNBnCa9UyBf5o24NoU+4baTKRknUreS0ZpkgVIPyUMA2IB2Mk9cJtWsvhHkTDr qCjcClJ8TwYqbApuL7GdvlYZgJCpUYIJxpk1oT+S4zy7fPsbAjU7MI8daR7rC/2EQrPI TWwtswpeMyd/EgO/uyVrZcHkz7547I0zJ674j2tyBZpP8h5uJ8y7pZHr7lWGyqyLl4so jigpxyInPrmqTL8RdkxDvE0H6q/aJj5zd8OqKe4MQtRcHFoqjOPOKrnAldHNxuomtGSn edTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c+Kt0PArB3y+ijbSsfSsEw1SqbmDMmpC2y/OF67/b6Y=; b=OjmyULvD9Xdguv+EZ81gz3/Wc9D/lVo06wtxT1It5rWU6kIc+B30aEZNpJoKv9kBCR OJfJzrRfZi+4mj71VjWLTcHG2oUDiO0rOVb7LvSj9jk+ymZpLxBabnpaanWE6lFQKeXO 4lFpWSEAthe2IlN2/AZJvKh5kt04YMogGHkBgj6ga+xwoFJnImXYH8trbL9WqjpFk0Bj LOIkslQrTJBFWBbgqMB70TlctrwBb9vlwOsK4W/uDZq302HT4iAn5fCvAApg/PZx8/1G ReSrkvYbUYwsIGDun4YBd3R6TP5qXlTDG5ugQHCNCghHG39TRWTqYF/T7WIoSBQxf8/g MOPg== X-Gm-Message-State: AOAM530Mf7+NciQm6WzSmeYd0GcPyZYhE9LWT2pvODmtCXKWDpNEviqS 2h9PG7OKOZTUDn0z6rwew8dV9Mq2UGI= X-Google-Smtp-Source: ABdhPJwKQsWhgPLsoHqQ65D459M3CmWantwYMmq+pxgzfB2i5y4wF4QDN43zGZM/JzEn3e2qhskB1w== X-Received: by 2002:a17:90a:9bc6:b0:1d8:2d8e:1b97 with SMTP id b6-20020a17090a9bc600b001d82d8e1b97mr12242223pjw.45.1652578813760; Sat, 14 May 2022 18:40:13 -0700 (PDT) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id 2-20020a17090a19c200b001d5c571f487sm3795440pjj.25.2022.05.14.18.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 18:40:13 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Openrisc , "Jason A. Donenfeld" , Stafford Horne , Jia Liu Subject: [PULL 2/4] hw/openrisc: support 4 serial ports in or1ksim Date: Sun, 15 May 2022 10:39:46 +0900 Message-Id: <20220515013948.2993495-3-shorne@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220515013948.2993495-1-shorne@gmail.com> References: <20220515013948.2993495-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=shorne@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Jason A. Donenfeld" The 8250 serial controller supports 4 serial ports, so wire them all up, so that we can have more than one basic I/O channel. Cc: Stafford Horne Signed-off-by: Jason A. Donenfeld [smh:Fixup indentation and lines over 80 chars] Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 99b14940f4..6873124f74 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -71,6 +71,10 @@ enum { OR1KSIM_ETHOC_IRQ = 4, }; +enum { + OR1KSIM_UART_COUNT = 4 +}; + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -239,11 +243,13 @@ static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base, static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, hwaddr size, int num_cpus, - OpenRISCCPU *cpus[], int irq_pin) + OpenRISCCPU *cpus[], int irq_pin, + int uart_idx) { void *fdt = state->fdt; char *nodename; qemu_irq serial_irq; + char alias[sizeof("uart0")]; int i; if (num_cpus > 1) { @@ -258,7 +264,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, serial_irq = get_cpu_irq(cpus, 0, irq_pin); } serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, - serial_hd(0), DEVICE_NATIVE_ENDIAN); + serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), + DEVICE_NATIVE_ENDIAN); /* Add device tree node for serial. */ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); @@ -271,7 +278,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, /* The /chosen node is created during fdt creation. */ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); - qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename); + snprintf(alias, sizeof(alias), "uart%d", uart_idx); + qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename); g_free(nodename); } @@ -414,9 +422,11 @@ static void openrisc_sim_init(MachineState *machine) smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); } - openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base, - or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus, - OR1KSIM_UART_IRQ); + for (n = 0; n < OR1KSIM_UART_COUNT; ++n) + openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base + + or1ksim_memmap[OR1KSIM_UART].size * n, + or1ksim_memmap[OR1KSIM_UART].size, + smp_cpus, cpus, OR1KSIM_UART_IRQ, n); load_addr = openrisc_load_kernel(ram_size, kernel_filename); if (load_addr > 0) { From patchwork Sun May 15 01:39:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 12849958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6B0EC433F5 for ; Sun, 15 May 2022 01:41:37 +0000 (UTC) Received: from localhost ([::1]:34006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq3GK-0005U9-KD for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 21:41:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq3F7-0003K6-IH for qemu-devel@nongnu.org; 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Sat, 14 May 2022 18:40:15 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Openrisc , "Jason A. Donenfeld" , Stafford Horne , Jia Liu Subject: [PULL 3/4] hw/openrisc: use right OMPIC size variable Date: Sun, 15 May 2022 10:39:47 +0900 Message-Id: <20220515013948.2993495-4-shorne@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220515013948.2993495-1-shorne@gmail.com> References: <20220515013948.2993495-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=shorne@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Jason A. Donenfeld" This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too and doesn't allow the IPI to work in Linux. So set it to the old value. Signed-off-by: Jason A. Donenfeld [smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX] Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 6873124f74..35adce17ac 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -82,7 +82,7 @@ static const struct MemmapEntry { [OR1KSIM_DRAM] = { 0x00000000, 0 }, [OR1KSIM_UART] = { 0x90000000, 0x100 }, [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, - [OR1KSIM_OMPIC] = { 0x98000000, 16 }, + [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 }, }; static struct openrisc_boot_info { @@ -418,7 +418,7 @@ static void openrisc_sim_init(MachineState *machine) if (smp_cpus > 1) { openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base, - or1ksim_memmap[OR1KSIM_UART].size, + or1ksim_memmap[OR1KSIM_OMPIC].size, smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); } From patchwork Sun May 15 01:39:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 12849960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C71AC433EF for ; Sun, 15 May 2022 01:43:55 +0000 (UTC) Received: from localhost ([::1]:39380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq3IY-0000dL-IU for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 21:43:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq3F8-0003K7-R1 for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:23 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:42528) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nq3F7-0002hl-9m for qemu-devel@nongnu.org; Sat, 14 May 2022 21:40:22 -0400 Received: by mail-pg1-x530.google.com with SMTP id 202so10938079pgc.9 for ; Sat, 14 May 2022 18:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lGPG1Q4prfE/rl5qsEZlPOkMPbP4eygWnz8hzswRd/4=; b=cR3ws6f1/E0n2n7vF0zR7G67jsroEnEHUNMY6cXoS/GBFsBE970SVqSbPR6kfHuEWE bTNkyWdRYyjfFqlmjdo4LOZJ2VzvyjY66taMZiIPiTCfLuNTfr4N5toKGlSSy6sYN7PI UdzzSmTPFTtrK/5IL2VSm21b1hItDF505po+mrU3sK4ek8AiAA/zjHzeuVzBlWZrO0hL 8gr+e2kSPaZijFZmEkyruzxPZSi+Cr90yYBJ7iRTDfsY33S+/gYdCNMvmrsxCn9bUqZ/ Xawh3nu/BWcsBzOG+2evs8n1Z1ijhlVeDuvqVI/gXIfito6HVURzMRRBAOaQulpprE13 4AlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lGPG1Q4prfE/rl5qsEZlPOkMPbP4eygWnz8hzswRd/4=; b=WR2y1068YIWMGOW1pT713nR7P2VYkvGbEJV7nEs/DBUqI2OYV+uWMvlnk4KXBwwNdE 5aQD/lXawXzcjq+k0mc11LY/iMZnX4pMvEmb01Qbr3H2H9cFsCU1LEogSn7t4tD5e6wt Ujlupv/M2W03tFc6b5f6Ydy0ONNd8Jakg3rXrqfOtPrTsINTiYmiS7CsRQj9aqrtsuBq dgFZSmBdGsqmsvLvsIDIZIkOKc+u6nWBmYzzCSzhs5r3FzvotmrMFXLGvShVLuf4lug9 OlhObTbziovdFqJhq4Z/HvM5s31mlM198d4YKw+EIw4Waj2qM08//j2cAJxyzBR4+tB9 Impg== X-Gm-Message-State: AOAM530sboqHF9z6VDBsRtO3572c3Y08p5YfeXhgW5olZ/V1+uayORFQ ZQBMIlfngTW+K/Q/BhVWwoBuEu0lCSU= X-Google-Smtp-Source: ABdhPJxdD0fE1jz01AKQ4DOi818HJdV0mD+kfRa2p7eYzyLNUMND2BYOBU0loqL9wuXWCmSLNCPKRg== X-Received: by 2002:a05:6a00:1307:b0:50d:b02e:11df with SMTP id j7-20020a056a00130700b0050db02e11dfmr11435637pfu.4.1652578818293; Sat, 14 May 2022 18:40:18 -0700 (PDT) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id 21-20020a630b15000000b003db580384d6sm3963954pgl.60.2022.05.14.18.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 18:40:17 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Openrisc , "Jason A. Donenfeld" , Stafford Horne , Richard Henderson Subject: [PULL 4/4] target/openrisc: Do not reset delay slot flag on early tb exit Date: Sun, 15 May 2022 10:39:48 +0900 Message-Id: <20220515013948.2993495-5-shorne@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220515013948.2993495-1-shorne@gmail.com> References: <20220515013948.2993495-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=shorne@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This was found when running linux crypto algorithm selftests used by wireguard. We found that randomly the tests would fail. We found through investigation that a combination of a tick timer interrupt, raised when executing a delay slot instruction at a page boundary caused the issue. This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec. On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was being used as a fallback. The OpenRISC set_pc implementation clears dflag, which caused the exception handling logic to not account for the delay slot. This was the bug, because it meant when execution resumed after the interrupt was handling it resumed in the wrong place. Fix this by implementing synchronize_from_tb which simply updates pc, and not clear the delay slot flag. Reported-by: Jason A. Donenfeld Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dfbafc5236..41d1b2a24a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" +#include "exec/exec-all.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { @@ -30,6 +31,15 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.dflag = 0; } +static void openrisc_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + + cpu->env.pc = tb->pc; +} + + static bool openrisc_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | @@ -186,6 +196,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, + .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, #ifndef CONFIG_USER_ONLY .tlb_fill = openrisc_cpu_tlb_fill,