From patchwork Wed May 18 13:07:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99254C433EF for ; Wed, 18 May 2022 13:07:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D560510ED7B; Wed, 18 May 2022 13:07:51 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 10B1610ED7B for ; Wed, 18 May 2022 13:07:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879269; x=1684415269; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=W2Q2Vyy8Grwv5EuRltdYu6dOxiFA8e5FuA+XwcZhweg=; b=mnki5T24sXPXY+Lae14L2+doIZhBSV+HgiC97jMhmDc1+UN8pzIqOTr9 I2hprf/ekZIMCUSTbSBAc9pATW9Z05kH6Xn4wuijdv7e5jS3/scADtluZ 4fZaCodF5Qsi9Q0KAdAZHWLsjwaHRoUgiLb+X+PZLJjWjWKTJ+mkfoY+b CWE9cEEBfA6+a8Vcptq8KZg5K1LsxzTov6iKlsMk8xy4oBSGEtewRWOgx UKGOddPIqILH6/LvL3LZvRGqS52Bvd8Tne7bWRVcMDhyDdWDB7I+oSjOR yQtaaIuYOHa0n1QKPy07oPvOujwv8VmndG6fvw7+i4iHWhAa61+fQ4Jfm Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071686" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071686" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:33 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314269" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:30 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:11 +0530 Message-Id: <20220518130716.10936-3-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/7] drm/i915/dg1: OpRegion PCON DG1 MBD config support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD) configs. MBD config requires HOST BIOS GPIO toggling support in order to enable/disable VRAM SR using ACPI OpRegion. i915 requires to check OpRegion PCON MBD Config bits to discover whether Gfx Card is MBD config before enabling VRSR. BSpec: 53440 Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 36 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_opregion.h | 6 ++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index a728f4c2f532..3dcd54517b89 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -53,6 +53,8 @@ #define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */ #define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */ +#define PCON_DG1_MBD_CONFIG BIT(9) +#define PCON_DG1_MBD_CONFIG_FIELD_VALID BIT(10) #define PCON_DGFX_BIOS_SUPPORTS_VRSR BIT(11) #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID BIT(12) @@ -1242,6 +1244,37 @@ void intel_opregion_unregister(struct drm_i915_private *i915) opregion->lid_state = NULL; } +static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (!IS_DG1(i915)) + return false; + + if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID) + return opregion->header->pcon & PCON_DG1_MBD_CONFIG; + else + return false; +} + +/** + * intel_opregion_vram_sr_required(). + * @i915 i915 device priv data. + * It returns a boolean whether opregion vram_sr support + * is required. + */ +bool +intel_opregion_vram_sr_required(struct drm_i915_private *i915) +{ + if (!IS_DGFX(i915)) + return false; + + if (IS_DG1(i915)) + return intel_opregion_dg1_mbd_config(i915); + + return false; +} + /* * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self * Refresh capability support. @@ -1269,6 +1302,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) { struct intel_opregion *opregion = &i915->opregion; + if (!intel_opregion_vram_sr_required(i915)) + return; + if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n")) return; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h index 0aa1c4a8a482..a74686aa3cc3 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.h +++ b/drivers/gpu/drm/i915/display/intel_opregion.h @@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); struct edid *intel_opregion_get_edid(struct intel_connector *connector); bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915); void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable); +bool intel_opregion_vram_sr_required(struct drm_i915_private *i915); #else /* CONFIG_ACPI*/ @@ -138,6 +139,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) { } +static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915) +{ + return false; +} + #endif /* CONFIG_ACPI */ #endif From patchwork Wed May 18 13:07:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF102C433F5 for ; Wed, 18 May 2022 13:07:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E48B510ED89; Wed, 18 May 2022 13:07:51 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 50D0810ED89 for ; Wed, 18 May 2022 13:07:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879271; x=1684415271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8BlmBu7KXr8XiL6TmFdz3zj2E4GErws4EeI6kT0w8MI=; b=O+vfUwGMX4YIXbVlE6yrgnjTIZVY6ONj9vBHevdWg3fDlAzXeROVKNEF lRD34oy7eBx7Cg9P75W4gYgeQjoa4YBDfU1AVVA9ke1P7CLs6W9nJBoqe Hygcuu7S2JZrvQolk13Q4JLvkBTNJ6MlbYaIeQCdl03MIhDHSVV5EVb+B 60KvD6Zd8x9+wDU9YKxha/DX8/Lgrztf11C7+xJWfHmiZr29JM2JKgQEa UfnSmeGILWzz4/aJ4xRr5blLv3xCfUchtIxKnei7hYlkmGsb83nLKQeB1 Y8B/UW32hovQ5rqs4EBnvTC9ZzZxtOwdIIfsTTQ40/OoCH1zK38GCfU8t Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071708" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071708" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:36 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314285" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:33 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:12 +0530 Message-Id: <20220518130716.10936-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/7] drm/i915/dg2: DG2 MBD config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add DG2 Motherboard Down Config check support. BSpec: 44477 Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 3dcd54517b89..dec7628522c5 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -1271,6 +1271,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915) if (IS_DG1(i915)) return intel_opregion_dg1_mbd_config(i915); + else if (IS_DG2_MBD(i915)) + return true; return false; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 10f273800645..c5ecc490dced 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1071,6 +1071,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_DG2_G12(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) +/* + * FIXME: Need to define a new SUBPLATFORM INTEL_SUBPLATFORM_DG2_MBD + * for PCI id range 5690..5695, but G10, G11 SUBPLATFROM conflicts + * with those pci id range. + */ +#define DG2_MBD_CONFIG_MASK GENMASK(7, 4) +#define DG2_MBD_CONFIG_VAL FIELD_PREP(DG2_MBD_CONFIG_MASK, 9) +#define IS_DG2_MBD(dev_priv) (IS_DG2(dev_priv) && \ + (INTEL_DEVID(dev_priv) & DG2_MBD_CONFIG_MASK) == DG2_MBD_CONFIG_VAL) #define IS_ADLS_RPLS(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_N(dev_priv) \ From patchwork Wed May 18 13:07:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45182C433F5 for ; Wed, 18 May 2022 13:07:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6F4910EE5D; Wed, 18 May 2022 13:07:55 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 079A810EE5E for ; Wed, 18 May 2022 13:07:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879272; x=1684415272; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QgmF85vseYXmTS8Yd08fZ57uDk7shmgUQ3D34D6a1sk=; b=niAEe22AHGvaolHcZV5SlB64zpe29A2axomgnEabPJmsZ8XN2i6GL5LY s0gkDPYOTXgZqNkQ9+77ecrvp9+ANLz8ttYUizEWnzyM7e9C7BN6Wamd/ jbbDak2sO/2LI+C4L+oyRMaqrZO0AZfbJGDQK4XQk4Joe14jGs7W4e2pZ ZE1Ka+NmT0CD94YYIdYulIBE7+neMn/8cOhHCt6GFxrqbtM9NYtjYxdrE DlCfTKEdmR7V1hqYgf6s8Kynx+aa8G1cYt3XH/9MbZjSI6WaduTlEtHzV hEuyjSgNdkCesRpN59LjCSAA2+iyicgSAJ/VAyTCEQdgbcIQvhYNg2+T+ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071741" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071741" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314303" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:36 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:13 +0530 Message-Id: <20220518130716.10936-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/7] drm/i915/dgfx: Add has_lmem_sr X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add has_lmem_sr platform specific flag to know, whether platform has VRAM self refresh support. As of now both DG1 and DG2 client platforms supports VRAM self refresh with D3Cold but let it enable first on DG2 as primary lead platform for D3Cold support. Let it get enable on DG1 once this feature is stable. Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c5ecc490dced..42463dc2979f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1360,6 +1360,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) +#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr) /* * Platform has the dedicated compression control state for each lmem surfaces diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d8d893bafa51..3347e3cce0a8 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -889,6 +889,7 @@ static const struct intel_device_info dg1_info = { DGFX_FEATURES, .graphics.rel = 10, PLATFORM(INTEL_DG1), + .has_lmem_sr = 0, .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), .require_force_probe = 1, .platform_engine_mask = @@ -1036,6 +1037,7 @@ static const struct intel_device_info xehpsdv_info = { static const struct intel_device_info dg2_info = { DG2_FEATURES, XE_LPD_FEATURES, + .has_lmem_sr = 1, .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D), .require_force_probe = 1, diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 60fc35ae81df..44bd993ef7fb 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -151,6 +151,7 @@ enum intel_ppgtt_type { func(has_l3_ccs_read); \ func(has_l3_dpf); \ func(has_llc); \ + func(has_lmem_sr); \ func(has_logical_ring_contexts); \ func(has_mslices); \ func(has_pooled_eu); \ From patchwork Wed May 18 13:07:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 834ABC433FE for ; Wed, 18 May 2022 13:07:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0C7010EE22; Wed, 18 May 2022 13:07:57 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7E4B10EDA2 for ; Wed, 18 May 2022 13:07:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879273; x=1684415273; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+pSBa1GnNKNtnpgN8PTvCzu5VMCKneJ23a+NFTDP3ak=; b=b8EMdXFrqKn0Yz6M1wVi87OH7baa5T6sZSm9U0V/pihKN+s09d+U0Pz0 O+VrdjpP71kfDiS4SXqZtfw3jYPRM1jlYFPvuCVkcF2Fm/AOUV9bMKZUn 7s8EC91vYWL9/YanaASkU1ShrFHBbsDFyJs87nYdZwchZ8HFMaKazNWGK r8RHE24C4tmVWn3xaI8w4/Hn7m3o72ZJYYO9bTTIU07mCoJDBPpgDRnP+ YhPlVs/IWCBtMYHNHJk6rw+W60nPmaBJJ674Lbfz54ZwTqY1yFXzBM5GS 55yOGNhGbxEvZnUFNg6WraNNMJmVjkHl2pNxwkqHWcnXOcfQ00QeWwvSB w==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071776" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071776" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:41 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314358" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:38 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:14 +0530 Message-Id: <20220518130716.10936-6-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/7] drm/i915/pcode: DGFX PCODE MBOX headers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DGFX uses similar PCODE MBOX interface as IGFX but uses distinct COMMAND and PARAM set of bit fields. Adding those headers Accordingly. Cc: Rodrigo Vivi Signed-off-by: Ashutosh Dixit Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 321a08281a3f..ec2609fa233b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6735,6 +6735,9 @@ #define GEN6_PCODE_MAILBOX _MMIO(0x138124) #define GEN6_PCODE_READY (1 << 31) +#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) +#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) +#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) #define GEN6_PCODE_ERROR_MASK 0xFF #define GEN6_PCODE_SUCCESS 0x0 #define GEN6_PCODE_ILLEGAL_CMD 0x1 From patchwork Wed May 18 13:07:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01FC7C433EF for ; Wed, 18 May 2022 13:07:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6660A10EDD8; Wed, 18 May 2022 13:07:57 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B47B510EDD8 for ; Wed, 18 May 2022 13:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879275; x=1684415275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CnmrX/MgcR7DXHlFrFAeCCJ1AIpkdGP2WxrbnSwx3+0=; b=ke/PLM3d6cqkC43SqA8Pr4PbQ/k0Uv77aDY0MSLRW0Q8M9AkCAiarzWb Ll4Ad45LW1HPFdiXqOCcOrYBITQyXU6njgKXeepRxTMU+aBfTb7i6sxCM wTOH7INJasihQSLWWdJAQBsnvwbtkhcwZnFi/7fIKz+8EOujyBI2LFwtN +H30ylYacnSU1L77wPTqNeBmmcWmjX+UtO8wdxSjtFc1GyyNidkXNW0Ww 9nLTfxioVudqvR3QXtor1FNsNSH58HdxjfYgFjm8BD7UGQ5WvR3sciCpY SpJ6ddVWXi9PDetX1UqSuZCF9OxbaXdkTDoHSPGzs27j3QG/jSe+DNSS1 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071814" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071814" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:44 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314378" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:41 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:15 +0530 Message-Id: <20220518130716.10936-7-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/7] drm/i915/dgfx: Setup VRAM SR with D3COLD X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Setup VRAM Self Refresh with D3COLD state. VRAM Self Refresh will retain the context of VRAM, driver need to save any corresponding hardware state that needs to be restore on D3COLD exit, example PCI state. Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_driver.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 7 +++++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_pcode.c | 25 +++++++++++++++++ drivers/gpu/drm/i915/intel_pcode.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 43 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.h | 2 ++ 7 files changed, 84 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index ed6028fd442d..5a9d5529fc90 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -633,6 +633,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) if (ret) goto err_msi; + intel_pm_vram_sr_setup(dev_priv); + /* * Fill the dram structure to get the system dram info. This will be * used for memory latency calculation. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 42463dc2979f..e15207e6a166 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -688,6 +688,13 @@ struct drm_i915_private { u32 bxt_phy_grc; u32 suspend_count; + + struct { + /* lock to protect vram_sr flags */ + struct mutex lock; + bool supported; + } vram_sr; + struct i915_suspend_saved_registers regfile; struct vlv_s0ix_state *vlv_s0ix_state; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ec2609fa233b..50e6c7266f7a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6803,11 +6803,15 @@ #define DG1_PCODE_STATUS 0x7E #define DG1_UNCORE_GET_INIT_STATUS 0x0 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 +#define DG1_PCODE_D3_VRAM_SR 0x71 +#define DG1_ENABLE_SR 0x1 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) +#define VRAM_CAPABILITY _MMIO(0x138144) +#define VRAM_SUPPORTED REG_BIT(0) /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c index ac727546868e..43b2e7cfc458 100644 --- a/drivers/gpu/drm/i915/intel_pcode.c +++ b/drivers/gpu/drm/i915/intel_pcode.c @@ -225,3 +225,28 @@ int intel_pcode_init(struct drm_i915_private *i915) return ret; } + +/** + * intel_pcode_enable_vram_sr - Enable pcode vram_sr. + * @dev_priv: i915 device + * + * This function triggers the required pcode flow to enable vram_sr. + * This function stictly need to call from rpm handlers, as i915 is + * transitioning to rpm idle/suspend, it doesn't require to grab + * rpm wakeref. + */ +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915) +{ + int ret = 0; + + if (!HAS_LMEM_SR(i915)) + return ret; + + ret = snb_pcode_write(i915, + REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, + DG1_PCODE_D3_VRAM_SR) | + REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, + DG1_ENABLE_SR), 0); /* no data needed for this cmd */ + + return ret; +} diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h index 0962a17fac48..3f695bd027a1 100644 --- a/drivers/gpu/drm/i915/intel_pcode.h +++ b/drivers/gpu/drm/i915/intel_pcode.h @@ -20,5 +20,6 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request, u32 reply_mask, u32 reply, int timeout_base_ms); int intel_pcode_init(struct drm_i915_private *i915); +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915); #endif /* _INTEL_PCODE_H */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ee0047fdc95d..6c14752f2dc8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8153,6 +8153,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv) atomic_set(&dev_priv->runtime_pm.wakeref_count, 0); } +void intel_pm_vram_sr_setup(struct drm_i915_private *i915) +{ + if (!HAS_LMEM_SR(i915)) + return; + + mutex_init(&i915->vram_sr.lock); + + i915->vram_sr.supported = intel_uncore_read(&i915->uncore, + VRAM_CAPABILITY) & VRAM_SUPPORTED; + if (intel_opregion_vram_sr_required(i915)) + i915->vram_sr.supported = i915->vram_sr.supported && + intel_opregion_bios_supports_vram_sr(i915); +} + +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable) +{ + int ret = 0; + + if (!HAS_LMEM_SR(i915)) + return -EOPNOTSUPP; + + mutex_lock(&i915->vram_sr.lock); + if (!i915->vram_sr.supported) { + drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n"); + ret = -EOPNOTSUPP; + goto unlock; + } + + drm_dbg(&i915->drm, "VRAM Self Refresh supported\n"); + if (enable) + ret = intel_pcode_enable_vram_sr(i915); + + if (ret) + goto unlock; + + intel_opregion_vram_sr(i915, enable); + +unlock: + mutex_unlock(&i915->vram_sr.lock); + + return ret; +} + static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) { struct intel_dbuf_state *dbuf_state; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 50604cf7398c..0da85d6b9ea7 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv); void intel_init_pm(struct drm_i915_private *dev_priv); void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); void intel_pm_setup(struct drm_i915_private *dev_priv); +void intel_pm_vram_sr_setup(struct drm_i915_private *i915); +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable); void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); From patchwork Wed May 18 13:07:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12853646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96944C433F5 for ; Wed, 18 May 2022 13:08:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B2CA10ED93; Wed, 18 May 2022 13:08:00 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id EEC3310EDD8 for ; Wed, 18 May 2022 13:07:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652879276; x=1684415276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=irv+D35PTx3xSADxPJOUoMTtlfW0lv3c8qVEqXlqnwM=; b=Yu9KZniCNG+tFvqPz+raAX6BIU4ciewa3AppvEkAVk3FSpwqTOrM9xLQ g5W7Jm3y3lGLys4RowZM8TB0DzUpz1uw9OSa+0USGPywHF2+dsXfbKQIJ DFQQGXScWV46IivriOPmh85wLMwA8AIBedN4TbIE5mCRGd182QgFdisnb B7Od7O7yQbG2w1a3GyuF/zuczQdth2tDSqElx7MVJ8FjgEtt1SkY5o1H8 ISsXM9GYJh/1LEnxSlHj+GxKz7ESPNz9Bbmw1QHgObdp9KJQavXUu5pYc 6ROKF572FSTM/QbnAnQAthgdjQ7Ba1rL91yf30rItdGSKAZ0kWEiqpflh w==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="358071836" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="358071836" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:46 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="742314402" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 06:07:44 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 18:37:16 +0530 Message-Id: <20220518130716.10936-8-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/rpm: Enable D3Cold VRAM SR Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, Chris Wilson , rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Intel Client DGFX card supports D3Cold with two option. D3Cold-off zero watt, D3Cold-VRAM Self Refresh. i915 requires to evict the lmem objects to smem in order to support D3Cold-Off, which increases i915 the suspend/resume latency. Enabling VRAM Self Refresh feature optimize the latency with additional power cost which required to retain the lmem. Adding intel_runtime_idle (runtime_idle callback) to enable VRAM_SR, it will be used for policy to choose between D3Cold-off vs D3Cold-VRAM_SR. Since we have introduced i915 runtime_idle callback. It need to be warranted that Runtime PM Core invokes runtime_idle callback when runtime usages count becomes zero. That requires to use pm_runtime_put instead of pm_runtime_put_autosuspend. Cc: Rodrigo Vivi Cc: Chris Wilson Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_driver.c | 26 +++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 5a9d5529fc90..bbb11c632799 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -1541,6 +1541,31 @@ static int i915_pm_restore(struct device *kdev) return i915_pm_resume(kdev); } +static int intel_runtime_idle(struct device *kdev) +{ + struct drm_i915_private *dev_priv = kdev_to_i915(kdev); + int ret = 1; + + if (!HAS_LMEM_SR(dev_priv)) { + /*TODO: Prepare for D3Cold-Off */ + goto out; + } + + disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + + ret = intel_pm_vram_sr(dev_priv, true); + if (!ret) + drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n"); + + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + +out: + pm_runtime_mark_last_busy(kdev); + pm_runtime_autosuspend(kdev); + + return ret; +} + static int intel_runtime_suspend(struct device *kdev) { struct drm_i915_private *dev_priv = kdev_to_i915(kdev); @@ -1726,6 +1751,7 @@ const struct dev_pm_ops i915_pm_ops = { .restore = i915_pm_restore, /* S0ix (via runtime suspend) event handlers */ + .runtime_idle = intel_runtime_idle, .runtime_suspend = intel_runtime_suspend, .runtime_resume = intel_runtime_resume, }; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6ed5786bcd29..4dade7e8a795 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_runtime_pm_release(rpm, wakelock); - pm_runtime_mark_last_busy(kdev); - pm_runtime_put_autosuspend(kdev); + pm_runtime_put(kdev); } /**