From patchwork Thu May 19 13:59:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 12855125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A047BC433EF for ; Thu, 19 May 2022 14:07:37 +0000 (UTC) Received: from localhost ([::1]:49232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nrgoS-0003bY-P0 for qemu-devel@archiver.kernel.org; Thu, 19 May 2022 10:07:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nrgga-0002Bp-GY; Thu, 19 May 2022 09:59:28 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:40921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nrggV-0001Yw-PU; Thu, 19 May 2022 09:59:28 -0400 Received: by mail-pj1-x1031.google.com with SMTP id nr2-20020a17090b240200b001df2b1bfc40so8863756pjb.5; Thu, 19 May 2022 06:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wbk3Tw473kMoNfK7VGBxPHBOaju8kfs9PwAcUJMVe7Q=; b=YYhyBW9Jd1pG5irwXYTRgNx72WGUUUe+CtPZO9Fz+2g+g2TikIQ3z/ITgvrlYtcuar m15iGHs4lMEtJqUznNJAn6z/lL/CtNs1hSlLZlgVwq4/N/RvT+CID8ozzYv94/yZy6H2 3ws1B8AUEs//f7gACMS1X3obqhypyBVlmV0RdRUy/kEv+b8pBc8yi8nLh6y7kxSqAZyl 3o+hBcblocKEDa1ZdsanborFEzbTGKYE9VlqN44g31YABmU4iM/G3tft8KXnCLb3ZDPt aHPQ1hOqYAaYUthkFRMFCYFHHj+aa81w/v0Y0weflChiWz1l7obN+hvSoJmw9/6OdrmX Y7PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wbk3Tw473kMoNfK7VGBxPHBOaju8kfs9PwAcUJMVe7Q=; b=3aXJt6oF5CudvAsXac76A0Yl/l25earjwlWUutvHZn5UMgiIPEHNKrBWCSZ+c/3avy bFqdJMpl9U++1fj3x+p+rmNVC9VXcmyLZDhHT4o0UFa/7KrDYRf1dE2r3Ir3uen1UAXJ 2QZeQD/CbGUQJYOCbRBhwWBek3JRgecRGMr7+Si0xsVJn76fxq02HG4npTxyaxpJghkP TGniOfZqtJ9J4tDiO0RFMpzgJwPw2N0RWGNkefweqSsXv/7sZJlZ6cpc+zkz/2sqSH2t 5yaV3oWKIp6jpWcxz9F6BbtQmo5R5EODtTK6PcZI6eHUzkwiQRNZqNUhvKeUOewdVdav bf0A== X-Gm-Message-State: AOAM5323GX8MB8OAfGsqlF1yGJrZA6G3m0MVWJBToYNc2nD8FXSAb3oP XMVWyUyq7wLCLYzSxKbviR4T4ohUrEy1uw== X-Google-Smtp-Source: ABdhPJyrvZ54UvMr527Zo7DSwwxwQ3N/U0/q6j5EK8PVaLoHV2Xo3f7F6f4Q6wNOz/KJdYeohU01Vw== X-Received: by 2002:a17:90a:d505:b0:1df:7d0e:a03c with SMTP id t5-20020a17090ad50500b001df7d0ea03cmr6095287pju.170.1652968761850; Thu, 19 May 2022 06:59:21 -0700 (PDT) Received: from bobo.ibm.com ([118.208.131.68]) by smtp.gmail.com with ESMTPSA id l8-20020a17090b078800b001d9927ef1desm5603817pjz.34.2022.05.19.06.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 06:59:21 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH 1/4] target/ppc: Fix eieio memory ordering semantics Date: Thu, 19 May 2022 23:59:05 +1000 Message-Id: <20220519135908.21282-2-npiggin@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220519135908.21282-1-npiggin@gmail.com> References: <20220519135908.21282-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The generated eieio memory ordering semantics do not match the instruction definition in the architecture. Add a big comment to explain this strange instruction and correct the memory ordering behaviour. Signed-off: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/translate.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa34f81c30..eb42f7e459 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3513,7 +3513,32 @@ static void gen_stswx(DisasContext *ctx) /* eieio */ static void gen_eieio(DisasContext *ctx) { - TCGBar bar = TCG_MO_LD_ST; + TCGBar bar = TCG_MO_ALL; + + /* + * eieio has complex semanitcs. It provides memory ordering between + * operations in the set: + * - loads from CI memory. + * - stores to CI memory. + * - stores to WT memory. + * + * It separately also orders memory for operations in the set: + * - stores to cacheble memory. + * + * It also serializes instructions: + * - dcbt and dcbst. + * + * It separately serializes: + * - tlbie and tlbsync. + * + * And separately serializes: + * - slbieg, slbiag, and slbsync. + * + * The end result is that CI memory ordering requires TCG_MO_ALL + * and it is not possible to special-case more relaxed ordering for + * cacheable accesses. TCG_BAR_SC is required to provide this + * serialization. + */ /* * POWER9 has a eieio instruction variant using bit 6 as a hint to From patchwork Thu May 19 13:59:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 12855116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25084C433FE for ; Thu, 19 May 2022 14:06:22 +0000 (UTC) Received: from localhost ([::1]:46186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nrgnF-00011G-7K for qemu-devel@archiver.kernel.org; Thu, 19 May 2022 10:06:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nrgga-0002CD-Kh; Thu, 19 May 2022 09:59:29 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:34659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nrggY-0001ZC-4e; Thu, 19 May 2022 09:59:28 -0400 Received: by mail-pj1-x102d.google.com with SMTP id qe3-20020a17090b4f8300b001dc24e4da73so6090945pjb.1; Thu, 19 May 2022 06:59:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rtvf9wMwhE+cLepszcQA0NiOqfuWl2f+Ach/5N2R/dw=; b=H+kYIJTOgxqDodtRYtZLkwnd5nBhjpmDa71h7ocbtAx91z+JzWpfIx6rAqdG+z+Vy2 mTiqeUXMmKGTjJtOU5r+nbFCFAGaMje+yx/ugGVWL38xqTzzxc1z2garVEfSvtGiCYKa yWyh+tJIH6gQXGJYf4uS8bfShzrX4KPv4/67j1FRRQwHu1HoMjZcTbtP4lz3UXWtNVOK RAyQ8dcJyCnEyZEhuLn+QUf/zU9+NuJX6W821QNprQTtUgPOdny6KRcaMEEVXxzqr8KD +M1jNFNPqe905cGucc1WcBV/t+jKlZP8JUOXbCf6WXSQts6qCw0xjt1Q/rShNXgi2qQj mZQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rtvf9wMwhE+cLepszcQA0NiOqfuWl2f+Ach/5N2R/dw=; b=pGiLtRqiYkJb4td4L4UWABZ2bUj8nKaPHO0I764O4Sq0B9VM1WjgsHorUtKvu2WW32 hjQqzJwVITCKEL4WP/oEQjSOabmONQua1Gp6oeEHrLeMWMzQavh78NWy/Cfgu8Kgq2uH dnD1N1mrAdahVibZ44XdtaKopWH5OTTnMjO9KH+XMOdncshOozpYCCQoUzGImo4O9DN+ MxPCCDSrmiBxBvWqEzkpmBdlOoFyaSqM7x2foRJapl7fo36P9RB+JYIcWnNlzDMiVACr vWpaVgiSL4bARmySwp4VBdELKIS2B12uqdgyZ9aoD3OOi7qZVT65m1yEuKhvDzRfTS9M M/9A== X-Gm-Message-State: AOAM533ZOSewVSkGJoPBBYaJ+AClGwFM6GHYCM7zsTTS3H92vfmO217m PB9yc827v/MKQ9qhxvfE3kEnXY0oysfuKQ== X-Google-Smtp-Source: ABdhPJzgJqrxYrMkdhfmHPoESMAgi9l8ugdk4fkUw0kkWjngUDD9GjIRoImlN3tGl61AQm+z5E7auw== X-Received: by 2002:a17:902:ba97:b0:161:524d:5adb with SMTP id k23-20020a170902ba9700b00161524d5adbmr4971111pls.126.1652968764421; Thu, 19 May 2022 06:59:24 -0700 (PDT) Received: from bobo.ibm.com ([118.208.131.68]) by smtp.gmail.com with ESMTPSA id l8-20020a17090b078800b001d9927ef1desm5603817pjz.34.2022.05.19.06.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 06:59:24 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH 2/4] tcg/ppc: ST_ST memory ordering is not provided with eieio Date: Thu, 19 May 2022 23:59:06 +1000 Message-Id: <20220519135908.21282-3-npiggin@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220519135908.21282-1-npiggin@gmail.com> References: <20220519135908.21282-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" eieio does not provide ordering between stores to CI memory and stores to cacheable memory so it can't be used as a general ST_ST barrier. Reviewed-by: Richard Henderson Signed-of-by: Nicholas Piggin --- tcg/ppc/tcg-target.c.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cfcd121f9c..3ff845d063 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1836,8 +1836,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) a0 &= TCG_MO_ALL; if (a0 == TCG_MO_LD_LD) { insn = LWSYNC; - } else if (a0 == TCG_MO_ST_ST) { - insn = EIEIO; } tcg_out32(s, insn); } From patchwork Thu May 19 13:59:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 12855126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8634C433EF for ; Thu, 19 May 2022 14:09:16 +0000 (UTC) Received: from localhost ([::1]:53146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nrgq3-0006v7-W3 for qemu-devel@archiver.kernel.org; Thu, 19 May 2022 10:09:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nrggc-0002Cl-6I; Thu, 19 May 2022 09:59:30 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:42890) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nrgga-0001ZO-M8; Thu, 19 May 2022 09:59:29 -0400 Received: by mail-pg1-x532.google.com with SMTP id a38so2280106pgl.9; Thu, 19 May 2022 06:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b6UlzvDweSn01XoFdH9Ht5swqfoLlqPhPpji1SjWP0s=; b=Gjc0N3RFAU9sCJ29lrpZdgwDHKB9PwmBxFvmepYnLVCzwpPfn6yCA1YyRb4f7muegA f8Wf13b1/nzW8/BsE9r+LNfTtN4RTfLFsRY/62eYJRtzWlqEObSuBgFSP6zivI5WjOol nHWxR1DPD46kDcUF8BfruJMjiXIrhhXIpGxs4KwLZ30MGOeA4CRVuG9miQT/07ihTZet 5zHrUg2nT+B0Ft5qnCZu9m7hmcLmgyR/FJVKuk6IHfMfQ5CI1i9eGKoYG6j5PcTe6IZb drpS6sr01u2S8hR8H3h7xteVtTI9q6tvDdLIrvS+gznfwWFvtT8dARnTDw7+wZZNT953 V0rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b6UlzvDweSn01XoFdH9Ht5swqfoLlqPhPpji1SjWP0s=; b=3lqCX9saN3MM1TJHUcMhmbyGN5ARZQN5MCIzj3ZTjYtbwwiS4v9JdJtyrIshKkqopm VUkOo9cK1PbeDGdpeeAJafZgr32Gj2kqB139JcLeYFSz8bjCNmeqT9DhH+onTX9e4oI8 i/5IIgf9g9DDHyBLWQByWLQzWO3qHwUcB8z6ZUbSqXf+AlvAngmXF4EE1efZgdHp3+Yc yJbLeSwPk/bOrUiyezCRi7mHAYLP5KabF7FJyuuzrVCIPnr3rd99AYPPx4HqTp9zUJ7h iBxul045PcG5zcy9Smzko83tzIDRAU0nONPSl5YL/YxBXRWZOYTtwRTzjysMnerrOOs8 OnqA== X-Gm-Message-State: AOAM531zYUUS9TEYx2Aa8hUcpEovDAZHNoJoASGBlqKEphLxAvUnAyw+ U2KBn9kOJXy+G0BtxxROuk3TiXMdKaL5DQ== X-Google-Smtp-Source: ABdhPJwU0eG4zY5wgQc70fq0Fqfkxp1ijTEQJfFs1jzs+eAl+8LQKyBqqJG68U1fCE8vC+j/NXVcIg== X-Received: by 2002:a65:5b8a:0:b0:3f5:d3d6:8782 with SMTP id i10-20020a655b8a000000b003f5d3d68782mr4210132pgr.49.1652968766978; Thu, 19 May 2022 06:59:26 -0700 (PDT) Received: from bobo.ibm.com ([118.208.131.68]) by smtp.gmail.com with ESMTPSA id l8-20020a17090b078800b001d9927ef1desm5603817pjz.34.2022.05.19.06.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 06:59:26 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH 3/4] tcg/ppc: Optimize memory ordering generation with lwsync Date: Thu, 19 May 2022 23:59:07 +1000 Message-Id: <20220519135908.21282-4-npiggin@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220519135908.21282-1-npiggin@gmail.com> References: <20220519135908.21282-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=npiggin@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" lwsync orders more than just LD_LD, importantly it matches x86 and s390 default memory ordering. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3ff845d063..c0a5bca34f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1832,11 +1832,14 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, static void tcg_out_mb(TCGContext *s, TCGArg a0) { - uint32_t insn = HWSYNC; - a0 &= TCG_MO_ALL; - if (a0 == TCG_MO_LD_LD) { + uint32_t insn; + + if (a0 & TCG_MO_ST_LD) { + insn = HWSYNC; + } else { insn = LWSYNC; } + tcg_out32(s, insn); } From patchwork Thu May 19 13:59:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 12855127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC602C433F5 for ; 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Thu, 19 May 2022 06:59:29 -0700 (PDT) Received: from bobo.ibm.com ([118.208.131.68]) by smtp.gmail.com with ESMTPSA id l8-20020a17090b078800b001d9927ef1desm5603817pjz.34.2022.05.19.06.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 06:59:29 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH 4/4] target/ppc: Implement lwsync with weaker memory ordering Date: Thu, 19 May 2022 23:59:08 +1000 Message-Id: <20220519135908.21282-5-npiggin@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220519135908.21282-1-npiggin@gmail.com> References: <20220519135908.21282-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=npiggin@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync rather than sync. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 4 +++- target/ppc/cpu_init.c | 13 +++++++------ target/ppc/machine.c | 3 ++- target/ppc/translate.c | 8 +++++++- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 48596cfb25..b9b2536394 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2271,6 +2271,8 @@ enum { PPC2_ISA300 = 0x0000000000080000ULL, /* POWER ISA 3.1 */ PPC2_ISA310 = 0x0000000000100000ULL, + /* lwsync instruction */ + PPC2_MEM_LWSYNC = 0x0000000000200000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2279,7 +2281,7 @@ enum { PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ - PPC2_ISA300 | PPC2_ISA310) + PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC) }; /*****************************************************************************/ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 527ad40fcb..0f891afa04 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5769,7 +5769,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -5846,7 +5846,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_64B | PPC_POPCNTB | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -5985,7 +5985,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | - PPC2_PM_ISA206; + PPC2_PM_ISA206 | PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -6159,7 +6159,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_PM_ISA206; + PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6379,7 +6379,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6596,7 +6596,8 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | + PPC2_MEM_LWSYNC; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 7104a5c67e..a7d9036c09 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -157,7 +157,8 @@ static int cpu_pre_save(void *opaque) | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 - | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; + | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM + | PPC2_MEM_LWSYNC; env->spr[SPR_LR] = env->lr; env->spr[SPR_CTR] = env->ctr; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index eb42f7e459..1d6daa4608 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4041,8 +4041,13 @@ static void gen_stqcx_(DisasContext *ctx) /* sync */ static void gen_sync(DisasContext *ctx) { + TCGBar bar = TCG_MO_ALL; uint32_t l = (ctx->opcode >> 21) & 3; + if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { + bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; + } + /* * We may need to check for a pending TLB flush. * @@ -4054,7 +4059,8 @@ static void gen_sync(DisasContext *ctx) if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { gen_check_tlb_flush(ctx, true); } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + + tcg_gen_mb(bar | TCG_BAR_SC); } /* wait */