From patchwork Fri May 20 09:41:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856562 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D987BC433FE for ; Fri, 20 May 2022 09:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347826AbiETJmZ (ORCPT ); Fri, 20 May 2022 05:42:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347784AbiETJmY (ORCPT ); Fri, 20 May 2022 05:42:24 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DD5C1498DD; Fri, 20 May 2022 02:42:19 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 01CED1C000D; Fri, 20 May 2022 09:42:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039738; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UkENKga2piTorYviraVnH7jRSnL6Crtq1ti3k91LTnI=; b=MXcqokgbm0v4Y8RI0Esjs8gwGTTatIgOEYJUn5SMvIrvX+eK93wM6ZqgsbpBrINwne0rd5 haI5MIShhtjH0CIjGfcZz3lh7iErNnZ58TwwOH52AdiGw5I/Zd1bYxwATSxhFNzGmlOW/A YimePu0l/zgtEXgjnt7Umbm/T7uduNxv+04ztUzKTI+SujAldiRoZL+JRfDAJL8VUrStzH ZaBJpfhZf+Z/FYtz6kCS2gUQXmbVC8Vh0uch5CIvn3ZVIUBvWNKnzEaW/2m865zz6n179H bHW/OdsmW+2Nr3miHOU5rXCT/RSXrD1TlP7g1sEmmqNhzCJW6nhXTtK9139zYg== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Date: Fri, 20 May 2022 11:41:50 +0200 Message-Id: <20220520094155.313784-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Convert Renesas PCI bridge bindings documentation to json-schema. Signed-off-by: Herve Codina Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ---------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++ 2 files changed, 156 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt deleted file mode 100644 index aeba38f0a387..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Renesas AHB to PCI bridge -------------------------- - -This is the bridge used internally to connect the USB controllers to the -AHB. There is one bridge instance per USB port connected to the internal -OHCI and EHCI controllers. - -Required properties: -- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; - "renesas,pci-r8a7743" for the R8A7743 SoC; - "renesas,pci-r8a7744" for the R8A7744 SoC; - "renesas,pci-r8a7745" for the R8A7745 SoC; - "renesas,pci-r8a7790" for the R8A7790 SoC; - "renesas,pci-r8a7791" for the R8A7791 SoC; - "renesas,pci-r8a7793" for the R8A7793 SoC; - "renesas,pci-r8a7794" for the R8A7794 SoC; - "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: A list of physical regions to access the device: the first is - the operational registers for the OHCI/EHCI controllers and the - second is for the bridge configuration and control registers. -- interrupts: interrupt for the device. -- clocks: The reference to the device clock. -- bus-range: The PCI bus number range; as this is a single bus, the range - should be specified as the same value twice. -- #address-cells: must be 3. -- #size-cells: must be 2. -- #interrupt-cells: must be 1. -- interrupt-map: standard property used to define the mapping of the PCI - interrupts to the GIC interrupts. -- interrupt-map-mask: standard property that helps to define the interrupt - mapping. - -Optional properties: -- dma-ranges: a single range for the inbound memory region. If not supplied, - defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the - allowed combinations of address and size. - -Example SoC configuration: - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - reg = <0x0 0xee090000 0x0 0xc00>, - <0x0 0xee080000 0x0 0x1100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - -Example board setup: - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file mode 100644 index 000000000000..494eb975c146 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas AHB to PCI bridge + +maintainers: + - Marek Vasut + - Yoshihiro Shimoda + +description: | + This is the bridge used internally to connect the USB controllers to the + AHB. There is one bridge instance per USB port connected to the internal + OHCI and EHCI controllers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,pci-r8a7742 # RZ/G1H + - renesas,pci-r8a7743 # RZ/G1M + - renesas,pci-r8a7744 # RZ/G1N + - renesas,pci-r8a7745 # RZ/G1E + - renesas,pci-r8a7790 # R-Car H2 + - renesas,pci-r8a7791 # R-Car M2-W + - renesas,pci-r8a7793 # R-Car M2-N + - renesas,pci-r8a7794 # R-Car E2 + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + + reg: + items: + - description: Operational registers for the OHCI/EHCI controllers. + - description: Bridge configuration and control registers. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Device clock + + clock-names: + items: + - const: pclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + bus-range: + description: | + The PCI bus number range; as this is a single bus, the range + should be specified as the same value twice. + + dma-ranges: + description: | + A single range for the inbound memory region. If not supplied, + defaults to 1GiB at 0x40000000. Note there are hardware restrictions on + the allowed combinations of address and size. + maxItems: 1 + +patternProperties: + 'usb@[0-1],0': + type: object + + description: + This a USB controller PCI device + + properties: + reg: + description: + Identify the correct bus, device and function number in the + form . + + items: + minItems: 5 + maxItems: 5 + + phys: + description: + Reference to the USB phy + maxItems: 1 + + phy-names: + maxItems: 1 + + required: + - reg + - phys + - phy-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-map + - interrupt-map-mask + - clocks + - resets + - power-domains + - bus-range + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pci@ee090000 { + compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0xee090000 0xc00>, + <0xee080000 0x1100>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + interrupts = ; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>; + dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; From patchwork Fri May 20 09:41:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856563 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A03FCC433F5 for ; Fri, 20 May 2022 09:42:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347855AbiETJmq (ORCPT ); Fri, 20 May 2022 05:42:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347835AbiETJmn (ORCPT ); Fri, 20 May 2022 05:42:43 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D61701498CD; Fri, 20 May 2022 02:42:23 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id B1EA41C0010; Fri, 20 May 2022 09:42:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039742; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E+wBIttrMTwzTgAXDWmn71GDy198lvRu0VhpdGU+5b4=; b=G5PdQpAu887/K/5/zqHowISzhW2hKkCfg5i1RFUkYyNcz5L/0xkcPBrCQPNsIffVWwzTWM 6YqbOA8H5g+fFXLmJrdtoOsaJ3L2J8NyaIH2CU472W/xlbQuabiiUmfXFvE4GiajitfMas d/lnkZa7oq8igVqkFaHQdrq9oFC20NIpfpyNWJha+OQ9zcs9+ngqJLq9kFvnHOI7bgg/YR JC5pKcbAOVEhWp2pJ3+33UvJMbaCV49UP4tvs0c6uXQDE9UCMVk0sT09T/YXSrlOl+xmqD UKgWFtF1JgDaev9+wBOJEOYNDGSX8ib8wPxYVQrjZRFsY4JeJ1gsB11b8fuNuw== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Date: Fri, 20 May 2022 11:41:51 +0200 Message-Id: <20220520094155.313784-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family. Compared to the R-Car Gen2 family, it needs three clocks instead of one. The 'resets' property for the RZ/N1 family is not required. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 50 +++++++++++++++---- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 494eb975c146..0f18cceba3d5 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -15,9 +15,6 @@ description: | AHB. There is one bridge instance per USB port connected to the internal OHCI and EHCI controllers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - properties: compatible: oneOf: @@ -32,6 +29,10 @@ properties: - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pci-r9a06g032 # RZ/N1D + - const: renesas,pci-rzn1 # RZ/N1 reg: items: @@ -41,13 +42,9 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: Device clock + clocks: true - clock-names: - items: - - const: pclk + clock-names: true resets: maxItems: 1 @@ -106,13 +103,46 @@ required: - interrupt-map - interrupt-map-mask - clocks - - resets - power-domains - bus-range - "#address-cells" - "#size-cells" - "#interrupt-cells" +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,pci-rzn1 + then: + properties: + clocks: + items: + - description: Internal bus clock (AHB) for HOST + - description: Internal bus clock (AHB) Power Management + - description: PCI clock for USB subsystem + clock-names: + items: + - const: hclkh + - const: hclkpm + - const: pciclk + required: + - clock-names + else: + properties: + clocks: + items: + - description: Device clock + clock-names: + items: + - const: pclk + required: + - resets + unevaluatedProperties: false examples: From patchwork Fri May 20 09:41:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856564 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ABCCC43217 for ; Fri, 20 May 2022 09:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347847AbiETJmr (ORCPT ); Fri, 20 May 2022 05:42:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347838AbiETJmo (ORCPT ); Fri, 20 May 2022 05:42:44 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4D441498DC; Fri, 20 May 2022 02:42:27 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 762811C0015; Fri, 20 May 2022 09:42:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039746; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oAMsDVvTiaLCVhxn/JVH0pxqslPhba8QbfwBEnkBzCU=; b=fPbwg++BkIMJuEKso3Lt0SdwKl5MmKSGVZXZ5rtqD6n6lkD3nrzxhYLjv+d/ux4yDR1WjK sQ30s1BBfPgy3GMQ/YzfxwUn+hfjLYt+SAd6udlXE4thk9IllXIwWFndsWEU95vDDiG/yp 1LQZnmYNFJ/tp+XGo4jNAMgxBb0GpeAGRB9podaNxbYae3Xhz8Gb+1D0AhFs5X+JYR7OIj 8CmkGt7DEeu1zJRKmg90Pjt4nEpFDAP2KoY4HZoDS3fmooWpIEDqRAmnKu7FFtwkgjGABV zRkVuZqy9y6zNdhm6Y/aAzxVcuC8V/Yhu66GYdu9S+eS3ubXbzTaw8ayoZNodg== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Date: Fri, 20 May 2022 11:41:52 +0200 Message-Id: <20220520094155.313784-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2 PCI bridge driver. The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one available in the R-Car Gen2 family. Tested with the RZ/N1D (R9A06G032) SOC. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring --- drivers/pci/controller/pci-rcar-gen2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c index 35804ea394fd..839695791757 100644 --- a/drivers/pci/controller/pci-rcar-gen2.c +++ b/drivers/pci/controller/pci-rcar-gen2.c @@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = { { .compatible = "renesas,pci-r8a7791", }, { .compatible = "renesas,pci-r8a7794", }, { .compatible = "renesas,pci-rcar-gen2", }, + { .compatible = "renesas,pci-rzn1", }, { }, }; From patchwork Fri May 20 09:41:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856566 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F68C433F5 for ; Fri, 20 May 2022 09:42:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347851AbiETJmy (ORCPT ); Fri, 20 May 2022 05:42:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347822AbiETJmp (ORCPT ); Fri, 20 May 2022 05:42:45 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA3871498EC; Fri, 20 May 2022 02:42:30 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 491A11C0009; Fri, 20 May 2022 09:42:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039749; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m2syZDhXMNfFFdbui/0S6GoKTUC26/S1VVnx+DdDmc4=; b=hDI9q5RqLcRMF8LHFZG4HuGcYkF0PtBmbohtsdG5azoefpgEoDzGQMn7GWynqA6nYlKz7j J1SiUVk9nGkSdoOtX3DExanNsFe/r4bAKa6IoLwAnbINUlYzcixeMmT/RF8VbcPOfvhGUD +3C7s3gakdl0kcMBZ6OsxWnOY3605X25iNk9OsPCKvVZawadQ+fgZKLWAjgAMzAKWa4WoL ovkGawphsqtbjDtSxzamGdX9D5I5ctIQDtu5dV2OJwhfvf4kPrROYUkPxUdGE5+xgsT2JJ IuG24Nl1ntOV7EqlGcry8DnWbjiKWUsYSi1OUsDe12YiamENkMkJSZms2USuvg== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Date: Fri, 20 May 2022 11:41:53 +0200 Message-Id: <20220520094155.313784-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 20286433d3c6..45944f849190 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -94,6 +94,35 @@ sysctrl: system-controller@4000c000 { clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; }; + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>; From patchwork Fri May 20 09:41:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856567 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B65AEC433FE for ; Fri, 20 May 2022 09:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347838AbiETJmz (ORCPT ); Fri, 20 May 2022 05:42:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347780AbiETJmp (ORCPT ); Fri, 20 May 2022 05:42:45 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FDD3149AA1; Fri, 20 May 2022 02:42:33 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 5340E1C000E; Fri, 20 May 2022 09:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039752; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Psg+kgsloOBducf16xRoRX/ej6BEYer73yn3GaQ0wJU=; b=HU+QOG9KiXtb7LHsmePl4nSulWwQG9taejn6I4SqqkSiinP4e2vJmS9iRCCtLZFC9kncnr fNZ87F9HLjxaUaO+W+Rr/XFWUzen3FSb+oHewlv3+0bQkOuax9c54LVfuVANQAWUMFcM/2 hjI3mDU9oZXZLL56Nb6IWVeD+8r49dC3LP3RGxg7JLXS26seDa1ODvivkVrga4TtmV1TUX ffCnk5ziJsNj89GDn27+hKwcvBemNUCQ6a5zM/VcMmT7ov5TGm8nBHiAXWHLRaJ0k6iIzb 021sAlR+DoTUU/932vy+KqdjMI7wpyDe9VqlFA119M/waHOrsKj7TSjZ/lqfXg== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Date: Fri, 20 May 2022 11:41:54 +0200 Message-Id: <20220520094155.313784-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 45944f849190..8cedc08ba3b9 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -255,4 +255,10 @@ timer { , ; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; }; From patchwork Fri May 20 09:41:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12856565 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8154DC4321E for ; Fri, 20 May 2022 09:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347869AbiETJms (ORCPT ); Fri, 20 May 2022 05:42:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347814AbiETJmq (ORCPT ); Fri, 20 May 2022 05:42:46 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8AA149AA2; Fri, 20 May 2022 02:42:37 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id CE5701C0006; Fri, 20 May 2022 09:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653039755; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3sbzBzsCcC7x9s3vXEvDzSjrA2nDIAK9IYFPPKABIDw=; b=gO27dZkzBfMtegto1vIGkWgZin67UDCXsQ+Lu64r2gl7wQtsk/28Wddo7Ucd1TuSZy14KI qlRkaQ7Nfij+MKOWV/DIEea+7XLbU5d2xhL9mAC7xBJHVNvNNutI1NE0PM7y1Og8s8UEEj 4wfh9YYh1BuzVIi+HBPHaownrza5ytvVXM6zoZ8Voti0HnUe/ir92wu/cUNOzsv0k/1UPk EKz8zp6dAOU8XkDhbmizxx/VNZRiorcSGgjjsRBSa6XJl3fqngMiVBWUBR9niweeP+Jabn ISJ6aOALrO31ER4ub1Sn2iPAyFq26fleAOP4b08Nn7ktCKnYJAQBO5N8HknCjw== From: Herve Codina To: Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= Cc: Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sergey Shtylyov , Thomas Petazzoni , Clement Leger , Miquel Raynal , Herve Codina Subject: [PATCH v6 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Date: Fri, 20 May 2022 11:41:55 +0200 Message-Id: <20220520094155.313784-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520094155.313784-1-herve.codina@bootlin.com> References: <20220520094155.313784-1-herve.codina@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 8cedc08ba3b9..db1e35381d9b 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -121,6 +121,18 @@ pci_usb: pci@40030000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 {