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No functional change intended. Signed-off-by: Roger Pau Monné Acked-by: Jan Beulich --- xen/arch/x86/x86_64/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 9d7f1f818b..24c5067ca2 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -156,7 +156,7 @@ void show_registers(const struct cpu_user_regs *regs) printk("CPU: %d\n", smp_processor_id()); _show_registers(&fault_regs, fault_crs, context, v); - if ( ler_msr && !guest_mode(regs) ) + if ( cpu_has_xen_lbr && !guest_mode(regs) ) { u64 from, to; From patchwork Fri May 20 13:37:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 12856847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA419C433F5 for ; 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Split the logic to enable LBRs into a separate function and expand the logic to also implement support for arch LBRs if model-specific LBRs are not supported. Signed-off-by: Roger Pau Monné --- xen/arch/x86/include/asm/msr-index.h | 18 +++++++++++++ xen/arch/x86/traps.c | 29 ++++++++++++++++++--- xen/include/public/arch-x86/cpufeatureset.h | 1 + 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 3e038db618..7b08e1804b 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -139,6 +139,24 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_ARCH_LBR_CTL 0x000014ce +#define ARCH_LBR_CTL_LBREN (_AC(1, ULL) << 0) +#define ARCH_LBR_CTL_OS (_AC(1, ULL) << 1) +#define ARCH_LBR_CTL_COND (_AC(1, ULL) << 16) +#define ARCH_LBR_CTL_NEAR_REL_JMP (_AC(1, ULL) << 17) +#define ARCH_LBR_CTL_NEAR_IND_JMP (_AC(1, ULL) << 18) +#define ARCH_LBR_CTL_NEAR_REL_CALL (_AC(1, ULL) << 19) +#define ARCH_LBR_CTL_NEAR_IND_CALL (_AC(1, ULL) << 20) +#define ARCH_LBR_CTL_NEAR_RET (_AC(1, ULL) << 21) +#define ARCH_LBR_CTL_OTHER_BRANCH (_AC(1, ULL) << 22) +#define ARCH_LBR_CTL_RECORD_ALL (ARCH_LBR_CTL_COND | \ + ARCH_LBR_CTL_NEAR_REL_JMP | \ + ARCH_LBR_CTL_NEAR_IND_JMP | \ + ARCH_LBR_CTL_NEAR_REL_CALL | \ + ARCH_LBR_CTL_NEAR_IND_CALL | \ + ARCH_LBR_CTL_NEAR_RET | \ + ARCH_LBR_CTL_OTHER_BRANCH) + #define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */ #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */ #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 4c38f6c015..133348d9f9 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1963,6 +1963,29 @@ void do_device_not_available(struct cpu_user_regs *regs) #endif } +static bool enable_lbr(void) +{ + uint64_t debugctl; + + wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); + rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); + if ( !(debugctl & IA32_DEBUGCTLMSR_LBR) ) + { + /* + * CPUs with no model-specific LBRs always return DEBUGCTLMSR.LBR + * == 0, attempt to set arch LBR if available. + */ + if ( !boot_cpu_has(X86_FEATURE_ARCH_LBR) ) + return false; + + /* Note that LASTINT{FROMIP,TOIP} matches LER_{FROM_IP,TO_IP} */ + wrmsrl(MSR_ARCH_LBR_CTL, ARCH_LBR_CTL_LBREN | ARCH_LBR_CTL_OS | + ARCH_LBR_CTL_RECORD_ALL); + } + + return true; +} + void do_debug(struct cpu_user_regs *regs) { unsigned long dr6; @@ -1997,7 +2020,7 @@ void do_debug(struct cpu_user_regs *regs) /* #DB automatically disabled LBR. Reinstate it if debugging Xen. */ if ( cpu_has_xen_lbr ) - wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); + enable_lbr(); if ( !guest_mode(regs) ) { @@ -2179,8 +2202,8 @@ void percpu_traps_init(void) if ( !ler_msr && (ler_msr = calc_ler_msr()) ) setup_force_cpu_cap(X86_FEATURE_XEN_LBR); - if ( cpu_has_xen_lbr ) - wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); + if ( cpu_has_xen_lbr && !enable_lbr() ) + printk(XENLOG_ERR "CPU#%u: failed to enable LBR\n", smp_processor_id()); } void __init init_idt_traps(void) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 9cee4b439e..cd6409f9f3 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -280,6 +280,7 @@ XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! 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Limit the information exposed in PERF_CAPABILITIES to the LBR format only. This is helpful as hardware without model-specific LBRs set format to 0x3f in order to notify the feature is not present. Signed-off-by: Roger Pau Monné --- Seeing as we have never exposed PDCM in CPUID I wonder whether there's something that I'm missing that makes exposing PERF_CAPABILITIES LBR format not as trivial as it looks. --- xen/arch/x86/msr.c | 9 +++++++++ xen/include/public/arch-x86/cpufeatureset.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 01a15857b7..423a795d1d 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -316,6 +316,15 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) *val = 0; break; + case MSR_IA32_PERF_CAPABILITIES: + if ( !cp->basic.pdcm ) + goto gp_fault; + + /* Only report LBR format. */ + rdmsrl(MSR_IA32_PERF_CAPABILITIES, *val); + *val &= MSR_IA32_PERF_CAP_LBR_FORMAT; + break; + case MSR_X2APIC_FIRST ... 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As documented in the Architectural Last Branch Records specification, processors not supporting model-specific LBRs MSR_IA32_DEBUGCTLMSR.LBR has no meaning, and can be written to 0 or 1, but reads will always return 0. Implement support in vmx_msr_write_intercept() by adding generic detection of lack of model-specific LBRs by checking if the LBR format reported in PERF_CAPABILITIES matches 0x3f, which is explicitly listed in the manual as a way to signal lack of model-specific LBRs presence. Signed-off-by: Roger Pau Monné --- Note the indentation change in vmx_msr_write_intercept() as a result of the addition of a new condition is left for a following patch in order to aid readability of the change. --- xen/arch/x86/hvm/vmx/vmx.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index cf428a4849..3f45ac05c6 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3007,6 +3007,8 @@ static const struct lbr_info { { MSR_GM_LASTBRANCH_0_FROM_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO }, { MSR_GM_LASTBRANCH_0_TO_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO }, { 0, 0 } +}, no_lbr[] = { + {0, 0} }; static const struct lbr_info *last_branch_msr_get(void) @@ -3070,6 +3072,21 @@ static const struct lbr_info *last_branch_msr_get(void) /* Goldmont */ case 0x5c: case 0x5f: return gm_lbr; + + default: + if ( cpu_has_pdcm ) + { + uint64_t cap; + + rdmsrl(MSR_IA32_PERF_CAPABILITIES, cap); + if ( (cap & MSR_IA32_PERF_CAP_LBR_FORMAT) == 0x3f ) + /* + * On processors that do not support model-specific LBRs, + * PERF_CAPABILITIES.LBR_FMT will have the value 0x3f. + */ + return no_lbr; + } + break; } break; @@ -3521,6 +3538,8 @@ static int cf_check vmx_msr_write_intercept( return X86EMUL_OKAY; } + if ( lbr->count ) + { for ( ; lbr->count; lbr++ ) { unsigned int i; @@ -3546,6 +3565,10 @@ static int cf_check vmx_msr_write_intercept( v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_TSX; if ( ler_to_fixup_needed ) v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_LER_TO; + } + else + /* No model specific LBRs, ignore DEBUGCTLMSR.LBR. */ + msr_content &= ~IA32_DEBUGCTLMSR_LBR; } __vmwrite(GUEST_IA32_DEBUGCTL, msr_content); From patchwork Fri May 20 13:37:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 12856850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 794E4C433EF for ; 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No functional change. Signed-off-by: Roger Pau Monné Reviewed-by: Kevin Tian --- Feel free to squash onto the previous patch, did separately to aid the readability of the previous change. --- xen/arch/x86/hvm/vmx/vmx.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 3f45ac05c6..ff10b293a4 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3540,31 +3540,31 @@ static int cf_check vmx_msr_write_intercept( if ( lbr->count ) { - for ( ; lbr->count; lbr++ ) - { - unsigned int i; - - for ( i = 0; i < lbr->count; i++ ) + for ( ; lbr->count; lbr++ ) { - int rc = vmx_add_guest_msr(v, lbr->base + i, 0); + unsigned int i; - if ( unlikely(rc) ) + for ( i = 0; i < lbr->count; i++ ) { - gprintk(XENLOG_ERR, - "Guest load/save list error %d\n", rc); - domain_crash(v->domain); - return X86EMUL_OKAY; - } + int rc = vmx_add_guest_msr(v, lbr->base + i, 0); - vmx_clear_msr_intercept(v, lbr->base + i, VMX_MSR_RW); + if ( unlikely(rc) ) + { + gprintk(XENLOG_ERR, + "Guest load/save list error %d\n", rc); + domain_crash(v->domain); + return X86EMUL_OKAY; + } + + vmx_clear_msr_intercept(v, lbr->base + i, VMX_MSR_RW); + } } - } - v->arch.hvm.vmx.lbr_flags |= LBR_MSRS_INSERTED; - if ( lbr_tsx_fixup_needed ) - v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_TSX; - if ( ler_to_fixup_needed ) - v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_LER_TO; + v->arch.hvm.vmx.lbr_flags |= LBR_MSRS_INSERTED; + if ( lbr_tsx_fixup_needed ) + v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_TSX; + if ( ler_to_fixup_needed ) + v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_LER_TO; } else /* No model specific LBRs, ignore DEBUGCTLMSR.LBR. */