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Tue, 24 May 2022 02:51:03 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=58200 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ntR91-0005Sf-4x; Tue, 24 May 2022 02:48:03 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH 1/3] fpga: mgr: Update the status for fpga-manager Date: Tue, 24 May 2022 15:17:43 +0530 Message-ID: <20220524094745.287002-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220524094745.287002-1-nava.manne@xilinx.com> References: <20220524094745.287002-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea1e04e4-d56b-4909-6194-08da3d6af568 X-MS-TrafficTypeDiagnostic: SN6PR02MB5440:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 09:51:21.8026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea1e04e4-d56b-4909-6194-08da3d6af568 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT055.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5440 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch update the below status values for fpga-manager. -Device Initialization error. -Device internal signal error. -All I/Os are placed in High-Z state. -Device start-up sequence error. -Firmware error. Signed-off-by: Nava kishore Manne --- drivers/fpga/fpga-mgr.c | 13 +++++++++++++ include/linux/fpga/fpga-mgr.h | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index a3595ecc3f79..be693fd531ea 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -475,6 +475,19 @@ static ssize_t status_show(struct device *dev, len += sprintf(buf + len, "reconfig IP protocol error\n"); if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR) len += sprintf(buf + len, "reconfig fifo overflow error\n"); + if (status & FPGA_MGR_STATUS_SECURITY_ERR) + len += sprintf(buf + len, "reconfig security error\n"); + if (status & FPGA_MGR_STATUS_DEVICE_INIT_ERR) + len += sprintf(buf + len, "Device Initialization error\n"); + if (status & FPGA_MGR_STATUS_SIGNAL_ERR) + len += sprintf(buf + len, "Device internal signal error\n"); + if (status & FPGA_MGR_STATUS_HIGH_Z_STATE_ERR) + len += sprintf(buf + len, + "All I/Os are placed in High-Z state\n"); + if (status & FPGA_MGR_STATUS_EOS_ERR) + len += sprintf(buf + len, "Device start-up sequence error\n"); + if (status & FPGA_MGR_STATUS_FIRMWARE_REQ_ERR) + len += sprintf(buf + len, "firmware error\n"); return len; } diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 0f9468771bb9..91accba14ba2 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -172,6 +172,12 @@ struct fpga_manager_ops { #define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2) #define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) #define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) +#define FPGA_MGR_STATUS_SECURITY_ERR BIT(5) +#define FPGA_MGR_STATUS_DEVICE_INIT_ERR BIT(6) +#define FPGA_MGR_STATUS_SIGNAL_ERR BIT(7) +#define FPGA_MGR_STATUS_HIGH_Z_STATE_ERR BIT(8) +#define FPGA_MGR_STATUS_EOS_ERR BIT(9) +#define FPGA_MGR_STATUS_FIRMWARE_REQ_ERR BIT(10) /** * struct fpga_manager - fpga manager structure From patchwork Tue May 24 09:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12859920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6894C433F5 for ; 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Tue, 24 May 2022 02:51:03 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=58200 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ntR97-0005Sf-JO; Tue, 24 May 2022 02:48:10 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH 2/3] firmware: xilinx: Add pm api function for PL readback Date: Tue, 24 May 2022 15:17:44 +0530 Message-ID: <20220524094745.287002-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220524094745.287002-1-nava.manne@xilinx.com> References: <20220524094745.287002-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff10153e-f106-4b5e-92ac-08da3d6af069 X-MS-TrafficTypeDiagnostic: CH2PR02MB6343:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 09:51:13.4531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff10153e-f106-4b5e-92ac-08da3d6af069 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0035.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6343 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds PM API for performing PL configuration readback. It provides an interface to the pmufw to readback the FPGA configuration registers as well as configuration data. For more detailed info related to the configuration registers and configuration data refer ug570. Signed-off-by: Nava kishore Manne Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 14 ++++++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7977a494a651..40b99299b662 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -927,6 +927,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); +/** + * zynqmp_pm_fpga_read - Perform the fpga configuration readback + * @reg_numframes: Configuration register offset (or) Number of frames to read + * @phys_address: Physical Address of the buffer + * @readback_type: Type of fpga readback operation + * 0 - FPGA configuration register readback + * 1 - FPGA configuration data readback + * @value: Value to read + * + * This function provides access to xilfpga library to perform + * fpga configuration readback. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_fpga_read(const u32 reg_numframes, const phys_addr_t phys_address, + bool readback_type, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ, reg_numframes, + lower_32_bits(phys_address), + upper_32_bits(phys_address), readback_type, + ret_payload); + *value = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_read); + /** * zynqmp_pm_pinctrl_request - Request Pin from firmware * @pin: Pin number to request diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 1ec73d5352c3..7dc4981345dc 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -61,6 +61,10 @@ #define PM_LOAD_PDI 0x701 #define PDI_SRC_DDR 0xF +/* FPGA readback type */ +#define PM_FPGA_READ_CONFIG_REG 0x0U +#define PM_FPGA_READ_CONFIG_DATA 0x1U + /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration @@ -116,6 +120,7 @@ enum pm_api_id { PM_CLOCK_GETRATE = 42, PM_CLOCK_SETPARENT = 43, PM_CLOCK_GETPARENT = 44, + PM_FPGA_READ = 46, PM_SECURE_AES = 47, PM_FEATURE_CHECK = 63, }; @@ -468,6 +473,8 @@ int zynqmp_pm_feature(const u32 api_id); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); +int zynqmp_pm_fpga_read(const u32 reg_numframes, const phys_addr_t phys_address, + bool readback_type, u32 *value); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -733,6 +740,13 @@ static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, { return -ENODEV; } + +static int zynqmp_pm_fpga_read(const u32 reg_numframes, + const phys_addr_t phys_address, + bool readback_type, u32 *value); +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Tue May 24 09:47:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12859919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B618C433EF for ; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 09:51:08.6096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23a2f9bf-d073-428d-21bf-08da3d6aed84 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0035.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6304 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds status interface for zynqmp-fpga, It's a read only interface which allows the user to get the PL status. Usage: To read the PL configuration status cat /sys/class/fpga_manager//status Signed-off-by: Nava kishore Manne --- drivers/fpga/zynqmp-fpga.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index c60f20949c47..07c7b7326726 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -14,6 +14,19 @@ /* Constant Definitions */ #define IXR_FPGA_DONE_MASK BIT(3) +#define READ_DMA_SIZE 256U + +/* Error Register */ +#define IXR_FPGA_ERR_CRC_ERR BIT(0) +#define IXR_FPGA_ERR_SECURITY_ERR BIT(16) + +/* Signal Status Register. For details refer ug570 */ +#define IXR_FPGA_END_OF_STARTUP BIT(4) +#define IXR_FPGA_GST_CFG_B BIT(5) +#define IXR_FPGA_INIT_B_INTERNAL BIT(11) +#define IXR_FPGA_DONE_INTERNAL_SIGNAL BIT(13) + +#define IXR_FPGA_CONFIG_STAT_OFFSET 7U /** * struct zynqmp_fpga_priv - Private data structure @@ -77,8 +90,47 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) return FPGA_MGR_STATE_UNKNOWN; } +static u64 zynqmp_fpga_ops_status(struct fpga_manager *mgr) +{ + unsigned int *buf, reg_val; + dma_addr_t dma_addr; + u64 status = 0; + int ret; + + buf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE, + &dma_addr, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = zynqmp_pm_fpga_read(IXR_FPGA_CONFIG_STAT_OFFSET, dma_addr, + PM_FPGA_READ_CONFIG_REG, ®_val); + if (ret) { + status = FPGA_MGR_STATUS_FIRMWARE_REQ_ERR; + goto free_dmabuf; + } + + if (reg_val & IXR_FPGA_ERR_CRC_ERR) + status |= FPGA_MGR_STATUS_CRC_ERR; + if (reg_val & IXR_FPGA_ERR_SECURITY_ERR) + status |= FPGA_MGR_STATUS_SECURITY_ERR; + if (!(reg_val & IXR_FPGA_INIT_B_INTERNAL)) + status |= FPGA_MGR_STATUS_DEVICE_INIT_ERR; + if (!(reg_val & IXR_FPGA_DONE_INTERNAL_SIGNAL)) + status |= FPGA_MGR_STATUS_SIGNAL_ERR; + if (!(reg_val & IXR_FPGA_GST_CFG_B)) + status |= FPGA_MGR_STATUS_HIGH_Z_STATE_ERR; + if (!(reg_val & IXR_FPGA_END_OF_STARTUP)) + status |= FPGA_MGR_STATUS_EOS_ERR; + +free_dmabuf: + dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf, dma_addr); + + return status; +} + static const struct fpga_manager_ops zynqmp_fpga_ops = { .state = zynqmp_fpga_ops_state, + .status = zynqmp_fpga_ops_status, .write_init = zynqmp_fpga_ops_write_init, .write = zynqmp_fpga_ops_write, };