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Wed, 25 May 2022 12:10:50 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 01/12] MIPS: CPS: Add a couple of multi-cluster utility functions Date: Wed, 25 May 2022 14:10:19 +0200 Message-Id: <20220525121030.16054-2-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d27d64dd-5084-4509-a430-08da3e479b89 X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This is useful because in some cases behaviour can be more optimal taking this knowledge into account. The means by which we check this is dependent upon the way we probe CPUs & assign their numbers, so keeping this knowledge confined here in arch/mips/ seems appropriate. - mips_cps_first_online_in_cluster() allows its caller to determine whether it is running upon the first CPU online within its cluster. This information is useful in cases where some cluster-wide configuration may need to occur, but should not be repeated if another CPU in the cluster is already online. Similarly to the above this is determined based upon knowledge of CPU numbering so it makes sense to keep that knowledge in arch/mips/. The function is defined in mips-cm.c rather than in asm/mips-cps.h in order to allow us to use asm/cpu-info.h & linux/smp.h without encountering an include nightmare. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h index c077e8d100f5..fa71cf3a25d7 100644 --- a/arch/mips/include/asm/mips-cps.h +++ b/arch/mips/include/asm/mips-cps.h @@ -228,4 +228,42 @@ static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int co return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1); } +/** + * mips_cps_multicluster_cpus() - Detect whether CPUs are in multiple clusters + * + * Determine whether the system includes CPUs in multiple clusters - ie. + * whether we can treat the system as single or multi-cluster as far as CPUs + * are concerned. Note that this is slightly different to simply checking + * whether multiple clusters are present - it is possible for there to be + * clusters which contain no CPUs, which this function will effectively ignore. + * + * Returns true if CPUs are spread across multiple clusters, else false. + */ +static inline bool mips_cps_multicluster_cpus(void) +{ + unsigned int first_cl, last_cl; + + /* + * CPUs are numbered sequentially by cluster - ie. CPUs 0..X will be in + * cluster 0, CPUs X+1..Y in cluster 1, CPUs Y+1..Z in cluster 2 etc. + * + * Thus we can detect multiple clusters trivially by checking whether + * the first & last CPUs belong to the same cluster. + */ + first_cl = cpu_cluster(&boot_cpu_data); + last_cl = cpu_cluster(&cpu_data[nr_cpu_ids - 1]); + return first_cl != last_cl; +} + +/** + * mips_cps_first_online_in_cluster() - Detect if CPU is first online in cluster + * + * Determine whether the local CPU is the first to be brought online in its + * cluster - that is, whether there are any other online CPUs in the local + * cluster. + * + * Returns true if this CPU is first online, else false. + */ +extern unsigned int mips_cps_first_online_in_cluster(void); + #endif /* __MIPS_ASM_MIPS_CPS_H__ */ diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index b4f7d950c846..5b843c2ff077 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -513,3 +513,40 @@ void mips_cm_error_report(void) /* reprime cause register */ write_gcr_error_cause(cm_error); } + +unsigned int mips_cps_first_online_in_cluster(void) +{ + unsigned int local_cl; + int i; + + local_cl = cpu_cluster(¤t_cpu_data); + + /* + * We rely upon knowledge that CPUs are numbered sequentially by + * cluster - ie. CPUs 0..X will be in cluster 0, CPUs X+1..Y in cluster + * 1, CPUs Y+1..Z in cluster 2 etc. This means that CPUs in the same + * cluster will immediately precede or follow one another. + * + * First we scan backwards, until we find an online CPU in the cluster + * or we move on to another cluster. + */ + for (i = smp_processor_id() - 1; i >= 0; i--) { + if (cpu_cluster(&cpu_data[i]) != local_cl) + break; + if (!cpu_online(i)) + continue; + return false; + } + + /* Then do the same for higher numbered CPUs */ + for (i = smp_processor_id() + 1; i < nr_cpu_ids; i++) { + if (cpu_cluster(&cpu_data[i]) != local_cl) + break; + if (!cpu_online(i)) + continue; + return false; + } + + /* We found no online CPUs in the local cluster */ + return true; +} From patchwork Wed May 25 12:10:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC8C4C433EF for ; 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This patch generates accessor functions for shared/global registers accessed via the redirect block, with "redir_" inserted after "gic_" in their names. For example the accessor function: read_gic_config() ...accesses the GIC_CONFIG register of the GIC in the local cluster. With this patch a new function: read_gic_redir_config() ...is added which accesses the GIC_CONFIG register of the GIC in whichever cluster the GCR_CL_REDIRECT register is configured to access. This mirrors the similar redirect block accessors already provided for the CM & CPC. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Reviewed-by: Jiaxun Yang diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 084cac1c5ea2..fd9da5e3beaa 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -28,11 +28,13 @@ extern void __iomem *mips_gic_base; /* For read-only shared registers */ #define GIC_ACCESSOR_RO(sz, off, name) \ - CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) + CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \ + CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name) /* For read-write shared registers */ #define GIC_ACCESSOR_RW(sz, off, name) \ - CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) + CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \ + CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name) /* For read-only local registers */ #define GIC_VX_ACCESSOR_RO(sz, off, name) \ @@ -45,7 +47,7 @@ extern void __iomem *mips_gic_base; CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name) /* For read-only shared per-interrupt registers */ -#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ +#define _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ static inline void __iomem *addr_gic_##name(unsigned int intr) \ { \ return mips_gic_base + (off) + (intr * (stride)); \ @@ -58,8 +60,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \ } /* For read-write shared per-interrupt registers */ -#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ +#define _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ \ static inline void write_gic_##name(unsigned int intr, \ unsigned int val) \ @@ -68,22 +70,30 @@ static inline void write_gic_##name(unsigned int intr, \ __raw_writel(val, addr_gic_##name(intr)); \ } +#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name) + +#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name) + /* For read-only local per-interrupt registers */ #define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ stride, vl_##name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ stride, vo_##name) /* For read-write local per-interrupt registers */ #define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ stride, vl_##name) \ - GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ stride, vo_##name) /* For read-only shared bit-per-interrupt registers */ -#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \ +#define _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ static inline void __iomem *addr_gic_##name(void) \ { \ return mips_gic_base + (off); \ @@ -106,8 +116,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \ } /* For read-write shared bit-per-interrupt registers */ -#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \ - GIC_ACCESSOR_RO_INTR_BIT(off, name) \ +#define _GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ \ static inline void write_gic_##name(unsigned int intr) \ { \ @@ -146,6 +156,14 @@ static inline void change_gic_##name(unsigned int intr, \ } \ } +#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name) + +#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RW_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name) + /* For read-only local bit-per-interrupt registers */ #define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \ GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ @@ -155,10 +173,10 @@ static inline void change_gic_##name(unsigned int intr, \ /* For read-write local bit-per-interrupt registers */ #define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \ - GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ - vl_##name) \ - GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ - vo_##name) + _GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ + vl_##name) \ + _GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ + vo_##name) /* GIC_SH_CONFIG - Information about the GIC configuration */ GIC_ACCESSOR_RW(32, 0x000, config) From patchwork Wed May 25 12:10:21 2022 Content-Type: text/plain; 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Wed, 25 May 2022 12:10:51 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Date: Wed, 25 May 2022 14:10:21 +0200 Message-Id: <20220525121030.16054-4-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2d3f9628-bbb2-441a-d420-08da3e479c3e X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4dXjUw2CzNK91TdbR7GXUUmDCxjcD7k0syb/3+Q16ZdXfEqQGzT99k7HCmV80nQb+2Yg8wjIIr9dvtH7XxVJqd4g6124RosfJ5Ui9LKYabXBQKvNLOwvETwz/4nLIik+Ysynsc5Dr7lxzLTpKHEzDTgoj7kEEI6Ha5MUDbmpqgoW3hub4VXPn8xhvhKIs6uZBF7lS5P0QkkxVYz/o/r0WECVDp/FYEZdtrPvepss2pXs3Xu0tWiixPxeA6zAe9aBY2NeczpL//omFkQRX0EaxunUwgesyOl9dZCvTU0NZqEtRGbt8XqvMK/jpQwKlKkdrdaxafdCTJd8Re8fae2Q+ZJf9ZYP90aSOQENEhmV4MnUSj7OlKGPYckA3uW4Ej7z6opIVP1+58irpIy0oxi9vuT4lXaf7H0Ykq5Db2jgEYxQ9hHHb7g57SaCtMgzga6eKvBFHxpE4T83VKxN71/uBsdpxo9h7b6sqkIWYEFMm8iy23Z43EKnuJIkTxqybluP6XbPCxZe6L3zyWPuiPqSFRdqRb34B25rzzSpkvmA9N5Bsg43Pu7TUKp9GESAGqdXqZVzpYYmD1gL4j1fFqPx5RedYwTdO5G+B18jutXmbXNnHrw2wUeujL0c/jOuAh6ucdtyq2Qvek9Yr6R3ktou+/E0mRx0sbpKvyLhXPt3jAfISI+vNBo0xuxMxEUJAfBL3KWj+JZC17vjYEfrtaN7pV8dmrWi2aUrk4dUp1FZY+7EVPYe8j6f1Ru/Bi0lL/5AiYCpINpb6AQQ6Vd/fm9mMvFeMVeNNuNrlA1jIxIXj5tT2s3lhQxfzsodb1NjyGPYyRuQonqXSa0XsDJCap+BZ3q45MAlnBV1NHlELFd6zunK0JdO0coGKzJmP1dLqKKOoW1km30M2JM1mG63cnPhVQ53T3VLtEm4NKb127LZWfIK7gHQwTojN9N6UcTRxh++tzXhwY/TnrwYF/d6BKt5tXZmY1Bx8Wc47NlcKtCdcoIl3llhSNTKMR42b5Yhd5Y5zX+CWqs5dPZEwTN3s0Yd9MKh3VeTC5Fm/58zfppRtBq4rDUbZvuwMiecV+NndgLQIKKM/oBVhmCqM4EskgMKpjZSWft4CPq5YoHLTsVhZ6lb6xXcZNpGSjfMd07E/Nm6YNwbjNjFWViKvbzOIYuBFjXi4pqYQJ4wiippu62CkBzYHQbL3MdABO2fyJ44/vJIVtrBLxnfKyyaDlGSSqO7k6BLW7g/PFIcF9NCeXOwDtCLh0futGjxghFw0bikdJzmp6F1oRam80JvysKm+Yu7J49YF5xbKd0Cncyuxw2VF5KVp/RzPjHrhZYlcnDzZql5J75KKaUWbVhHoiRzvahRMFo9nI2rbz+spdDXZA5x40Mws/fPuarPbr59FflGSKbBFdG4IJFHgMXsXwz+k9ipy1RXdNGOoi77W+PP7l+pzPa14HHlh0bZMKYUq0iaU/eHIFacz2UWTjA4dz4loEPDWU4MsYgLOnWNGTuTlPXVevGXdin52VHmb5dB7Vbncjp/r3QZijNL24XkttKzExuVEriRoJZcymjdbk5yaqczc8LKLFx+KEWCiDh4H4cHco23wUAVpnOjf/pEkCaBKBf7jCO6ZnFIV1XJLlwZrY+db/dMTJagYjPfC+SbV0VYLwOHd5CaBJu3H4HwfMwnoWen3zdkqIdWCeAhlZMIaEtsPK/HuMs94aYcdCtNF9SCuHHpAvhlIsh3ceC7ARKNnwbzEkJkCN0Ek2b1qsZmzpnq7MY= X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d3f9628-bbb2-441a-d420-08da3e479c3e X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:51.3184 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: opIP3kUlevw0scumphav6/gVQaLnWuFJx4GV3cP9yB6OleBEeXJ5DLahiwaZs/rHYPd7DVPXDevCziC55wJ+WdTSXZb64QvjU6IhwtXJWb4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7859 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton A few pieces of code in the MIPS GIC driver operate on the GIC local register block for each online CPU, accessing each via the GIC's other/redirect register block. This patch abstracts the process of iterating over online CPUs & configuring the other/redirect region to access their registers through a new gic_with_each_online_cpu() macro. This simplifies users of the new macro slightly, and more importantly prepares us for handling multi-cluster systems where the register configuration will be done via the CM's GCR_CL_REDIRECT register. By abstracting all other/redirect block configuration through this macro, and the __gic_with_next_online_cpu() function which backs it, users will trivially gain support for multi-cluster when it is implemented in __gic_with_next_online_cpu(). Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ff89b36267dd..4872bebe24cf 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -65,6 +65,45 @@ static struct gic_all_vpes_chip_data { bool mask; } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; +static int __gic_with_next_online_cpu(int prev) +{ + unsigned int cpu; + + /* Discover the next online CPU */ + cpu = cpumask_next(prev, cpu_online_mask); + + /* If there isn't one, we're done */ + if (cpu >= nr_cpu_ids) + return cpu; + + /* + * Lock access to the next CPU's GIC local register block. + * + * In the single cluster case we simply set GIC_VL_OTHER. The caller + * holds gic_lock so nothing can clobber the value we write. + */ + write_gic_vl_other(mips_cm_vp_id(cpu)); + + return cpu; +} + +/** + * gic_with_each_online_cpu() - Iterate over online CPUs, access local registers + * @cpu: An integer variable to hold the current CPU number + * + * Iterate over online CPUs & configure the other/redirect register region to + * access each CPUs GIC local register block, which can be accessed from the + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or + * their derivatives. + * + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER + * cannot be clobbered. + */ +#define gic_with_each_online_cpu(cpu) \ + for ((cpu) = __gic_with_next_online_cpu(-1); \ + (cpu) = __gic_with_next_online_cpu(cpu), \ + (cpu) < nr_cpu_ids;) + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -357,10 +396,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) cd->mask = false; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_rmask(BIT(intr)); - } spin_unlock_irqrestore(&gic_lock, flags); } @@ -375,10 +412,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) cd->mask = true; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_smask(BIT(intr)); - } spin_unlock_irqrestore(&gic_lock, flags); } @@ -532,10 +567,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, return -EPERM; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_map(mips_gic_vx_map_reg(intr), map); - } spin_unlock_irqrestore(&gic_lock, flags); return 0; From patchwork Wed May 25 12:10:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ACF7C433F5 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0K9VHDF6FpTfwGoCsg5siTT/GqFNEdbZugTz4gcTBd2YNggyVpjyIR4TzRFqiyB9o1djySB0KwWcdntqRiq3ql1NC/QPSMMNsWBwSOFPWQGik0p+U6ErkYSAGGMWK7GBoip3XWqhy4C7kLKwwjysg0P1n6Uh2iVYTWEFPU0khhGbls5NGW4PtpH6w6ZlMDNj6WakvFGGFF/PFPX9vM1lrCrfOpkCs8+VryLZPYwQlGUCbgDQQzAQFq2RKQTl4Ic+MCBiOggzEM0BxcHlhIvfSuJOVSc7iS21PxXMWntSfN0rkBdsBFDTT1dwqc3d/AIIlQTxdzqHY4YoWaRmOhQY1xclutJDBbUUX4hkx4XME6s8zKFZC8cF42Zi1tlspe+TStlO/Mt+E9QwpMpeEYpg/tw5rdInuBlUrSexA+IML6K3f3FXcgPRTizvCt1TUERWPs4bcj4d9GBR7p0Q+ik6MfzmQfDvHh/Yh3wCCO9bY8BJiUz/210VNijqWUiBMivmNJdBVR6X6JjZExwGsJ75MN2Ebic+XvuS6UArgJeib36lJ/dp+j+yhVmN7+9qxv4pZnwupSbZ6EeTzLZ1ACM2vSZm/ph7hoaVGwHm3oT/vd7gNZefkT+E7FmRWFkTkOMVoEnnsfpgsnX0WUrzAqCsrUVINPNCagQZjZmUsKd+2rH/yXtV6zKgl+WCbfN0UrCiUgQedE1GrZaaTqf9f9A/chiPdjYoPlsUZgCJgm6BBa2vf1H0ulK0WK1B9OovuwnA78A5EZ32P9UfiVkroXTFFkNXG6Iq7tC80TAAJjeC3w0vztYTYFPLNxcVYNpBCvHszcugMh3ifoNbDs26lvDqHs12w/sJVaZVAorKHkbfeQ1lcmGb+OkP4jz/7wNlDW0KmxtrHPgkx+uxuzNSN1fIcKc4uTT7Ibcop4R9q+x4/2l3gxUk4GYLSi/RUZPA+FA3dHs4WmeO5aMMO88HfKbdYDiPdnRMeJcFT2AZAo6q75pSyNbA06nAqXHHJifldnt7BKN9TDbx67z2mXjeQNGgzGEu048ampjyhlVGuCKrbaLU29S3AJdA/tLiqdlAHAbOfkjQy2n5MOR5D+NExde/FGeETzdzmgmwxd+Y1JAlVaRbo15bhBKq+EzsSV/IsoUcMvD6dABPOaE/0/VASgA/PWZ2gJiJC+FvLnCSdlk5eOuqvjmMlDIkythVhMZ6TR1HTaemEA6gehD1yRCFx1jnzgzeRUp92dyZOFvz/2kHNjtpmMev3inQ+TahnvXyi3bYkfPSSvgMmCPxDmGJOaJ9LY7GgMKDInNpbVG3PV+4fTXoK2aURseM1bM3t8899eRPgJMzg7haILeUYIEzcsdgTQO9RmqD1rD3ihpRI4pEjeTCt7pevFaOIc3uL6dJwHYiRBvqiCdylfM933JNRWIKPdO44JD5gQ39OTyzT7EoEiKI200ZfaVAk0N8KZ1Zzy2QyxVGupHDS3QrAGSsIXxYoowqHYphf5on7rgjCdpnZ9EjzWr8cT/UQ80yqWwkfiYfSNyy3nRyTJO7nfJbhCEwKjyuvX4j79PeGoYi5eLfzBiAt0RyNZzwLZI7edkKT0fAZw9idQr0Dz0gZWXXbpOYHCqoDmpD16X0kTEL/3/abfc2VOiafkF9kxLVhno630YqaSgm/nEls6cc78ThhH3EwGHOjk2HOOswxpOfJ8JvRkMCJkfdUrzv/MPcggMnMHUe74Lg1U2QyHYfFDddNLJ0CenHArIuifEONmYVtjGgS6s= X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 08553885-e854-4e3d-f188-08da3e479ce0 X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:52.7090 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5Bx+8/xxVBNsTSOxOlQiiGCwo8JlB/jkgGf3GFHsJzGAyTgjw/cTVCvyEpDBLC+/j45yHpX1pNFmQme46LawHJmEs6OAjUWg3vfUduRFutY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7859 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton Introduce support for multi-cluster GIC register access in __gic_with_next_online_cpu(), and therefore in its user gic_with_each_online_cpu(). We access registers in remote clusters using the CM's GCR_CL_REDIRECT register, and so here we delegate to mips_cm_lock_other() in order to configure this access. With this done, users of gic_with_each_online_cpu() gain support for multi-cluster with no further changes. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 4872bebe24cf..89a3c6d04e09 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -69,6 +69,20 @@ static int __gic_with_next_online_cpu(int prev) { unsigned int cpu; + /* + * Unlock access to the previous CPU's GIC local register block. + * + * Delegate to the CM locking code in the multi-cluster case, since + * other clusters can only be accessed using GCR_CL_REDIRECT. + * + * In the single cluster case we don't need to do anything; the caller + * is responsible for maintaining gic_lock & nothing should be + * expecting any particular value of GIC_VL_OTHER so we can leave it + * as-is. + */ + if ((prev != -1) && mips_cps_multicluster_cpus()) + mips_cm_unlock_other(); + /* Discover the next online CPU */ cpu = cpumask_next(prev, cpu_online_mask); @@ -79,10 +93,16 @@ static int __gic_with_next_online_cpu(int prev) /* * Lock access to the next CPU's GIC local register block. * + * Delegate to the CM locking code in the multi-cluster case, since + * other clusters can only be accessed using GCR_CL_REDIRECT. + * * In the single cluster case we simply set GIC_VL_OTHER. The caller * holds gic_lock so nothing can clobber the value we write. */ - write_gic_vl_other(mips_cm_vp_id(cpu)); + if (mips_cps_multicluster_cpus()) + mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL); + else + write_gic_vl_other(mips_cm_vp_id(cpu)); return cpu; } From patchwork Wed May 25 12:10:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73E0AC433EF for ; Wed, 25 May 2022 12:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243458AbiEYMLW (ORCPT ); Wed, 25 May 2022 08:11:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243212AbiEYMLA (ORCPT ); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LlYHyZ1v1HwtfWIbgk4O0y6Nh9wX04waqdT1zP5YL7Ea5j5/PpHNCY1K9wX1nFPhH1bqFEG7r9u0JVjaehudaAIq61/vbC4161RpMe/sFBGe6i6WAnRO2xMh3euAj6HRegMx0VRWkWWpfkOD5NxTLmGSam0PinbqaOWVHbpFjWggG2BHR9MEH3OtGfY0lms7imnucpKa/BufHdQcUMPbhMQG2dBas/RQOoZGNFqujK0aHWbbUXQkp7oD+gtEkCerHOogc3p/fcMyYhm9YyuqlH+FPYOPv+Ti4fZhc7A3YMHVQAVd0n2mGMjvOlPtwatMiTYXE1s/kuG/goQaFyrQ+BjRtCPlx7tdPCbgg1W/nRpEVObEjw3vb5pXj5j+ZuN7YBCSMtToy1sIbKJbBxDJxJgQbpr2gI88GSFPLULw1Yp9k+FguDvp+A0y9QJH2CyeimkLoaHX0lhedHolQ828Cwrqc6pY2CkSc9Y5gY8BwmTgs/r2Z/AB8bZ/rX/kkh5HnY/FFbER/0IdRLhdDj78Uun80xgPZRvXxhK7+gQQRfH8zvXSR6aq71jlnqqr1CN6mxryY+ujeCOaghYCzKTW5RDOE3cTxoIS9X6+RUoyQPunPrSdJ4SHxkqLo0mfv1n/UQQdr4cvip+usYpnh7rp0tAEc5bpFpWY0oyWWdf9vND2VIHkg93QjGlSme0QmxFhggMljhZWQU0iHxh5FHAIy/4l6jBRDCFTkIS/kpakjASrl1Poo8WLphNa7ieXe2YDAmtbKKFI+phhQKEJn0unEy1LZ+peDkidTL+nr3lnVAhJyqzr/T+uVNPI8VJJhdCCgItkHdbvgi+DDav4ZPmx9/2O+z7C4njvOEIeHpQ+taE8ozbEqDI649F4rvr32iy33pz+9I/JOp1Wr1k70XY3eYzMMgvLfDaBXBlS8ZvH36L13OWWkdNiI4CgXBHmyB5EurS4HU+/j2/YsqCcmZdL3y2XBS3+IaY2dFQo57yTkMUnhEbbJD24SF3ykAZDNsE0ysHc3ApemVzqe92OigGbTnpUrJJhoCbWNW4i3RU6x0a0U0AEgIlZnx/Mm9Sb4dnc+nl7dmm/OX5Du5VttGZdbhC3DBYvzQGtsVRg+GQppB5HMgNQH1oNSzfM/BDggwJKQ4A+9VGZdqPzeuuGz8uhnaOZ86w2MuXlYCB0gb/rYC++rQCOPUF1AVeCgR5M/l3VBLo4F3wgzScPp54iSZMQjaRdFt3/H/oe7Mb9uUe32Vc7H3MZ79Ojdo0E8g6vAQdzF5UzUNGChtJVx/PzZ3O1gtC41Mup4oyrWh1+1OQUjrHmHkSWxYDPW70tRVzsFQySzF2c6iiLlrCrKiDF9u/m4wkdL2fXVIWoKYjHas23csl5IJ4z5sZJzCzUBdzmhpD3ysfcQcivMhvnsqk2ys/6YU3wzsCFgz1AqW5svJ2xn/5fWpAA/Kbyk85M2SC7bR03sKXu9wb1DVksMivfPiuadPZWSaQVlxcZNIWOwXbxTSLthXR08b1TC51z1RYnS+HILByY3i9nGS1gCJ/VglO2NCs7TWFicvETijK5p5HAjNQACy8yi0zMHBRT18/1QdwEvWXq9b4pc7gs/urDeHUVF3pVyCAdweQAYeOF46+mUzuTxPAUi7cY4Vu/6H1CIfn5bOE6NaZuChn/WghrzNWZb2pUHc9MeaFa13i1sh341fJOXt8uXmDdI+p+K+eRcBMmw3+PDcSo2+LsDhcY0ECw1iNDmQJhPKTT8sCIjBFwTQk= X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 039eb4ac-a435-4a41-5ad5-08da3e479db0 X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:53.6620 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TFHHOhRT+y+o5TQPRncnXPjs4xbVq2zNhjHG5k0xHW6OeEJQKnqUHEjdMrPtXHShvUPyf/yy36waoKBnmwEVcWPNc01o7rEnGfyzV93nUWo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7859 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Chao-ying Fu In multi-cluster MIPS I6500 systems we have a GIC per cluster. The default shared interrupt setup that we configure in gic_of_init() will only apply to the GIC in the cluster containing the boot CPU, leaving the GICs of other clusters unconfigured. Similarly configure other clusters here. Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 89a3c6d04e09..f692392666a2 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -741,7 +741,7 @@ static int gic_cpu_startup(unsigned int cpu) static int __init gic_of_init(struct device_node *node, struct device_node *parent) { - unsigned int cpu_vec, i, gicconfig, v[2], num_ipis; + unsigned int cpu_vec, i, gicconfig, v[2], num_ipis, cl, nclusters; unsigned long reserved; phys_addr_t gic_base; struct resource res; @@ -860,11 +860,30 @@ static int __init gic_of_init(struct device_node *node, board_bind_eic_interrupt = &gic_bind_eic_interrupt; - /* Setup defaults */ - for (i = 0; i < gic_shared_intrs; i++) { - change_gic_pol(i, GIC_POL_ACTIVE_HIGH); - change_gic_trig(i, GIC_TRIG_LEVEL); - write_gic_rmask(i); + /* + * Initialise each cluster's GIC shared registers to sane default + * values. + * Otherwise, the IPI set up will be erased if we move code + * to gic_cpu_startup for each cpu. + */ + nclusters = mips_cps_numclusters(); + for (cl = 0; cl < nclusters; cl++) { + if (cl == cpu_cluster(¤t_cpu_data)) { + for (i = 0; i < gic_shared_intrs; i++) { + change_gic_pol(i, GIC_POL_ACTIVE_HIGH); + change_gic_trig(i, GIC_TRIG_LEVEL); + write_gic_rmask(i); + } + } else { + mips_cm_lock_other(cl, 0, 0, + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + for (i = 0; i < gic_shared_intrs; i++) { + change_gic_redir_pol(i, GIC_POL_ACTIVE_HIGH); + change_gic_redir_trig(i, GIC_TRIG_LEVEL); + write_gic_redir_rmask(i); + } + mips_cm_unlock_other(); + } } return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, From patchwork Wed May 25 12:10:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE035C433F5 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6FIYGFEDSnU06dGa/+h2nYamzpKyBK69t4E6wqf21YDyZLQMO8Cw/DezJqLYs/lJGN3vRAfS91v83zrFqVSp9UBmzSKqxjGxxMTyKYuQ88GFsKwjdvotJGSCpc+JoIsKB5nN6zLRZCf60T6DInx1NfP7tysa0+yha2BjLf/n8pcflF5wzhZ/QJOktwc4OCSVds+UpO0LK7S/3kU3wqnryvOUvwkGqXsVYlQDg4Ij+ndAIHFfPmJdfZvA+tOJd3riXJ90PlYL7zp7tT4ZExPAu0ycKsglAj0ymTYSrGjUgzcH2fNcOHmHyqtkaDxZFeG/cdQtlkVJhaMJFA+37FkfUIy4DGCngLrlSHzGyJGBSRWqWooQgY9HBMLytzUNiZ6ylZwZFQHgjKIkOG4+yhha/Tfu6luvlqpcfyoZuNb0Whm4XVnv9uGln9NolnkaimnmImj2B6FgoOAWvdFgfD6+iQwfGrws76zs+S7I/+qy0qjihKzkW9YIvKLt4PgxUZeX4NR2n6cNwqnKqiAJtf/4Nce8vC/cjGY39bBTmWu5AqSGr8xnxURKK4mPpTiNJrAf4/o7bfd1al8iWGJsdB/sN4fCMpvH9OqVTsW0/SDSTIcdJ8kinyIacaK3op/a6zVeXZoT5+Hm1ab09UwWCHNAeNtAn4ddi/DuBoLluc6dwdZxFwCmMS2N0C3dzWLO61PcXuI+99WStjuzSCJNovq91+LJCt0uB7W+a1lIKXd6+OkElwNrRbcQpiY3sWz1IcwwF9potnQzkUrfEj9cpsdIbTu8yJEhxl7TeVUKf2Iw1vSYb9NXCAWDIoHx8vvbE9n0GRK7YPzamNtLv0sLwhG0ocvI1USH208u4WYlzIqDF0fRoLeAY8UkWWbfj760p0+E/AEt+u8cBFmiBKkAwYVc+q1D+HDzy2KQv6riW8pbxQMAfunEEwZGsFFJTUrcjWBSrV2MZVUERvV0UhK0Fx1vinYkFGuYzdzcqg+39oUFZtH1Eae1hkie6F8txyaY8qWHSMT1pmxYmOEvmhR9BWWw6fkwiLs/walxvhPrUjaGH5sZKFRS6q2H8MxAt4jrQgO50RR4g1YwTOktWQXlq/9R/PwKX0CnFldOUA0TA9GOZ9Yq5ptX54njJbfuvPs+MyH50ibLcHKRg6eXRmdN1qDJB/msxEyB0b13+5jMGPJMDUUS9sG3UizvPES5YWOcfTX52qG4lCVxX6aC5JXElOApGudYB2jlmuGRyviFlu887tPfuxmGhadUfvWPZFcrZt+L2E06OhT5JDe8pDtmV3ynEUpdh7JAqESypwl5WsYfOxaM3pBZWdGo60xxLGtmLiUsfPgF9oqzWo/iXjOORuAF7jJiahlLGN6d22afkEBI6N3AyrWb+zUno2AKI/P++zMf/B53cLUFiYtjKefVcfsnHSQo30QXOFbN4Pw8wNxwQvt2QDj32Nap8XzpU2tYEMEc/+94P2RXsvQDNAmEwfOtjFKHm1DoJvOTOXyo8sAd4XdFBMEMy+oq1B4tbp80TQKezXYoF+nL+F8WSOHP2xmSorr/m6HvmSEzaD4PbOU5enGq4iLIPVlPd02aaIGZRdhV7FzQggVVVFEwbHnMtwLM1iA7tJ9D8fyEyrggOJXp6Jrf8r+pTrJGTH8AxM1IqupEwh3aqXhcBD+Y57qcLt7N6XGJulOpr3EZb0si7jTZairAf5ttNV7QqH5ahdms9jy4wlEpqukvKEh1t+2kmWekPzHcfLvCikPUZY70kh3FYzA= X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58b3ef36-ff9e-4c0b-2e26-08da3e479e06 X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:54.2714 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +MHEAQWu/sGoV1K+vkiuZ126lo1DVyXHlaj0CB9w/LYmnM/AqtmW9zsHpSlolAZVyR5i/UhRPMxjQri2VzI8eiE8KIUba7FmUXrZSsYfwgM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7859 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of multiple clusters to the system. In these systems each cluster contains its own GIC, so the GIC isn't truly global any longer. We do have the ability to access registers in the GICs of remote clusters using a redirect register block much like the redirect register blocks provided by the CM & CPC, and configured through the same GCR_REDIRECT register that we our mips_cm_lock_other() abstraction builds upon. It is expected that external interrupts are connected identically to all clusters. That is, if we have a device providing an interrupt connected to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC in the system. This simplifies things somewhat by allowing us for the most part to treat the GIC as though it is still truly global, so long as we take care to configure interrupts in the cluster that we want them affine to. This patch introduces support for such multi-cluster systems in the MIPS GIC irqchip driver. We introduce a new gic_irq_lock_cluster() function which allows us to either: 1) Configure access to a GIC in a remote cluster via the redirect register block, using mips_cm_lock_other(). Or: 2) Detect that the interrupt in question is affine to the local cluster and we should use plain old GIC register access to the GIC in the local cluster. It is possible to access the local cluster's GIC registers via the redirect block, but keeping the special case for them is both good for performance (because we avoid the locking & indirection overhead of using the redirect block) and necessary to maintain compatibility with systems using CM revisions prior to 3.5 which don't support the redirect block. The gic_irq_lock_cluster() function relies upon an IRQs effective affinity in order to discover which cluster the IRQ is affine to. In order to track this & allow it to be updated at an appropriate point during gic_set_affinity() we select the generic support for effective affinity using CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK. gic_set_affinity() is the one function which gains much complexity. It now deconfigures routing to any VP(E), ie. CPU, on the old cluster when moving affinity to a new cluster. Because we only configure an interrupts trigger type in the cluster which it is affine to we call gic_set_type() to configure that in the new cluster, after having updated the effective affinity mask such that gic_irq_lock_cluster() begins operating on the new cluster. Finally we map the interrupt to the appropriate pin & VP(E) in the new cluster. gic_shared_irq_domain_map() moves its update of the IRQs effective affinity to before its use of gic_irq_lock_cluster(), in order to ensure we operate on the cluster the IRQ is affine to. The remaining changes are straightforward use of the gic_irq_lock_cluster() function to select between local cluster & remote cluster code-paths when configuring interrupts. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 15edb9a6fcae..5f706b3a27aa 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -310,6 +310,7 @@ config KEYSTONE_IRQ config MIPS_GIC bool + select GENERIC_IRQ_EFFECTIVE_AFF_MASK select GENERIC_IRQ_IPI select MIPS_CM diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index f692392666a2..45c9c660f2ef 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -124,6 +124,41 @@ static int __gic_with_next_online_cpu(int prev) (cpu) = __gic_with_next_online_cpu(cpu), \ (cpu) < nr_cpu_ids;) +/** + * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster + * @d: struct irq_data corresponding to the interrupt we're interested in + * + * Locks redirect register block access to the global register block of the GIC + * within the remote cluster that the IRQ corresponding to @d is affine to, + * returning true when this redirect block setup & locking has been performed. + * + * If @d is affine to the local cluster then no locking is performed and this + * function will return false, indicating to the caller that it should access + * the local clusters registers without the overhead of indirection through the + * redirect block. + * + * In summary, if this function returns true then the caller should access GIC + * registers using redirect register block accessors & then call + * mips_cm_unlock_other() when done. If this function returns false then the + * caller should trivially access GIC registers in the local cluster. + * + * Returns true if locking performed, else false. + */ +static bool gic_irq_lock_cluster(struct irq_data *d) +{ + unsigned int cpu, cl; + + cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); + BUG_ON(cpu >= NR_CPUS); + + cl = cpu_cluster(&cpu_data[cpu]); + if (cl == cpu_cluster(¤t_cpu_data)) + return false; + + mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + return true; +} + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -170,7 +205,12 @@ static void gic_send_ipi(struct irq_data *d, unsigned int cpu) { irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); - write_gic_wedge(GIC_WEDGE_RW | hwirq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(GIC_WEDGE_RW | hwirq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(GIC_WEDGE_RW | hwirq); + } } int gic_get_c0_compare_int(void) @@ -238,7 +278,13 @@ static void gic_mask_irq(struct irq_data *d) { unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); - write_gic_rmask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_rmask(intr); + mips_cm_unlock_other(); + } else { + write_gic_rmask(intr); + } + gic_clear_pcpu_masks(intr); } @@ -247,7 +293,12 @@ static void gic_unmask_irq(struct irq_data *d) unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); unsigned int cpu; - write_gic_smask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_smask(intr); + mips_cm_unlock_other(); + } else { + write_gic_smask(intr); + } gic_clear_pcpu_masks(intr); cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); @@ -258,7 +309,12 @@ static void gic_ack_irq(struct irq_data *d) { unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); - write_gic_wedge(irq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(irq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(irq); + } } static int gic_set_type(struct irq_data *d, unsigned int type) @@ -298,9 +354,16 @@ static int gic_set_type(struct irq_data *d, unsigned int type) break; } - change_gic_pol(irq, pol); - change_gic_trig(irq, trig); - change_gic_dual(irq, dual); + if (gic_irq_lock_cluster(d)) { + change_gic_redir_pol(irq, pol); + change_gic_redir_trig(irq, trig); + change_gic_redir_dual(irq, dual); + mips_cm_unlock_other(); + } else { + change_gic_pol(irq, pol); + change_gic_trig(irq, trig); + change_gic_dual(irq, dual); + } if (trig == GIC_TRIG_EDGE) irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, @@ -318,25 +381,72 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); + unsigned int cpu, cl, old_cpu, old_cl; unsigned long flags; - unsigned int cpu; + /* + * The GIC specifies that we can only route an interrupt to one VP(E), + * ie. CPU in Linux parlance, at a time. Therefore we always route to + * the first online CPU in the mask. + */ cpu = cpumask_first_and(cpumask, cpu_online_mask); if (cpu >= NR_CPUS) return -EINVAL; - /* Assumption : cpumask refers to a single CPU */ - spin_lock_irqsave(&gic_lock, flags); + old_cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); + old_cl = cpu_cluster(&cpu_data[old_cpu]); + cl = cpu_cluster(&cpu_data[cpu]); - /* Re-route this IRQ */ - write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + spin_lock_irqsave(&gic_lock, flags); - /* Update the pcpu_masks */ - gic_clear_pcpu_masks(irq); - if (read_gic_mask(irq)) - set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + /* + * If we're moving affinity between clusters, stop routing the + * interrupt to any VP(E) in the old cluster. + */ + if (cl != old_cl) { + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_vp(irq, 0); + mips_cm_unlock_other(); + } else { + write_gic_map_vp(irq, 0); + } + } + /* + * Update effective affinity - after this gic_irq_lock_cluster() will + * begin operating on the new cluster. + */ irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + /* + * If we're moving affinity between clusters, configure the interrupt + * trigger type in the new cluster. + */ + if (cl != old_cl) + gic_set_type(d, irqd_get_trigger_type(d)); + + /* Route the interrupt to its new VP(E) */ + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_pin(irq, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_redir_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + + mips_cm_unlock_other(); + } else { + write_gic_map_pin(irq, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + } + spin_unlock_irqrestore(&gic_lock, flags); return IRQ_SET_MASK_OK; @@ -488,11 +598,21 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, unsigned long flags; data = irq_get_irq_data(virq); + irq_data_update_effective_affinity(data, cpumask_of(cpu)); spin_lock_irqsave(&gic_lock, flags); - write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); - write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); - irq_data_update_effective_affinity(data, cpumask_of(cpu)); + + /* Route the interrupt to its VP(E) */ + if (gic_irq_lock_cluster(data)) { + write_gic_redir_map_pin(intr, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + mips_cm_unlock_other(); + } else { + write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + } + spin_unlock_irqrestore(&gic_lock, flags); return 0; @@ -670,6 +790,9 @@ static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, if (ret) goto error; + /* Set affinity to cpu. */ + irq_data_update_effective_affinity(irq_get_irq_data(virq + i), + cpumask_of(cpu)); ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); 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Wed, 25 May 2022 12:10:56 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 07/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Date: Wed, 25 May 2022 14:10:25 +0200 Message-Id: <20220525121030.16054-8-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42273378-62a5-437b-8abd-08da3e479e65 X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The counters in each GIC are not synchronised in any way, so they can drift relative to one another through the lifetime of the system. This is problematic for a clocksource which ought to be global. Avoid problems by always accessing cluster 0's counter, using cross-cluster register access. This adds overhead so we only do so on systems where we actually have CPUs present in multiple clusters. For now, be extra conservative and don't use gic counter for vdso or sched_clock in this case. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index be4175f415ba..6632d314a2c0 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -170,6 +170,37 @@ static u64 gic_hpt_read(struct clocksource *cs) return gic_read_count(); } +static u64 gic_hpt_read_multicluster(struct clocksource *cs) +{ + unsigned int hi, hi2, lo; + u64 count; + + mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + if (mips_cm_is64) { + count = read_gic_redir_counter(); + goto out; + } + + hi = read_gic_redir_counter_32h(); + while (true) { + lo = read_gic_redir_counter_32l(); + + /* If hi didn't change then lo didn't wrap & we're done */ + hi2 = read_gic_redir_counter_32h(); + if (hi2 == hi) + break; + + /* Otherwise, repeat with the latest hi value */ + hi = hi2; + } + + count = (((u64)hi) << 32) + lo; +out: + mips_cm_unlock_other(); + return count; +} + static struct clocksource gic_clocksource = { .name = "GIC", .read = gic_hpt_read, @@ -204,6 +235,11 @@ static int __init __gic_clocksource_init(void) /* Calculate a somewhat reasonable rating value. */ gic_clocksource.rating = 200 + gic_frequency / 10000000; + if (mips_cps_multicluster_cpus()) { + gic_clocksource.read = &gic_hpt_read_multicluster; + gic_clocksource.vdso_clock_mode = VDSO_CLOCKMODE_NONE; + } + ret = clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0) pr_warn("Unable to register clocksource\n"); @@ -262,7 +298,8 @@ static int __init gic_clocksource_of_init(struct device_node *node) * stable CPU frequency or on the platforms with CM3 and CPU frequency * change performed by the CPC core clocks divider. */ - if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { + if ((mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) && + !mips_cps_multicluster_cpus()) { sched_clock_register(mips_cm_is64 ? gic_read_count_64 : gic_read_count_2x32, 64, gic_frequency); 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Wed, 25 May 2022 12:10:58 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 08/12] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Wed, 25 May 2022 14:10:26 +0200 Message-Id: <20220525121030.16054-9-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b59a8061-c9bc-42a3-84fc-08da3e479ec2 X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems it has been fine for us to clear COUNTSTOP once in gic_clocksource_of_init() in order to start the counter, since with only one cluster we know that we won't be resetting that cluster's GIC at any point (ignoring suspend/resume cycles which would need to handle clearing COUNTSTOP in the resume path). Once we support multi-cluster systems this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 6632d314a2c0..90a736a13115 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -119,6 +119,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -289,9 +292,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with From patchwork Wed May 25 12:10:27 2022 Content-Type: text/plain; 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Wed, 25 May 2022 12:10:58 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 09/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Date: Wed, 25 May 2022 14:10:27 +0200 Message-Id: <20220525121030.16054-10-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 566d64f6-4257-46db-43e1-08da3e479f24 X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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VPs/threads in a core). This works fine for single cluster systems, but with multi-cluster systems a core number is no longer unique in the system, leading to sharing between CPUs that are not actually siblings. Avoid this issue by using per-CPU variables as they are more generally used - ie. access them using CPU numbers rather than core numbers. Sharing between siblings is then accomplished by: - Assigning the same pointer to entries for each sibling CPU for the nc_asm_enter & ready_count variables, which allow this by virtue of being per-CPU pointers. - Indexing by the first CPU set in a CPUs cpu_sibling_map in the case of pm_barrier, for which we can't use the previous approach because the per-CPU variable is not a pointer. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 9bf60d7d44d3..a7bcf2b814c8 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -56,10 +56,7 @@ static DEFINE_PER_CPU_ALIGNED(u32*, ready_count); /* Indicates online CPUs coupled with the current CPU */ static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled); -/* - * Used to synchronize entry to deep idle states. Actually per-core rather - * than per-CPU. - */ +/* Used to synchronize entry to deep idle states */ static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier); /* Saved CPU state across the CPS_PM_POWER_GATED state */ @@ -118,9 +115,10 @@ int cps_pm_enter_state(enum cps_pm_state state) cps_nc_entry_fn entry; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; + atomic_t *barrier; /* Check that there is an entry function for this state */ - entry = per_cpu(nc_asm_enter, core)[state]; + entry = per_cpu(nc_asm_enter, cpu)[state]; if (!entry) return -EINVAL; @@ -156,7 +154,7 @@ int cps_pm_enter_state(enum cps_pm_state state) smp_mb__after_atomic(); /* Create a non-coherent mapping of the core ready_count */ - core_ready_count = per_cpu(ready_count, core); + core_ready_count = per_cpu(ready_count, cpu); nc_addr = kmap_noncoherent(virt_to_page(core_ready_count), (unsigned long)core_ready_count); nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK); @@ -164,7 +162,8 @@ int cps_pm_enter_state(enum cps_pm_state state) /* Ensure ready_count is zero-initialised before the assembly runs */ WRITE_ONCE(*nc_core_ready_count, 0); - coupled_barrier(&per_cpu(pm_barrier, core), online); + barrier = &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu])); + coupled_barrier(barrier, online); /* Run the generated entry code */ left = entry(online, nc_core_ready_count); @@ -635,12 +634,14 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) static int cps_pm_online_cpu(unsigned int cpu) { - enum cps_pm_state state; - unsigned core = cpu_core(&cpu_data[cpu]); + unsigned int sibling, core; void *entry_fn, *core_rc; + enum cps_pm_state state; + + core = cpu_core(&cpu_data[cpu]); for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) { - if (per_cpu(nc_asm_enter, core)[state]) + if (per_cpu(nc_asm_enter, cpu)[state]) continue; if (!test_bit(state, state_support)) continue; @@ -652,16 +653,19 @@ static int cps_pm_online_cpu(unsigned int cpu) clear_bit(state, state_support); } - per_cpu(nc_asm_enter, core)[state] = entry_fn; + for_each_cpu(sibling, &cpu_sibling_map[cpu]) + per_cpu(nc_asm_enter, sibling)[state] = entry_fn; } - if (!per_cpu(ready_count, core)) { + if (!per_cpu(ready_count, cpu)) { core_rc = kmalloc(sizeof(u32), GFP_KERNEL); if (!core_rc) { pr_err("Failed allocate core %u ready_count\n", core); return -ENOMEM; } - per_cpu(ready_count, core) = core_rc; + + for_each_cpu(sibling, &cpu_sibling_map[cpu]) + per_cpu(ready_count, sibling) = core_rc; } return 0; From patchwork Wed May 25 12:10:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA35C433EF for ; Wed, 25 May 2022 12:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243610AbiEYML2 (ORCPT ); Wed, 25 May 2022 08:11:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243338AbiEYMLU (ORCPT ); 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For now only one struct cluster_boot_config will be allocated & we'll simply defererence its core_config field to find the struct core_boot_config array which we use to boot as usual. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 7e5b9411faee..84a713667be2 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -20,7 +20,11 @@ struct core_boot_config { struct vpe_boot_config *vpe_config; }; -extern struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config { + struct core_boot_config *core_config; +}; + +extern struct cluster_boot_config *mips_cps_cluster_bootcfg; extern void mips_cps_core_entry(void); extern void mips_cps_core_init(void); diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 04ca75278f02..7d1f032e8275 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -391,6 +391,9 @@ void output_cps_defines(void) { COMMENT(" MIPS CPS offsets. "); + OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config); + DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config)); + OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config)); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 975343240148..f80466f810d4 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -17,6 +17,10 @@ #define GCR_CPC_BASE_OFS 0x0088 #define GCR_CL_COHERENCE_OFS 0x2008 #define GCR_CL_ID_OFS 0x2028 +#define CM3_GCR_Cx_ID_CLUSTER_SHF 8 +#define CM3_GCR_Cx_ID_CLUSTER_MSK (0xff << 8) +#define CM3_GCR_Cx_ID_CORENUM_SHF 0 +#define CM3_GCR_Cx_ID_CORENUM_MSK (0xff << 0) #define CPC_CL_VC_STOP_OFS 0x2020 #define CPC_CL_VC_RUN_OFS 0x2028 @@ -305,13 +309,22 @@ LEAF(mips_cps_core_init) */ LEAF(mips_cps_get_bootcfg) /* Calculate a pointer to this cores struct core_boot_config */ + PTR_LA v0, mips_cps_cluster_bootcfg + PTR_L v0, 0(v0) cmgcrb t0 lw t0, GCR_CL_ID_OFS(t0) +#ifdef CONFIG_CPU_MIPSR6 + ext t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8 + li t2, CLUSTERBOOTCFG_SIZE + mul t1, t1, t2 + PTR_ADDU \ + v0, v0, t1 +#endif + PTR_L v0, CLUSTERBOOTCFG_CORECONFIG(v0) + andi t0, t0, CM3_GCR_Cx_ID_CORENUM_MSK li t1, COREBOOTCFG_SIZE mul t0, t0, t1 - PTR_LA t1, mips_cps_core_bootcfg - PTR_L t1, 0(t1) - PTR_ADDU v0, t0, t1 + PTR_ADDU v0, v0, t0 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ li t9, 0 diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index a7bcf2b814c8..84e79bd84971 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -107,12 +107,14 @@ static void coupled_barrier(atomic_t *a, unsigned online) int cps_pm_enter_state(enum cps_pm_state state) { unsigned cpu = smp_processor_id(); + unsigned int cluster = cpu_cluster(¤t_cpu_data); unsigned core = cpu_core(¤t_cpu_data); unsigned online, left; cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled); u32 *core_ready_count, *nc_core_ready_count; void *nc_addr; cps_nc_entry_fn entry; + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; atomic_t *barrier; @@ -142,7 +144,8 @@ int cps_pm_enter_state(enum cps_pm_state state) if (!mips_cps_smp_in_use()) return -EINVAL; - core_cfg = &mips_cps_core_bootcfg[core]; + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; + core_cfg = &cluster_cfg->core_config[core]; vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)]; vpe_cfg->pc = (unsigned long)mips_cps_pm_restore; vpe_cfg->gp = (unsigned long)current_thread_info(); diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index bcd6a944b839..360d132bee71 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -27,7 +27,7 @@ static bool threads_disabled; static DECLARE_BITMAP(core_power, NR_CPUS); -struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config *mips_cps_cluster_bootcfg; static int __init setup_nothreads(char *s) { @@ -118,9 +118,11 @@ static void __init cps_smp_setup(void) static void __init cps_prepare_cpus(unsigned int max_cpus) { - unsigned ncores, core_vpes, c, cca; + unsigned int nclusters, ncores, core_vpes, c, cl, cca; bool cca_unsuitable, cores_limited; u32 *entry_code; + struct cluster_boot_config *cluster_bootcfg; + struct core_boot_config *core_bootcfg; mips_mt_set_cpuoptions(); @@ -168,40 +170,54 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (void *)entry_code - (void *)&mips_cps_core_entry); __sync(); - /* Allocate core boot configuration structs */ - ncores = mips_cps_numcores(0); - mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), - GFP_KERNEL); - if (!mips_cps_core_bootcfg) { - pr_err("Failed to allocate boot config for %u cores\n", ncores); - goto err_out; - } + /* Allocate cluster boot configuration structs */ + nclusters = mips_cps_numclusters(); + mips_cps_cluster_bootcfg = kcalloc(nclusters, + sizeof(*mips_cps_cluster_bootcfg), + GFP_KERNEL); - /* Allocate VPE boot configuration structs */ - for (c = 0; c < ncores; c++) { - core_vpes = core_vpe_count(0, c); - mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, - sizeof(*mips_cps_core_bootcfg[c].vpe_config), - GFP_KERNEL); - if (!mips_cps_core_bootcfg[c].vpe_config) { - pr_err("Failed to allocate %u VPE boot configs\n", - core_vpes); + for (cl = 0; cl < nclusters; cl++) { + /* Allocate core boot configuration structs */ + ncores = mips_cps_numcores(cl); + core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg), + GFP_KERNEL); + if (!core_bootcfg) goto err_out; + mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; + + /* Allocate VPE boot configuration structs */ + for (c = 0; c < ncores; c++) { + core_vpes = core_vpe_count(cl, c); + core_bootcfg[c].vpe_config = kcalloc(core_vpes, + sizeof(*core_bootcfg[c].vpe_config), + GFP_KERNEL); + if (!core_bootcfg[c].vpe_config) + goto err_out; } } /* Mark this CPU as booted */ - atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask, - 1 << cpu_vpe_id(¤t_cpu_data)); + cl = cpu_cluster(¤t_cpu_data); + c = cpu_core(¤t_cpu_data); + cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; + core_bootcfg = &cluster_bootcfg->core_config[c]; + atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); return; err_out: /* Clean up allocations */ - if (mips_cps_core_bootcfg) { - for (c = 0; c < ncores; c++) - kfree(mips_cps_core_bootcfg[c].vpe_config); - kfree(mips_cps_core_bootcfg); - mips_cps_core_bootcfg = NULL; + if (mips_cps_cluster_bootcfg) { + for (cl = 0; cl < nclusters; cl++) { + cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; + ncores = mips_cps_numcores(cl); + for (c = 0; c < ncores; c++) { + core_bootcfg = &cluster_bootcfg->core_config[c]; + kfree(core_bootcfg->vpe_config); + } + kfree(mips_cps_cluster_bootcfg[c].core_config); + } + kfree(mips_cps_cluster_bootcfg); + mips_cps_cluster_bootcfg = NULL; } /* Effectively disable SMP by declaring CPUs not present */ @@ -286,17 +302,23 @@ static void boot_core(unsigned int core, unsigned int vpe_id) static void remote_vpe_boot(void *dummy) { + unsigned int cluster = cpu_cluster(¤t_cpu_data); unsigned core = cpu_core(¤t_cpu_data); - struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg = + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); } static int cps_boot_secondary(int cpu, struct task_struct *idle) { + unsigned int cluster = cpu_cluster(&cpu_data[cpu]); unsigned core = cpu_core(&cpu_data[cpu]); unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); - struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg = + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; unsigned long core_entry; unsigned int remote; @@ -449,12 +471,14 @@ static void cps_kexec_nonboot_cpu(void) static int cps_cpu_disable(void) { unsigned cpu = smp_processor_id(); + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; if (!cps_pm_support_state(CPS_PM_POWER_GATED)) return -EINVAL; - core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)]; + cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; + core_cfg = &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); smp_mb__after_atomic(); set_cpu_online(cpu, false); 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Wed, 25 May 2022 12:11:00 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 11/12] MIPS: Report cluster in /proc/cpuinfo Date: Wed, 25 May 2022 14:10:29 +0200 Message-Id: <20220525121030.16054-12-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8285ba3b-7220-4ddb-73ca-08da3e479fd9 X-MS-TrafficTypeDiagnostic: VE1PR03MB5439:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index bb43bf850314..a66e7705315d 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -282,6 +283,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "kscratch registers\t: %d\n", hweight8(cpu_data[n].kscratch_mask)); seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package); + if (mips_cm_revision() >= CM_REV_CM3_5) + seq_printf(m, "cluster\t\t\t: %d\n", cpu_cluster(&cpu_data[n])); seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n])); #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) From patchwork Wed May 25 12:10:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 12861095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4B18C433FE for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: llQzSegOBhsIjG/TpCTEgvKeWdgg9pb9XXiWbT2hRzSsnxR6/Cw6ZbpePgHTKB8vH/Wpu3GnNyhc9RTr9dxUgpyJ2mhKuj9aIJJA/Oxjgyhv6XJJhm8cPGaEJccQedujRsPQkEapOOnOi50iOE1wjBD5//CUTxVyTGB5dbk6Ikvns1RvCa/R8wgBCeZ8+pOWX+0dt44gj4awRHTMmj0EY4zjvuEoARaui2xzeN7hbmuaFkFaJJ2NfdNjYvH6yNX2ToSxxeTyo6ZNpzMJPqJQme+hMjwqVeTX5iU+mkkP930eeB98WQAwaNiqMdTGWjOXVMQOOX23EMl5hgdHPk/NbZMrW4n3MLd7mYMJh1uNHtNONrCFN1KQk/m/4Sl/ISvPQgW1WTDKRNwq5NUdOIuAT1166nDReUozJFdN2rOYXNNj+itma+3ErrVMrOZALIVDnNA38WcxtuwI9aGYzLQQAS6yfi/lm6GSGE216Lyto5bdPloECTvbwECLENSQwjz+rvM7M7nr6tzJI1OIIrmpQSThD7NI9FHBpW1T6fjkeNfiASmEkEV9wqCkH+Lh8CPtjeNlLqCu6Iz3wLOHwj5gYZWvpJhEwCrKn+EThN7b0ONDNJoo9GFQSnn5ACUmw3PF3x/3qYeF7znHyRV3Lzc5aNvO/DDsMV7cqvVj14j2Q02RD4m2VoLcaR2B1Jrr10l9XWEU0gSAv4MiluaQg/il+F44MJp5UO6SWJb6OO7oNOWUXT53Pz+eNz1G+I+CU2CWAFcFzPABAYeeZu1VLYUBQMVcLVtTYhVqYjmsdaMzgcOSUeN27ONSr13xF8dJW33qw6OfcDkBBosrLD6QUxccENQzUueSxJljHZqv/yFGy5KLDyF9HkzKvnPD54viLVa1mQbtH8su1Fi57dJ9gl3X2CyDcVXDzyFBe3fDjKIZDdQme5S8/76h34098K61vmxlRYlBjbijL1rYB16LvGmw3q7WBxv8JOwkGlThBPVIhjOxS8hanmho4sRiJ1+KIhzO1XBFTJgG4BG6PWzOGw7ww0o+/fKvmNxDz+00Y/wg49MMd6hv0nXaRPAEw8wKrJm7OiWP/1BLvojj7r3tiiF/EDGDh+JkIvNoDFGiDzZ1NxtceAAjFCpCIxAmRxD7bo2TSZoX7G13adh5QvQJkuwTV+EhVxBlvoXf3rFNragE1Ka5D97EHzcQeywDYyoUWIeCB44p/XLj648rixMzvcAn6CT6X8f3sYI9AUOvhyDQx4+mPsao9wDQRpyc/55GGshe2oHwDNqLj0WHsszaBHBOCRSFDrBG61Xvyh5yvmhKPN0/4wewX0V5YqFvckTyhoQc2Dg4Wr1DEzmMo7QJ4kdF+ujbkYlSNDNeHGRnuVbzB0ZGrQdso/91iMsD06StfVV6KmLFksMeLbtaqpRaSbIgD6D0owiZlAaidtYNnb4StgTp02cWLg1x0h5Zts9qUU0tsK90vtheGlHHZ7Wj27lU9M8unD/miiyIew9SF59xVDjbywLHS0qRBEC7p5okx2eQDp+uDrllCJSQTi+nPlqd0X2cOAD5sVA2sD4bVpEuxPPvYic7qXinQfQF2UUhNAVwaU4T2J2cbVZL7MNvu8smSMvr3Se4hTk2RhlooIKs1K8AfJDSqrN5dbAkUXcTt728sjSXHV99QbB8NTKHAbTFEHZMhnTWfr6URE4ifdsI5R5XdFMreKQSP/hSbi8IbsrV0uSt+vRccLVLQJ54Sb7/JGXcI8PAa1p6NJglZHRXLGolsqchkT7LMzxLAhecMDXE X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: da47688e-03f6-40d7-827d-08da3e47a02a X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:57.8493 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jYu8iyqfCx0Zpiq+QPzNFmyFMe56FDMMrGvrKiojXPHyT9AdpH8J3icjUU6ddzR90QWUXuo+J7ZZ6MMT0gs4fJbSPJapO174ZsCJnNhkLSw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR03MB5439 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton Probe for & boot CPUs (cores & VPs) in secondary clusters (ie. not the cluster that began booting Linux) when they are present in systems with CM 3.5 or higher. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..435049907e44 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -239,6 +239,12 @@ GCR_ACCESSOR_RW(32, 0x130, l2_config) GCR_ACCESSOR_RO(32, 0x150, sys_config2) #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0) +/* GCR_L2-RAM_CONFIG - Configuration & status of L2 cache RAMs */ +GCR_ACCESSOR_RW(64, 0x240, l2_ram_config) +#define CM_GCR_L2_RAM_CONFIG_PRESENT BIT(31) +#define CM_GCR_L2_RAM_CONFIG_HCI_DONE BIT(30) +#define CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED BIT(29) + /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */ GCR_ACCESSOR_RW(32, 0x300, l2_pft_control) #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12) @@ -250,6 +256,18 @@ GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b) #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8) #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0) +/* GCR_L2_TAG_ADDR - Access addresses in L2 cache tags */ +GCR_ACCESSOR_RW(64, 0x600, l2_tag_addr) + +/* GCR_L2_TAG_STATE - Access L2 cache tag state */ +GCR_ACCESSOR_RW(64, 0x608, l2_tag_state) + +/* GCR_L2_DATA - Access data in L2 cache lines */ +GCR_ACCESSOR_RW(64, 0x610, l2_data) + +/* GCR_L2_ECC - Access ECC information from L2 cache lines */ +GCR_ACCESSOR_RW(64, 0x618, l2_ecc) + /* GCR_L2SM_COP - L2 cache op state machine control */ GCR_ACCESSOR_RW(32, 0x620, l2sm_cop) #define CM_GCR_L2SM_COP_PRESENT BIT(31) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 84a713667be2..7bcad119ceb1 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -21,6 +21,7 @@ struct core_boot_config { }; struct cluster_boot_config { + unsigned long *core_power; struct core_boot_config *core_config; }; diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 5b843c2ff077..f4c23bcab417 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -309,7 +309,9 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core, FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp); if (cm_rev >= CM_REV_CM3_5) { - val |= CM_GCR_Cx_OTHER_CLUSTER_EN; + if (cluster != cpu_cluster(¤t_cpu_data)) + val |= CM_GCR_Cx_OTHER_CLUSTER_EN; + val |= CM_GCR_Cx_OTHER_GIC_EN; val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster); val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block); } else { diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 360d132bee71..311e9e40e5c7 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -25,7 +25,6 @@ #include static bool threads_disabled; -static DECLARE_BITMAP(core_power, NR_CPUS); struct cluster_boot_config *mips_cps_cluster_bootcfg; @@ -36,6 +35,51 @@ static int __init setup_nothreads(char *s) } early_param("nothreads", setup_nothreads); +static void power_up_other_cluster(unsigned int cluster) +{ + u32 stat, seq_state; + unsigned int timeout; + + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); + stat = read_cpc_co_stat_conf(); + mips_cm_unlock_other(); + + seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; + seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); + if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) + return; + + /* Set endianness & power up the CM */ + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); + write_cpc_redir_pwrup_ctl(1); + mips_cm_unlock_other(); + + /* Wait for the CM to start up */ + timeout = 1000; + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); + while (1) { + stat = read_cpc_co_stat_conf(); + seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; + seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); + if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) + break; + + if (timeout) { + mdelay(1); + timeout--; + } else { + pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", + cluster, stat); + mdelay(1000); + } + } + + mips_cm_unlock_other(); +} + static unsigned core_vpe_count(unsigned int cluster, unsigned core) { if (threads_disabled) @@ -59,6 +103,9 @@ static void __init cps_smp_setup(void) pr_cont(","); pr_cont("{"); + if (mips_cm_revision() >= CM_REV_CM3_5) + power_up_other_cluster(cl); + ncores = mips_cps_numcores(cl); for (c = 0; c < ncores; c++) { core_vpes = core_vpe_count(cl, c); @@ -86,8 +133,8 @@ static void __init cps_smp_setup(void) /* Indicate present CPUs (CPU being synonymous with VPE) */ for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { - set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0); - set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0); + set_cpu_possible(v, true); + set_cpu_present(v, true); __cpu_number_map[v] = v; __cpu_logical_map[v] = v; } @@ -95,19 +142,15 @@ static void __init cps_smp_setup(void) /* Set a coherent default CCA (CWB) */ change_c0_config(CONF_CM_CMASK, 0x5); - /* Core 0 is powered up (we're running on it) */ - bitmap_set(core_power, 0, 1); - /* Initialise core 0 */ mips_cps_core_init(); /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); + core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); + if (mips_cm_revision() >= CM_REV_CM3) write_gcr_bev_base(core_entry); - } #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -185,6 +228,10 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) goto err_out; mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; + mips_cps_cluster_bootcfg[cl].core_power = + kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), + GFP_KERNEL); + /* Allocate VPE boot configuration structs */ for (c = 0; c < ncores; c++) { core_vpes = core_vpe_count(cl, c); @@ -196,11 +243,12 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) } } - /* Mark this CPU as booted */ + /* Mark this CPU as powered up & booted */ cl = cpu_cluster(¤t_cpu_data); c = cpu_core(¤t_cpu_data); cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; core_bootcfg = &cluster_bootcfg->core_config[c]; + bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1); atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); return; @@ -228,16 +276,123 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) } } -static void boot_core(unsigned int core, unsigned int vpe_id) +static void init_cluster_l2(void) { - u32 stat, seq_state; - unsigned timeout; + u32 l2_cfg, l2sm_cop, result; + + while (1) { + l2_cfg = read_gcr_redir_l2_ram_config(); + + /* If HCI is not supported, use the state machine below */ + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) + break; + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) + break; + + /* If the HCI_DONE bit is set, we're finished */ + if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) + return; + } + + l2sm_cop = read_gcr_redir_l2sm_cop(); + if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), + "L2 init not supported on this system yet")) + return; + + /* Clear L2 tag registers */ + write_gcr_redir_l2_tag_state(0); + write_gcr_redir_l2_ecc(0); + + /* Ensure the L2 tag writes complete before the state machine starts */ + mb(); + + /* Wait for the L2 state machine to be idle */ + do { + l2sm_cop = read_gcr_redir_l2sm_cop(); + } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); + + /* Start a store tag operation */ + l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; + l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE); + l2sm_cop |= CM_GCR_L2SM_COP_CMD_START; + write_gcr_redir_l2sm_cop(l2sm_cop); + + /* Ensure the state machine starts before we poll for completion */ + mb(); + + /* Wait for the operation to be complete */ + do { + l2sm_cop = read_gcr_redir_l2sm_cop(); + result = l2sm_cop & CM_GCR_L2SM_COP_RESULT; + result >>= __ffs(CM_GCR_L2SM_COP_RESULT); + } while (!result); + + WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK, + "L2 state machine failed cache init with error %u\n", result); +} + +static void boot_core(unsigned int cluster, unsigned int core, + unsigned int vpe_id) +{ + struct cluster_boot_config *cluster_cfg; + u32 access, stat, seq_state; + unsigned int timeout, ncores; + unsigned long core_entry; + + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; + ncores = mips_cps_numcores(cluster); + core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); + + if ((cluster != cpu_cluster(¤t_cpu_data)) && + bitmap_empty(cluster_cfg->core_power, ncores)) { + power_up_other_cluster(cluster); + + mips_cm_lock_other(cluster, core, 0, + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + /* Ensure cluster GCRs are where we expect */ + write_gcr_redir_base(read_gcr_base()); + write_gcr_redir_cpc_base(read_gcr_cpc_base()); + write_gcr_redir_gic_base(read_gcr_gic_base()); + + init_cluster_l2(); + + /* Mirror L2 configuration */ + write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); + write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); + write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); + + /* Mirror ECC/parity setup */ + write_gcr_redir_err_control(read_gcr_err_control()); + + /* Set BEV base */ + write_gcr_redir_bev_base(core_entry); + + mips_cm_unlock_other(); + } + + if (cluster != cpu_cluster(¤t_cpu_data)) { + mips_cm_lock_other(cluster, core, 0, + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + /* Ensure the core can access the GCRs */ + access = read_gcr_redir_access(); + access |= BIT(core); + write_gcr_redir_access(access); + + mips_cm_unlock_other(); + } else { + /* Ensure the core can access the GCRs */ + access = read_gcr_access(); + access |= BIT(core); + write_gcr_access(access); + } /* Select the appropriate core */ - mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); + mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -245,9 +400,6 @@ static void boot_core(unsigned int core, unsigned int vpe_id) /* Start it with the legacy memory map and exception base */ write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); - /* Ensure the core can access the GCRs */ - set_gcr_access(1 << core); - if (mips_cpc_present()) { /* Reset the core */ mips_cpc_lock_other(core); @@ -297,7 +449,17 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_unlock_other(); /* The core is now powered up */ - bitmap_set(core_power, core, 1); + bitmap_set(cluster_cfg->core_power, core, 1); + + /* + * Restore CM_PWRUP=0 so that the CM can power down if all the cores in + * the cluster do (eg. if they're all removed via hotplug. + */ + if (mips_cm_revision() >= CM_REV_CM3_5) { + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + write_cpc_redir_pwrup_ctl(0); + mips_cm_unlock_other(); + } } static void remote_vpe_boot(void *dummy) @@ -324,10 +486,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned int remote; int err; - /* We don't yet support booting CPUs in other clusters */ - if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data)) - return -ENOSYS; - vpe_cfg->pc = (unsigned long)&smp_bootstrap; vpe_cfg->sp = __KSTK_TOS(idle); vpe_cfg->gp = (unsigned long)task_thread_info(idle); @@ -336,14 +494,15 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) preempt_disable(); - if (!test_bit(core, core_power)) { + if (!test_bit(core, cluster_cfg->core_power)) { /* Boot a VPE on a powered down core */ - boot_core(core, vpe_id); + boot_core(cluster, core, vpe_id); goto out; } if (cpu_has_vp) { - mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); + mips_cm_lock_other(cluster, core, vpe_id, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); write_gcr_co_reset_base(core_entry); mips_cm_unlock_other(); @@ -543,11 +702,15 @@ static void wait_for_sibling_halt(void *ptr_cpu) static void cps_cpu_die(unsigned int cpu) { + unsigned int cluster = cpu_cluster(&cpu_data[cpu]); unsigned core = cpu_core(&cpu_data[cpu]); unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); ktime_t fail_time; unsigned stat; int err; + struct cluster_boot_config *cluster_cfg; + + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; /* Wait for the cpu to choose its way out */ if (!cpu_wait_death(cpu, 5)) { @@ -605,7 +768,7 @@ static void cps_cpu_die(unsigned int cpu) } while (1); /* Indicate the core is powered off */ - bitmap_clear(core_power, core, 1); + bitmap_clear(cluster_cfg->core_power, core, 1); } else if (cpu_has_mipsmt) { /* * Have a CPU with access to the offlined CPUs registers wait