From patchwork Mon May 30 11:27:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2A3CC433EF for ; Mon, 30 May 2022 11:33:34 +0000 (UTC) Received: from localhost ([::1]:47360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvdeP-0003ZS-L2 for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 07:33:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdYt-00006y-Le for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:55 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:43780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvdYg-0001KN-MI for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:51 -0400 Received: by mail-pl1-x632.google.com with SMTP id b5so10049442plx.10 for ; Mon, 30 May 2022 04:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4s3AwNuRr6rszDvvIyp9DCkPdUSckHh0rwFtRF3kLVg=; b=MyverThzPUgDt29aKnzMJ8Gq/UKB3OfFKLgzIRn00IjpK5II/ujLMNeWl7CLiGqN+T NHtfMR4vMH2boDjaOOOYudMfqX26I/XEZJU16MER1DSPIh1TkKGAzTjpqh4y8m+Lwq1+ o9h+4jrawdFePMI9n7XLjNjAsIGVo4oOrxdYHL426WEwHiR8StrYwjx6J2B0K7/V9mVi iXeu4qats729MrBRjZZrsPMDNur+v5i16RhTIwlggf/2HxqDlPKavqZXmBJeMvvg9c49 zEN8H2K9ZCpq24vc/9SZo3zxQ4O+JkLblMWmc4iv53vVxo1pvQ5bLviR93v8enYRnxfT Qz2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4s3AwNuRr6rszDvvIyp9DCkPdUSckHh0rwFtRF3kLVg=; b=ESxrzJtgszjwCUGeMYxUw04LtOsjehp2WGmj7StNCNhqDkiRb2uYJACXpYDezBOsWc Pjf8ebNGAc2o6qbfnrbWBJjAtb4u4YPHXBP5t6AA+0dpS9iZ/j8ZuoLkU289n3nUgj+k gP6vqFXIodrhyR2KBxPzhkaSJ419jESUyq19vxvYKnOp6S5r1WmapBe1NEMws1Kj9M/2 S1h/BNae2tyrfGNNfHDwWn3h3d7UP8ggWBisgxxspsa0D+xt7j4a8h2TUboeWh98rAjJ uPId7WXUjMTk9ksCmKoIhAfdC2vK8OAG7X6BsLBWmyM0wfR94MiqaVsU/KsUJsDUj1+t ckuA== X-Gm-Message-State: AOAM533ntPutPRDm3bHlxt0W70ZLTad/WvB2rVVeWac609EMYx30NjEy BCPkQHnqdWQ24UZ0SRrgNDk= X-Google-Smtp-Source: ABdhPJxaUYJxb0xd/snoKDj34DHYyJqTuk9JMBzP9c4EHRSAo9ZT+YakFC0T3DxfiPjRN1nidjsjvA== X-Received: by 2002:a17:90b:4ac9:b0:1e3:1dca:d995 with SMTP id mh9-20020a17090b4ac900b001e31dcad995mr1354585pjb.111.1653910056694; Mon, 30 May 2022 04:27:36 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id x26-20020aa7941a000000b0050dc7628158sm8647896pfo.50.2022.05.30.04.27.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:27:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 01/11] hw/acpi/piix4: move xen_enabled() logic from piix4_pm_init() to piix4_pm_realize() Date: Mon, 30 May 2022 13:27:08 +0200 Message-Id: <20220530112718.26582-2-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This logic can be included as part of piix4_pm_realize() and does not need to be handled externally. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20220528091934.15520-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index fe5625d07a..bf20fa139b 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -525,6 +525,10 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) s->machine_ready.notify = piix4_pm_machine_ready; qemu_add_machine_init_done_notifier(&s->machine_ready); + if (xen_enabled()) { + s->use_acpi_hotplug_bridge = false; + } + piix4_acpi_system_hot_add_init(pci_address_space_io(dev), pci_get_bus(dev), s); qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s)); @@ -551,9 +555,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, s->irq = sci_irq; s->smi_irq = smi_irq; s->smm_enabled = smm_enabled; - if (xen_enabled()) { - s->use_acpi_hotplug_bridge = false; - } pci_realize_and_unref(pci_dev, bus, &error_fatal); From patchwork Mon May 30 11:27:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACA76C433F5 for ; Mon, 30 May 2022 11:43:30 +0000 (UTC) Received: from localhost ([::1]:55634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvdo1-0001CM-DB for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 07:43:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdYw-00007X-Er for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:55 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:36769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvdYp-0001Kq-Pc for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:54 -0400 Received: by mail-pf1-x432.google.com with SMTP id f21so10336939pfa.3 for ; Mon, 30 May 2022 04:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OIu+NoT4gZ0qR5vroZwrG3oH+d1OSRS6QV1jDSTNRMk=; b=mgzQsmjVk5neRxzN/NbKBMjCI8JQj+BhEKxodL89IhVkaAN277YuKYzfrftAD+H+3q kHkijyy5/8TQuMWrxtawwKtm/3+tGzpSPsIX2wjfTM4drldVt9XsHq6K4tmsLtDDb5ay 6RiPV/YZRfB8OsO2JbSq4sUVGW+Ituh07TlLp4kyodmCLs3LreyByaTqRewc8B2EZcE/ qy6BTcVfU29IMhq6vE65t/IE4ZzPY7FyWugnjBhj4UmLUPnB8L0n5q5gX4TFpLhbFXta WOEplecgwzrhjYpgt1giBZ/7ellJfcdLxpFFI2To/j5090H6p0qsvlrfbR1htzsBAzY1 O46A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OIu+NoT4gZ0qR5vroZwrG3oH+d1OSRS6QV1jDSTNRMk=; b=izGqMF2EAwYGk2qwBBTwBu7ZUdj0ex8zPlBytbggLgmaKO+L1DulXmY+XFP99DePqB Ul7woI2CAsNzbDK+4EnaXMB3TZMo8Etog9YmdB3ZNU/NVwwEflCK82q8JEMA/ID62mma 7/XxbfeE+05D8RMrw9gGsSk72wrcS1HMrrLL9Qeqkw4uFMiTA1+pA/BawpVUAVKstTTf aU6mJB+CRRv3iALsgEulBSlKLXPx96mq2kIgz/DB1Tb6rMB7eqcEUlBrP5/LB5uf7eTV BT0TQHDCxKFplpJ4jYYjhFr1ytEF3JEhxfI+JD/ALSf/1ESrF9RxsNMVx6VcP5AdHhhP 2ugw== X-Gm-Message-State: AOAM533vnMN8Ym+OVkhijta52uDGjTsuSq0x3x7bzrqMqZQs6Wxt5Duy Ckcj6+5LR6cFap1dlMjFhRk= X-Google-Smtp-Source: ABdhPJzbvP0MiHkjffrVpRJp6/UFD6cfPAOGikD4W2qGtGBjLHLCtXJr0PXT6IbOJQ2eEYltLvVFyg== X-Received: by 2002:aa7:888c:0:b0:505:7832:98fc with SMTP id z12-20020aa7888c000000b00505783298fcmr56211210pfe.0.1653910066470; Mon, 30 May 2022 04:27:46 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id c22-20020a170902c2d600b0015e8d4eb2e8sm8849963pla.306.2022.05.30.04.27.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:27:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 02/11] hw/acpi/piix4: change smm_enabled from int to bool Date: Mon, 30 May 2022 13:27:09 +0200 Message-Id: <20220530112718.26582-3-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This is in preparation for conversion to a qdev property. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20220528091934.15520-3-mark.cave-ayland@ilande.co.uk> [PMD: Change simm_enabled from int to bool, suggested by Ani Sinha] Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 4 ++-- include/hw/southbridge/piix.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index bf20fa139b..558c250884 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -74,7 +74,7 @@ struct PIIX4PMState { qemu_irq irq; qemu_irq smi_irq; - int smm_enabled; + bool smm_enabled; bool smm_compat; Notifier machine_ready; Notifier powerdown_notifier; @@ -538,7 +538,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, - int smm_enabled, DeviceState **piix4_pm) + bool smm_enabled, DeviceState **piix4_pm) { PCIDevice *pci_dev; DeviceState *dev; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index f63f83e5c6..ff8d96ae8c 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -19,7 +19,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, - int smm_enabled, DeviceState **piix4_pm); + bool smm_enabled, DeviceState **piix4_pm); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 From patchwork Mon May 30 11:27:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C362BC433EF for ; Mon, 30 May 2022 11:56:55 +0000 (UTC) Received: from localhost ([::1]:41898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nve0z-0003gC-U6 for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 07:56:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdZ1-0000AG-FV for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:59 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:43616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvdYz-0001M9-SF for qemu-devel@nongnu.org; Mon, 30 May 2022 07:27:59 -0400 Received: by mail-pf1-x42f.google.com with SMTP id y189so10318669pfy.10 for ; Mon, 30 May 2022 04:27:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Xg3ddB2ASNlFC7R7TJt/TAeFKmI/LPGXMVgfcznMf0=; b=mQK09UIXCOv/dAvenP8EcLB7GbC8/Bv3b1vlv9G6km3Y2JYf3LXy8EiJ98MU2lKy7Y 5YDc/Hf8JHRvNEH+Br/ST56ZA/NXN+QRS+ZgX/fZFZbx1datiMVyzQfe2CfqUuhG85Gh 7Xo/HuFis76AOVWNmYmBs20zYWXPnc+2s9IeZ37vprWAJKDa33gRcavnXrtW9uY/5cWD hKXH+JFGMfyU9gHVa4WBrlCo3Uva5QCgVANYeehy38UZSPaljuTkThYT7dS90wzxKBPM Yj4t0znta7yP/8W44pX+eiqclXwKwFEBH779NRhaPY/FFlWsfV0glRzyAAe8x0xGieqS V7tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Xg3ddB2ASNlFC7R7TJt/TAeFKmI/LPGXMVgfcznMf0=; b=DsoitxjuNEQSdcLx1SpEtf6SFflGlh8Ih4hrOEPZU7OAp2sKAZjK1LtOxqXB6aZQ4/ qQTsCoeLO+MBzR+07xZZLho8527XHMI2FMlD4Omb1E+DMkpPfVhdKRDUEG3avjLUoq1S X14Y1TqSkzFrMBP9EdFkgMY2X/es5MrKxxuSRYyayHXLT9p2OTxGHeMleScf4Xk8t9uo mMB/f+WofiTJjMtzuq72HMMlG1ghSS6PlkuF4iaWWQ39NKGioMWDPjUMW8MXx67PGcje GMwkvc5NEKh664BNTHRjxRkRAZcDRkAwVdTfrwt+rrVX+V+f7Q8JFrO/dMtZI5qpTgWt iK6Q== X-Gm-Message-State: AOAM532ivVGiOd5LVppAlHax/cGCAyHqaBTTG/b5ABKl2rgt0eOuc1gP rPYlww8Ku5eJ41qtgIM+i4I= X-Google-Smtp-Source: ABdhPJyJnBwmY334wWKxjsyfgqZm8oIRxztcJNCLi4S8SMovC5nTSJcQ+dTnVr2pXgwg+116gsxBEA== X-Received: by 2002:a62:e40e:0:b0:518:3f5d:eecc with SMTP id r14-20020a62e40e000000b005183f5deeccmr16496571pfh.22.1653910076255; Mon, 30 May 2022 04:27:56 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id u1-20020a17090282c100b00163fbb2bae5sm85700plz.209.2022.05.30.04.27.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:27:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 03/11] hw/acpi/piix4: convert smm_enabled bool to qdev property Date: Mon, 30 May 2022 13:27:10 +0200 Message-Id: <20220530112718.26582-4-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This allows the smm_enabled value to be set using a standard qdev property instead of being referenced directly in piix4_pm_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20220528091934.15520-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 558c250884..316e41e1d0 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -547,6 +547,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, pci_dev = pci_new(devfn, TYPE_PIIX4_PM); dev = DEVICE(pci_dev); qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); + qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); if (piix4_pm) { *piix4_pm = dev; } @@ -554,7 +555,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, s = PIIX4_PM(dev); s->irq = sci_irq; s->smi_irq = smi_irq; - s->smm_enabled = smm_enabled; pci_realize_and_unref(pci_dev, bus, &error_fatal); @@ -664,6 +664,7 @@ static Property piix4_pm_properties[] = { DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, acpi_memory_hotplug.is_enabled, true), DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), + DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false), DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState, not_migrate_acpi_index, false), DEFINE_PROP_END_OF_LIST(), From patchwork Mon May 30 11:27:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98C3EC433F5 for ; Mon, 30 May 2022 11:53:57 +0000 (UTC) Received: from localhost ([::1]:35978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvdy8-0007w6-EQ for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 07:53:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdZD-0000Lm-3C for qemu-devel@nongnu.org; Mon, 30 May 2022 07:28:11 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:43616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvdZ9-0001M9-9L for qemu-devel@nongnu.org; Mon, 30 May 2022 07:28:10 -0400 Received: by mail-pf1-x42f.google.com with SMTP id y189so10318669pfy.10 for ; Mon, 30 May 2022 04:28:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Brn3LJTyKBvbiwsipzY18kk75AySoM4ugZRgTNJLjIo=; b=pV/oXIBXxPoHovhL4/zfdDP/zJWl7bSw26MMjFCavv/8Ka9mmNAzEbFRIuxaOaiWmx bBu9nXt2ms4R7LeMCUB8e/RG968e5wf0AVcqHkIz8X38g5apghwFo31LABz9HlwgwLtI 68DOKSFynCdj5rJJj7uBaNabLsE1NxKxdZBbKPy2+cYHIIVbTzeI1Nu8wWMXjMuNIZFn KpdoVWVtWQv7PV3e6xkf9jWCboC6AaH6Oqa/e7R5Fl+MEATKGIPHMWqn71sd7ScNT0kk WetbegYE/462V06gDD29XSWPDZCX4Ek5H0tmWEkuSgPN3QDyxZRJZb16B92FlOckCNum Kgdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Brn3LJTyKBvbiwsipzY18kk75AySoM4ugZRgTNJLjIo=; b=6vb0XbCVLIu0WHqiAhnjNzai88M9y3+UIonBEyzatzl5QE/qkX/FLWc5gBIHde4+Ms uPT8uXib2EjilKoo03IaCdqINdSqMrpv15eCXOT8KdmOoU5v0ik3P0qczaG1+Jqn+2lw qlaTDqpfcF7/Ev7Mdk4H8HoY3YdekpMv30Bm2c57b1SXEB+Z2SbUccgri50LAu1Q330I jlpCXgpifIkAXN6OQfmkIrPfXdnLUnAAmb0bJYLz86a2tU3Dmmx63ykiF3bO4HquAib5 XxV1fndTKviGJgeK+UVIUOco5t3mFEEWzLXsbytEXgYFZH4m2LnbQYsRqr4pHgDW1/Cz yr0Q== X-Gm-Message-State: AOAM533n2UUhSELCmH7SCrLWVSHS7YhQ7MaClS3HcRRNWhCW7hDfGbNN JikQO2+9Wgd+0/PwL67yBLE= X-Google-Smtp-Source: ABdhPJwS/HRYryH7QiJlEBXQaFupn9xlCEcckktHttwFE6drqTHPJmGYZsucCmW3LAc3XW6g2ZyS8w== X-Received: by 2002:a65:4c0c:0:b0:3c1:5bb1:6701 with SMTP id u12-20020a654c0c000000b003c15bb16701mr48306913pgq.136.1653910086061; Mon, 30 May 2022 04:28:06 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id kx10-20020a17090b228a00b001cd4989fed4sm6699626pjb.32.2022.05.30.04.28.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:28:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 04/11] hw/acpi/piix4: move PIIX4PMState into separate piix4.h header Date: Mon, 30 May 2022 13:27:11 +0200 Message-Id: <20220530112718.26582-5-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This allows the QOM types in hw/acpi/piix4.c to be used elsewhere by simply including hw/acpi/piix4.h. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 43 +------------------- hw/i386/acpi-build.c | 1 + include/hw/acpi/piix4.h | 75 +++++++++++++++++++++++++++++++++++ include/hw/southbridge/piix.h | 2 - 4 files changed, 78 insertions(+), 43 deletions(-) create mode 100644 include/hw/acpi/piix4.h diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 316e41e1d0..c2177c5093 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -28,6 +28,8 @@ #include "hw/pci/pci.h" #include "hw/qdev-properties.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/pcihp.h" +#include "hw/acpi/piix4.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "sysemu/xen.h" @@ -56,47 +58,6 @@ struct pci_status { uint32_t down; }; -struct PIIX4PMState { - /*< private >*/ - PCIDevice parent_obj; - /*< public >*/ - - MemoryRegion io; - uint32_t io_base; - - MemoryRegion io_gpe; - ACPIREGS ar; - - APMState apm; - - PMSMBus smb; - uint32_t smb_io_base; - - qemu_irq irq; - qemu_irq smi_irq; - bool smm_enabled; - bool smm_compat; - Notifier machine_ready; - Notifier powerdown_notifier; - - AcpiPciHpState acpi_pci_hotplug; - bool use_acpi_hotplug_bridge; - bool use_acpi_root_pci_hotplug; - bool not_migrate_acpi_index; - - uint8_t disable_s3; - uint8_t disable_s4; - uint8_t s4_val; - - bool cpu_hotplug_legacy; - AcpiCpuHotplug gpe_cpu; - CPUHotplugState cpuhp_state; - - MemHotplugState acpi_memory_hotplug; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM) - static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index c125939ed6..89ac326d7f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -46,6 +46,7 @@ #include "hw/acpi/tpm.h" #include "hw/acpi/vmgenid.h" #include "hw/acpi/erst.h" +#include "hw/acpi/piix4.h" #include "sysemu/tpm_backend.h" #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h new file mode 100644 index 0000000000..32686a75c5 --- /dev/null +++ b/include/hw/acpi/piix4.h @@ -0,0 +1,75 @@ +/* + * ACPI implementation + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2.1 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef HW_ACPI_PIIX4_H +#define HW_ACPI_PIIX4_H + +#include "hw/pci/pci.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/cpu_hotplug.h" +#include "hw/acpi/memory_hotplug.h" +#include "hw/acpi/pcihp.h" +#include "hw/i2c/pm_smbus.h" +#include "hw/isa/apm.h" + +#define TYPE_PIIX4_PM "PIIX4_PM" +OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM) + +struct PIIX4PMState { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + + MemoryRegion io; + uint32_t io_base; + + MemoryRegion io_gpe; + ACPIREGS ar; + + APMState apm; + + PMSMBus smb; + uint32_t smb_io_base; + + qemu_irq irq; + qemu_irq smi_irq; + bool smm_enabled; + bool smm_compat; + Notifier machine_ready; + Notifier powerdown_notifier; + + AcpiPciHpState acpi_pci_hotplug; + bool use_acpi_hotplug_bridge; + bool use_acpi_root_pci_hotplug; + bool not_migrate_acpi_index; + + uint8_t disable_s3; + uint8_t disable_s4; + uint8_t s4_val; + + bool cpu_hotplug_legacy; + AcpiCpuHotplug gpe_cpu; + CPUHotplugState cpuhp_state; + + MemHotplugState acpi_memory_hotplug; +}; + +#endif diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index ff8d96ae8c..04cbc3fe30 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,8 +15,6 @@ #include "hw/pci/pci.h" #include "qom/object.h" -#define TYPE_PIIX4_PM "PIIX4_PM" - I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, bool smm_enabled, DeviceState **piix4_pm); From patchwork Mon May 30 11:27:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB328C433F5 for ; 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Mon, 30 May 2022 04:28:15 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id p1-20020a170902ebc100b00163ad74fe4esm2716945plg.70.2022.05.30.04.28.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:28:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 05/11] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState Date: Mon, 30 May 2022 13:27:12 +0200 Message-Id: <20220530112718.26582-6-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be mapped outside of piix4_pm_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 11 ++++------- hw/i386/pc_piix.c | 10 +++++----- hw/isa/piix4.c | 8 +++++--- include/hw/southbridge/piix.h | 7 ++++--- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index c2177c5093..c4cfb75020 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -497,9 +497,9 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) piix4_pm_add_properties(s); } -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled, DeviceState **piix4_pm) +PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + bool smm_enabled) { PCIDevice *pci_dev; DeviceState *dev; @@ -509,9 +509,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, dev = DEVICE(pci_dev); qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); - if (piix4_pm) { - *piix4_pm = dev; - } s = PIIX4_PM(dev); s->irq = sci_irq; @@ -519,7 +516,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, pci_realize_and_unref(pci_dev, bus, &error_fatal); - return s->smb.smbus; + return s; } static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 578e537b35..891692616b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -281,14 +281,14 @@ static void pc_init1(MachineState *machine, } if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - DeviceState *piix4_pm; + PIIX4PMState *piix4_pm; smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); + piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, + x86ms->gsi[9], smi_irq, + x86_machine_is_smm_enabled(x86ms)); + pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ - pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, - x86ms->gsi[9], smi_irq, - x86_machine_is_smm_enabled(x86ms), - &piix4_pm); smbus_eeprom_init(pcms->smbus, 8, NULL, 0); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8607e0ac36..7d9bedd1bb 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -293,6 +293,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) { PIIX4State *s; + PIIX4PMState *pms; PCIDevice *pci; DeviceState *dev; int devfn = PCI_DEVFN(10, 0); @@ -310,9 +311,10 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0, NULL); + pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100, + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0); + *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); } pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 04cbc3fe30..a362ec7484 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,10 +14,11 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled, DeviceState **piix4_pm); +PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + bool smm_enabled); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 From patchwork Mon May 30 11:27:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91A61C433F5 for ; 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Mon, 30 May 2022 04:28:25 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id j1-20020a635501000000b003f285ba5a9fsm8330168pgb.57.2022.05.30.04.28.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:28:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 06/11] hw/acpi/piix4: rename piix4_pm_init() to piix4_pm_initfn() Date: Mon, 30 May 2022 13:27:13 +0200 Message-Id: <20220530112718.26582-7-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland When QOMifying a device it is typical to use _init() as the suffix for an instance_init function, however this name is already in use by the legacy piix4_pm_init() wrapper function. Eventually the wrapper function will be removed, but for now rename it to piix4_pm_initfn() to avoid a naming collision. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 6 +++--- hw/i386/pc_piix.c | 6 +++--- hw/isa/piix4.c | 6 +++--- include/hw/southbridge/piix.h | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index c4cfb75020..418ec4ee56 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -497,9 +497,9 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) piix4_pm_add_properties(s); } -PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled) +PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + bool smm_enabled) { PCIDevice *pci_dev; DeviceState *dev; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 891692616b..d2ab9f966c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -284,9 +284,9 @@ static void pc_init1(MachineState *machine, PIIX4PMState *piix4_pm; smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, - x86ms->gsi[9], smi_irq, - x86_machine_is_smm_enabled(x86ms)); + piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, + x86ms->gsi[9], smi_irq, + x86_machine_is_smm_enabled(x86ms)); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(pcms->smbus, 8, NULL, 0); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 7d9bedd1bb..33a7015ea3 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -311,9 +311,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0); + pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0); *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index a362ec7484..f75a4adf5f 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -16,9 +16,9 @@ #include "qom/object.h" #include "hw/acpi/piix4.h" -PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled); +PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + bool smm_enabled); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 From patchwork Mon May 30 11:27:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB223C433EF for ; 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Mon, 30 May 2022 04:28:35 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id g2-20020a170902d5c200b0015e8d4eb2ddsm8905312plh.295.2022.05.30.04.28.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:28:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 07/11] hw/acpi/piix4: use qdev gpio to wire up sci_irq Date: Mon, 30 May 2022 13:27:14 +0200 Message-Id: <20220530112718.26582-8-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Introduce piix4_pm_init() instance init function and use it to initialise the separate qdev gpio for the SCI IRQ. The sci_irq can now be wired up directly using a qdev gpio instead of having to set the IRQ externally in piix4_pm_initfn(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-9-mark.cave-ayland@ilande.co.uk> [PMD: Partially squash 20220528091934.15520-8-mark.cave-ayland@ilande.co.uk] Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 12 +++++++++--- hw/i386/pc_piix.c | 4 ++-- hw/isa/piix4.c | 6 +++--- include/hw/southbridge/piix.h | 3 +-- 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 418ec4ee56..fe5ec0a723 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -497,9 +497,15 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) piix4_pm_add_properties(s); } +static void piix4_pm_init(Object *obj) +{ + PIIX4PMState *s = PIIX4_PM(obj); + + qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); +} + PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled) + qemu_irq smi_irq, bool smm_enabled) { PCIDevice *pci_dev; DeviceState *dev; @@ -511,7 +517,6 @@ PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); s = PIIX4_PM(dev); - s->irq = sci_irq; s->smi_irq = smi_irq; pci_realize_and_unref(pci_dev, bus, &error_fatal); @@ -663,6 +668,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_pm_info = { .name = TYPE_PIIX4_PM, .parent = TYPE_PCI_DEVICE, + .instance_init = piix4_pm_init, .instance_size = sizeof(PIIX4PMState), .class_init = piix4_pm_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d2ab9f966c..0662bf44a9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -284,9 +284,9 @@ static void pc_init1(MachineState *machine, PIIX4PMState *piix4_pm; smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, - x86ms->gsi[9], smi_irq, + piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, smi_irq, x86_machine_is_smm_enabled(x86ms)); + qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(pcms->smbus, 8, NULL, 0); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 33a7015ea3..0b6ea22143 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -311,9 +311,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0); + pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, NULL, 0); + qdev_connect_gpio_out(DEVICE(pms), 0, + qdev_get_gpio_in_named(dev, "isa", 9)); *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index f75a4adf5f..105d158f78 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -17,8 +17,7 @@ #include "hw/acpi/piix4.h" PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled); + qemu_irq smi_irq, bool smm_enabled); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 From patchwork Mon May 30 11:27:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1257C433EF for ; Mon, 30 May 2022 12:02:41 +0000 (UTC) Received: from localhost ([::1]:53200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nve6a-0003Pl-UU for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 08:02:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdZs-0001G7-5C for qemu-devel@nongnu.org; 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Mon, 30 May 2022 04:28:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 08/11] hw/acpi/piix4: use qdev gpio to wire up smi_irq Date: Mon, 30 May 2022 13:27:15 +0200 Message-Id: <20220530112718.26582-9-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Initialize the SMI IRQ in piix4_pm_init(). The smi_irq can now be wired up directly using a qdev gpio instead of having to set the IRQ externally in piix4_pm_initfn(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-10-mark.cave-ayland@ilande.co.uk> [PMD: Partially squash 20220528091934.15520-8-mark.cave-ayland@ilande.co.uk] Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 4 ++-- hw/i386/pc_piix.c | 3 ++- hw/isa/piix4.c | 2 +- include/hw/southbridge/piix.h | 2 +- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index fe5ec0a723..32033bc9d7 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -502,10 +502,11 @@ static void piix4_pm_init(Object *obj) PIIX4PMState *s = PIIX4_PM(obj); qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); + qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1); } PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq smi_irq, bool smm_enabled) + bool smm_enabled) { PCIDevice *pci_dev; DeviceState *dev; @@ -517,7 +518,6 @@ PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); s = PIIX4_PM(dev); - s->smi_irq = smi_irq; pci_realize_and_unref(pci_dev, bus, &error_fatal); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0662bf44a9..683ec39b80 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -284,9 +284,10 @@ static void pc_init1(MachineState *machine, PIIX4PMState *piix4_pm; smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, smi_irq, + piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, x86_machine_is_smm_enabled(x86ms)); qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); + qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(pcms->smbus, 8, NULL, 0); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0b6ea22143..775e15eb20 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -311,7 +311,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, NULL, 0); + pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, 0); qdev_connect_gpio_out(DEVICE(pms), 0, qdev_get_gpio_in_named(dev, "isa", 9)); *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 105d158f78..b69e0dfb04 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -17,7 +17,7 @@ #include "hw/acpi/piix4.h" PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq smi_irq, bool smm_enabled); + bool smm_enabled); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 From patchwork Mon May 30 11:27:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBEC4C433F5 for ; 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Mon, 30 May 2022 04:28:54 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h10-20020a63574a000000b003c25dfd7372sm8173575pgm.26.2022.05.30.04.28.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:28:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 09/11] hw/i386/pc_piix: create PIIX4_PM device directly instead of using piix4_pm_initfn() Date: Mon, 30 May 2022 13:27:16 +0200 Message-Id: <20220530112718.26582-10-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM device can be instantiated directly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 683ec39b80..d6668b7c06 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -47,6 +47,7 @@ #include "hw/xen/xen-x86.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -281,11 +282,15 @@ static void pc_init1(MachineState *machine, } if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - PIIX4PMState *piix4_pm; + PCIDevice *piix4_pm; smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, - x86_machine_is_smm_enabled(x86ms)); + piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); + qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); + qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", + x86_machine_is_smm_enabled(x86ms)); + pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); + qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); From patchwork Mon May 30 11:27:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23C4FC433EF for ; Mon, 30 May 2022 12:06:55 +0000 (UTC) Received: from localhost ([::1]:33606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nveAg-0000xb-7x for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 08:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdaC-0001KU-4e for qemu-devel@nongnu.org; Mon, 30 May 2022 07:29:15 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:46840) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvda6-0001T3-AW for qemu-devel@nongnu.org; Mon, 30 May 2022 07:29:11 -0400 Received: by mail-pf1-x42f.google.com with SMTP id j6so10314998pfe.13 for ; Mon, 30 May 2022 04:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mth1gvUbuD4AT0F5emQ5fFGB+oFvgzntgmPLZykCEgk=; b=YFyA6YyiGZkkNP4wZGZ5ATpr7ZA9BcvKzfCckF+xdXNZI+3loydGdlwZvKxrNbRpxY z6Atxs6DxghYD00iqhDP/NioWkd6va+9rI93jcDDt/D0dCqIJD9a3PQ6BZ9OVJeYKVrR SifmwG2h3RF6CmPUfAE4/c/B2N64fszvB2zMl4OrFcFl9vrv55om1y19RDzdD1qXOSRv QUlLmJQzdi0IlZL5pUBtH/XpVCMkaL5/lMZC9TewavkPgypeLmjKuoZ5ALOd9Jd/2x3p xiXdXjJwTQhEtenXP1KG0qaCZyGn4n/IOnK/pHQisK07LUuhFZQuo6uYFZqk0yRRvxlh Qn3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mth1gvUbuD4AT0F5emQ5fFGB+oFvgzntgmPLZykCEgk=; b=m9nRPYMr4khmbvug9mIUG2EYHqkJKH5MHUWLgNvieGLtKF1/KVXjTa5NPToKO+/l2N ze1uW147RjZnWD9aNTQVBEX4sT7NAeQarNH03StC8gBCi+OA/fQTUEY4gQ98trwyrVl1 UYO+HWv/wwqLcSoj0fGSU84AVL/8t4D/ql8h8b4DQ+IEXLlLpDewddBSP4HOFrnfuM2E 5o7ov60Ear9JI68S3GzlQPSl9VEKZIHwJru3k0PGWZS8xnHPisl9ETJrMQDlZabyZkMZ +/GnnZnTInM8EoOuyg2mFWizThG6SH228mBOFQzCfmd4op3fAVdRhDCzRH7J4LD+aFlB D1Zg== X-Gm-Message-State: AOAM532kAZXMyo5AWONvJcSA/HVUamKvAlWuyAykzoZl/vyDXlfZJ9bb eisy4eUEU/ybQvloE1vFovg= X-Google-Smtp-Source: ABdhPJw2HRYvEPYs42+NzxejWE6cgop6kpoYvz+VuJEdeYDDe1zwrx10Ujc1cznPh1ln1tqrnqu26g== X-Received: by 2002:a63:8043:0:b0:3fb:984f:69b2 with SMTP id j64-20020a638043000000b003fb984f69b2mr15585755pgd.108.1653910145196; Mon, 30 May 2022 04:29:05 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id m16-20020a170902f65000b0015e8d4eb2ccsm8880823plg.278.2022.05.30.04.29.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:29:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 10/11] hw/isa/piix4.c: create PIIX4_PM device directly instead of using piix4_pm_initfn() Date: Mon, 30 May 2022 13:27:17 +0200 Message-Id: <20220530112718.26582-11-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM device can be instantiated directly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 775e15eb20..9a6d981037 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -34,6 +34,7 @@ #include "hw/timer/i8254.h" #include "hw/rtc/mc146818rtc.h" #include "hw/ide/pci.h" +#include "hw/acpi/piix4.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -293,7 +294,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) { PIIX4State *s; - PIIX4PMState *pms; PCIDevice *pci; DeviceState *dev; int devfn = PCI_DEVFN(10, 0); @@ -311,10 +311,13 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, 0); - qdev_connect_gpio_out(DEVICE(pms), 0, + pci = pci_new(devfn + 3, TYPE_PIIX4_PM); + qdev_prop_set_uint32(DEVICE(pci), "smb_io_base", 0x1100); + qdev_prop_set_bit(DEVICE(pci), "smm-enabled", 0); + pci_realize_and_unref(pci, pci_bus, &error_fatal); + qdev_connect_gpio_out(DEVICE(pci), 0, qdev_get_gpio_in_named(dev, "isa", 9)); - *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); + *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pci), "i2c")); } pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); From patchwork Mon May 30 11:27:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12864578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91A95C433EF for ; Mon, 30 May 2022 12:12:34 +0000 (UTC) Received: from localhost ([::1]:45122 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nveG8-0000bY-UB for qemu-devel@archiver.kernel.org; Mon, 30 May 2022 08:12:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvdaJ-0001Rl-8T for qemu-devel@nongnu.org; Mon, 30 May 2022 07:29:22 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:47007) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvdaH-0001UB-IU for qemu-devel@nongnu.org; Mon, 30 May 2022 07:29:18 -0400 Received: by mail-pl1-x635.google.com with SMTP id w3so10053011plp.13 for ; Mon, 30 May 2022 04:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i4vm5jZ9TRldGyYRbAdinFtRSddzUKOPwSaq3LzDjBM=; b=e9Th+fdPFELEG7YJlF/DvBFBnnkeUuMXyctZZwHB0MqIS3NYzYwFsS7O8zV/0npK33 NkxunkyiLkEfiiCMywEKEOSA5+ESIqAw4iPh1SSo1dqh0xoy087OYW96HR6b1WK2qvA0 799t3yhcksYEFkC2P7BTZPoyd++9tntGcHJ9NpzZ1QqQJDfcaPwB/sHDJr1JaxjM2Bcp /9W7X9Qpodp9UzBgYjW4AXC83IHG0lEeGTnp0eUJvPEzql7BC4VyzTd/1XLK3P7Y3P83 52nstE2Mlc/cZKgYkiW4jOxKddd2DU43lsKmD/cmmUYfKR/IrhtGeX7Z9j+ngoLis8T5 j6jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i4vm5jZ9TRldGyYRbAdinFtRSddzUKOPwSaq3LzDjBM=; b=jbH9qlBuGtTI9KHC8DfbVX4nuoDptjW2kRnYrtQuYOdOV5E7fNWVHP/0zDUgu6Io1U rM9Ut2x16wcEA92lF50/YU49n1MvwRUbU0ZV3wA6McmltHhv6cjsuPaYISc2LJQssRK+ TaqZaVLy9bdb8t0DGikG+iBGa/n3kwmDjPdmi6zCffYjRjatHl4wCncMzYcTvMY/5y6b jMUyKtEuGGW3yHq3O9HgNNXZsmWtHLcW8jooJtr5SbQ7ITBvqGOaevYCn+ZUYbj7pyLN no/taKxBt1tPfDO+2gwJYJsPGD+l9lCS95jjewInPC+isyfuwQA+8TisLTuQIgzKGav7 Ynpg== X-Gm-Message-State: AOAM533t2SYpucrzsdZfKUF9AIsYgvlxexsWTulNPk24rhtUHeZ8BrcS oAe5Dx7Is5ee7hpvOqaMUz0= X-Google-Smtp-Source: ABdhPJxQFvnkdQavuCvbtMim8A8I6uQhCbNVHc25YZDrn97CIzJS2LzVhBYcf+xrAzEW0LKALnLZJA== X-Received: by 2002:a17:902:d582:b0:161:c681:c326 with SMTP id k2-20020a170902d58200b00161c681c326mr55495618plh.84.1653910155269; Mon, 30 May 2022 04:29:15 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id r4-20020a17090a1bc400b001e2d2235176sm3189215pjr.51.2022.05.30.04.29.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 May 2022 04:29:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 11/11] hw/acpi/piix4: remove unused piix4_pm_initfn() function Date: Mon, 30 May 2022 13:27:18 +0200 Message-Id: <20220530112718.26582-12-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This function is now unused and so can be completely removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220528091934.15520-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 19 ------------------- include/hw/southbridge/piix.h | 4 ---- 2 files changed, 23 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 32033bc9d7..0a81f1ad93 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -505,25 +505,6 @@ static void piix4_pm_init(Object *obj) qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1); } -PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - bool smm_enabled) -{ - PCIDevice *pci_dev; - DeviceState *dev; - PIIX4PMState *s; - - pci_dev = pci_new(devfn, TYPE_PIIX4_PM); - dev = DEVICE(pci_dev); - qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); - qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); - - s = PIIX4_PM(dev); - - pci_realize_and_unref(pci_dev, bus, &error_fatal); - - return s; -} - static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) { PIIX4PMState *s = opaque; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b69e0dfb04..976b4da582 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,10 +14,6 @@ #include "hw/pci/pci.h" #include "qom/object.h" -#include "hw/acpi/piix4.h" - -PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - bool smm_enabled); /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60