From patchwork Sat Jun 4 12:40:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12869611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7EF2C43334 for ; Sat, 4 Jun 2022 12:41:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234845AbiFDMlF (ORCPT ); Sat, 4 Jun 2022 08:41:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233159AbiFDMlE (ORCPT ); Sat, 4 Jun 2022 08:41:04 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1311531536; Sat, 4 Jun 2022 05:41:03 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 354F53200344; Sat, 4 Jun 2022 08:41:00 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Sat, 04 Jun 2022 08:41:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :message-id:mime-version:reply-to:sender:subject:subject:to:to; s=fm2; t=1654346459; x=1654432859; bh=lVC02QK4SHsr+00py+U1MSnZZ Egh3HHWEX2YPoM+RBo=; b=4hiQqR26na7FmbxhQbKOst12IMMuhyNU9p9p5LDCc gfwoi2N72pxgcVOoOB4G0174YDXLpZZ03hx9KYUxTuBk6DB67KU6BBq5ZzQjB8eg gZ61ae9f8u/JghYAXe4XaLB7clcWpSdab8MDmgl2SBLD1EGT4Kew6flvher+Pl0q bGzSvqV9cVlHktd4wIFf6a9gxoLR4wdDpbi44Q6v1pvr1A9kZ/l2S9RjYLpN4Fl1 W5BnCQapr6D+vniBN4RuseIZnKCt2TuvLXLF0jtBoCTENxAC6rPScx1bkmhjj9vc C71AM6OQEh0uiWbp+FfXntZUJteaAcp9+bPXSNp2fbBYQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1654346459; x=1654432859; bh=lVC02QK4SHsr+00py+U1MSnZZEgh3HHWEX2 YPoM+RBo=; b=FrbJDl6fBu/000qV/LpbkIRjm9EonOFBHRAzIvRFPf2/NjH410F akKPp9xHyX8qLugC4CkJlIvVOkcHmjg+f/Q5G6Z2UM3W2sgeN0lYXYDaMHGgFMqc 5GMQXwA9bEpSOqMs3UntXuLKsZ5SeOpZaEpAJGtFSRElCriWJkOH5UFiiWZiAc/Q JpA9vKHxJkpetlREqO9yjjpfB+Q/vta2/k2+Yj5//Oh+UsUXm1KLRS8Bit4EBE2n UUlGUf8d/DX7TwRiMe1BA8arkJz5Iyo5sFE3BXihSrvNBC4jCjnSJQLhVsi5juqB NHtYLTGbZph1xYaoOw4CmK2Jv405wWilkRA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrleekgdehgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgggfestdekredtre dttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhgsehf lhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpefhtedutdduveeileejjeetff ehueejudehgfffjeduhfeuleeludfffefgffevkeenucevlhhushhtvghrufhiiigvpedt necurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihghhorg htrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Jun 2022 08:40:57 -0400 (EDT) From: Jiaxun Yang To: chenhuacai@kernel.org Cc: kernel@xen0n.name, maz@kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Jiaxun Yang Subject: [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Date: Sat, 4 Jun 2022 13:40:51 +0100 Message-Id: <20220604124052.1550-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch") replaced get_ebase_cpunum with physical processor id from SMP facilities. However that breaks MIPS non-SMP build and makes booting from other cores inpossible on non-SMP kernel. Thus we revert get_ebase_cpunum back and use get_csr_cpuid for LoongArch. Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch") Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index aed88857d90f..c11cf97bcd1a 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -39,6 +39,14 @@ #define LIOINTC_ERRATA_IRQ 10 +#if defined(CONFIG_MIPS) +#define liointc_core_id get_ebase_cpunum() +#elif defined(CONFIG_LOONGARCH) +#define liointc_core_id get_csr_cpuid() +#else +#define liointc_core_id 0 +#endif + struct liointc_handler_data { struct liointc_priv *priv; u32 parent_int_map; @@ -57,7 +65,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip_generic *gc = handler->priv->gc; - int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES; + int core = liointc_core_id % LIOINTC_NUM_CORES; u32 pending; chained_irq_enter(chip, desc); From patchwork Sat Jun 4 12:40:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12869612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8D89CCA47C for ; Sat, 4 Jun 2022 12:41:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233159AbiFDMlH (ORCPT ); Sat, 4 Jun 2022 08:41:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241004AbiFDMlG (ORCPT ); Sat, 4 Jun 2022 08:41:06 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7879E31536; 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Sat, 4 Jun 2022 08:41:01 -0400 (EDT) From: Jiaxun Yang To: chenhuacai@kernel.org Cc: kernel@xen0n.name, maz@kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Jiaxun Yang Subject: [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid Date: Sat, 4 Jun 2022 13:40:52 +0100 Message-Id: <20220604124052.1550-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604124052.1550-1-jiaxun.yang@flygoat.com> References: <20220604124052.1550-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Only low 9 bits of CPUID CSR represents coreid, higher bits are marked as reserved. In case Loongson may define higher bits in future, just mask them out for get_csr_cpuid. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/loongarch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 3ba4f7e87cd2..7f3933f747f9 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -1200,7 +1200,7 @@ static inline u64 drdtime(void) static inline unsigned int get_csr_cpuid(void) { - return csr_read32(LOONGARCH_CSR_CPUID); + return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID; } static inline void csr_any_send(unsigned int addr, unsigned int data,