From patchwork Tue Jun 7 11:31:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 12871794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D1E6C43334 for ; Tue, 7 Jun 2022 11:33:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=qnXXdgqgWJUDt7Ny2iCB1wU5TduusgZ5zC1fiSJ5ALs=; b=UInPm2EsZRKXEm Zypc62BxqUOZTKoe2zVXA4b8GqnBoUIuwO05GMVfO+P7crxYjO+LmIS/rsVUa1p3iMRrqXZ/WwS5r TeLU3Im2c0GaEGLaBQAxunaH9FzBmsrMdvg4ST9+KYfRQDFo+iLFfOJYN3SVL0XSJY0gVsoi13C6k aozPT+UavdiypHk4zCMTS8Fz2U/0C+1SCdtIg+nDQI6zdRtB8/elF4d9g78BGVQbfbUJFCE4VIPUb 9aCJxUa6m7YSp1JD+jbJCzh7vhOwtEC2oalRcG1OIVp1vqqGwO6iVa54umzWgvQ7Znz8edVVDcNCD ZVgigEB2OU1G32Be7zKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyXRm-00761U-GV; Tue, 07 Jun 2022 11:32:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyXRf-0075yZ-Kg for linux-arm-kernel@lists.infradead.org; Tue, 07 Jun 2022 11:32:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1763814BF; Tue, 7 Jun 2022 04:32:19 -0700 (PDT) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B90D3F73B; Tue, 7 Jun 2022 04:32:18 -0700 (PDT) From: Vincenzo Frascino To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com Cc: vincenzo.frascino@arm.com, Catalin Marinas , Will Deacon Subject: [PATCH] mte: Initialize tag storage to KASAN_TAG_INVALID Date: Tue, 7 Jun 2022 12:31:50 +0100 Message-Id: <20220607113150.55140-1-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_043223_821915_33E788E7 X-CRM114-Status: GOOD ( 15.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the kernel is entered on aarch64, the MTE allocation tags are in an UNKNOWN state. With MTE enabled, the tags are initialized: - When a page is allocated and the user maps it with PROT_MTE. - On allocation, with in-kernel MTE enabled (KHWASAN). If the tag pool is zeroed by the hardware at reset, it makes it difficult to track potential places where the initialization of the tags was missed. This can be observed under QEMU for aarch64, which initializes the MTE allocation tags to zero. Initialize to tag storage to KASAN_TAG_INVALID to catch potential places where the initialization of the tags was missed. This is done introducing a new kernel command line parameter "mte.tags_init" that enables the debug option. Note: The proposed solution should be considered a debug option because it might have performance impact on large machines at boot. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Vincenzo Frascino --- arch/arm64/kernel/mte.c | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 57b30bcf9f21..259a826363f1 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,8 @@ DEFINE_STATIC_KEY_FALSE(mte_async_or_asymm_mode); EXPORT_SYMBOL_GPL(mte_async_or_asymm_mode); #endif +static bool mte_tags_init __ro_after_init; + static void mte_sync_page_tags(struct page *page, pte_t old_pte, bool check_swap, bool pte_is_tagged) { @@ -107,6 +110,48 @@ int memcmp_pages(struct page *page1, struct page *page2) return ret; } +/* mte.tags_init=off/on */ +static int __init early_mte_tags_init(char *arg) +{ + if (!arg) + return -EINVAL; + + if (!strcmp(arg, "off")) + mte_tags_init = false; + else if (!strcmp(arg, "on")) + mte_tags_init = true; + else + return -EINVAL; + + return 0; +} +early_param("mte.tags_init", early_mte_tags_init); + +static inline void __mte_tag_storage_init(void) +{ + static bool mte_tags_uninitialized = true; + phys_addr_t pa_start, pa_end; + u64 index; + + if (mte_tags_init && !mte_tags_uninitialized) + return; + + for_each_mem_range(index, &pa_start, &pa_end) { + void *va_start = (void *)__phys_to_virt(pa_start); + void *va_end = (void *)__phys_to_virt(pa_end); + size_t va_size = (u64)va_end - (u64)va_start; + + if (va_start >= va_end) + break; + + mte_set_mem_tag_range(va_start, va_size, KASAN_TAG_INVALID, false); + } + + /* Tags are now initialized to KASAN_TAG_INVALID */ + mte_tags_uninitialized = false; + pr_info("MTE: Tag Storage Initialized\n"); +} + static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) { /* Enable MTE Sync Mode for EL1. */ @@ -114,6 +159,8 @@ static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf)); isb(); + __mte_tag_storage_init(); + pr_info_once("MTE: enabled in %s mode at EL1\n", mode); }