From patchwork Wed Jun 8 05:39:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Liu X-Patchwork-Id: 12872872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E832AC433EF for ; Wed, 8 Jun 2022 05:43:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 07 Jun 2022 22:41:59 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 7 Jun 2022 22:39:23 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 13:39:21 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 8 Jun 2022 13:39:20 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: =?unknown-8bit?q?Sean_Wang_=3Csean=2Ewang=40mediatek=2Ecom=3E=2C_Zhiyong?= =?unknown-8bit?q?_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_N=EDcolas_F_?= =?unknown-8bit?q?=2E_R_=2E_A_=2E_Prado_=3Cnfraprado=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_=3Clinux-gpio=40vger=2Ekernel=2Eorg=3E=2C_=3Cdevicetree?= =?unknown-8bit?q?=40vger=2Ekernel=2Eorg=3E=2C_=3Clinux-arm-kernel=40lists?= =?unknown-8bit?q?=2Einfradead=2Eorg=3E=2C_=3Clinux-mediatek=40lists=2Einfra?= =?unknown-8bit?q?dead=2Eorg=3E=2C_=3Clinux-kernel=40vger=2Ekernel=2Eorg=3E?= =?unknown-8bit?q?=2C_=3CProject=5FGlobal=5FChrome=5FUpstream=5FGroup=40medi?= =?unknown-8bit?q?atek=2Ecom=3E=2C_Guodong_Liu_=3Cguodong=2Eliu=40mediatek?= =?unknown-8bit?q?=2Ecom=3E?= Subject: [PATCH v1 1/4] pinctrl: add generic driving setup property on mt8192 Date: Wed, 8 Jun 2022 13:39:06 +0800 Message-ID: <20220608053909.1252-2-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220608053909.1252-1-guodong.liu@mediatek.com> References: <20220608053909.1252-1-guodong.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_224203_451595_2EF54466 X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch provides generic driving setup, which support 2/4/6/8/10/12/14/16mA driving, original driver just set raw data setup setting when use drive-strength property Signed-off-by: Guodong Liu --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index acccde9262ba..9faf7001369d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1372,8 +1372,8 @@ static const struct mtk_pin_soc mt8192_data = { .gpio_m = 0, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_raw, - .drive_get = mtk_pinconf_drive_get_raw, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, .adv_pull_get = mtk_pinconf_adv_pull_get, .adv_pull_set = mtk_pinconf_adv_pull_set, .adv_drive_get = mtk_pinconf_adv_drive_get, From patchwork Wed Jun 8 05:39:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Liu X-Patchwork-Id: 12872873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2968AC43334 for ; Wed, 8 Jun 2022 05:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GIjtMaZAdQZ1bgQzd0AQ75xHS3tuoKmBwlvjh6lcOV8=; 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Tue, 07 Jun 2022 22:42:09 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 7 Jun 2022 22:39:41 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 13:39:40 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 8 Jun 2022 13:39:38 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: =?unknown-8bit?q?Sean_Wang_=3Csean=2Ewang=40mediatek=2Ecom=3E=2C_Zhiyong?= =?unknown-8bit?q?_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_N=EDcolas_F_?= =?unknown-8bit?q?=2E_R_=2E_A_=2E_Prado_=3Cnfraprado=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_=3Clinux-gpio=40vger=2Ekernel=2Eorg=3E=2C_=3Cdevicetree?= =?unknown-8bit?q?=40vger=2Ekernel=2Eorg=3E=2C_=3Clinux-arm-kernel=40lists?= =?unknown-8bit?q?=2Einfradead=2Eorg=3E=2C_=3Clinux-mediatek=40lists=2Einfra?= =?unknown-8bit?q?dead=2Eorg=3E=2C_=3Clinux-kernel=40vger=2Ekernel=2Eorg=3E?= =?unknown-8bit?q?=2C_=3CProject=5FGlobal=5FChrome=5FUpstream=5FGroup=40medi?= =?unknown-8bit?q?atek=2Ecom=3E=2C_Guodong_Liu_=3Cguodong=2Eliu=40mediatek?= =?unknown-8bit?q?=2Ecom=3E?= Subject: [PATCH v1 2/4] pinctrl: add drive for I2C related pins on mt8192 Date: Wed, 8 Jun 2022 13:39:07 +0800 Message-ID: <20220608053909.1252-3-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220608053909.1252-1-guodong.liu@mediatek.com> References: <20220608053909.1252-1-guodong.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_224218_566395_24225601 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch provides the advanced drive raw data setting version for I2C used pins on mt8192 Signed-off-by: Guodong Liu --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 31 +++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 9faf7001369d..d11ff5519e1e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1259,6 +1259,32 @@ static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), }; +static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] = { + PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 0, 5), + PIN_FIELD_BASE(90, 90, 2, 0x0040, 0x10, 5, 5), + + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3), +}; + static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] = { PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1), PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1), @@ -1357,6 +1383,7 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8192_pin_r1_range), [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8192_pin_e1e0en_range), [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8192_pin_e0_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8192_pin_drv_adv_range), [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8192_pin_e1_range), }; @@ -1376,8 +1403,8 @@ static const struct mtk_pin_soc mt8192_data = { .drive_get = mtk_pinconf_drive_get_rev1, .adv_pull_get = mtk_pinconf_adv_pull_get, .adv_pull_set = mtk_pinconf_adv_pull_set, - .adv_drive_get = mtk_pinconf_adv_drive_get, - .adv_drive_set = mtk_pinconf_adv_drive_set, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, }; static const struct of_device_id mt8192_pinctrl_of_match[] = { From patchwork Wed Jun 8 05:39:08 2022 Content-Type: text/plain; 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Tue, 07 Jun 2022 22:41:59 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 7 Jun 2022 22:39:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 13:39:48 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 8 Jun 2022 13:39:46 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: =?unknown-8bit?q?Sean_Wang_=3Csean=2Ewang=40mediatek=2Ecom=3E=2C_Zhiyong?= =?unknown-8bit?q?_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_N=EDcolas_F_?= =?unknown-8bit?q?=2E_R_=2E_A_=2E_Prado_=3Cnfraprado=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_=3Clinux-gpio=40vger=2Ekernel=2Eorg=3E=2C_=3Cdevicetree?= =?unknown-8bit?q?=40vger=2Ekernel=2Eorg=3E=2C_=3Clinux-arm-kernel=40lists?= =?unknown-8bit?q?=2Einfradead=2Eorg=3E=2C_=3Clinux-mediatek=40lists=2Einfra?= =?unknown-8bit?q?dead=2Eorg=3E=2C_=3Clinux-kernel=40vger=2Ekernel=2Eorg=3E?= =?unknown-8bit?q?=2C_=3CProject=5FGlobal=5FChrome=5FUpstream=5FGroup=40medi?= =?unknown-8bit?q?atek=2Ecom=3E=2C_Guodong_Liu_=3Cguodong=2Eliu=40mediatek?= =?unknown-8bit?q?=2Ecom=3E?= Subject: [PATCH v1 3/4] pinctrl: mediatek: add rsel setting on mt8192 Date: Wed, 8 Jun 2022 13:39:08 +0800 Message-ID: <20220608053909.1252-4-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220608053909.1252-1-guodong.liu@mediatek.com> References: <20220608053909.1252-1-guodong.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_224203_451595_28356C75 X-CRM114-Status: GOOD ( 10.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org I2C pins's resistance value can be controlled by rsel register. This patch provides rsel (resistance selection) setting on mt8192 Signed-off-by: Guodong Liu --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 204 ++++++++++++++-------- 1 file changed, 134 insertions(+), 70 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index d11ff5519e1e..1486c141ee8c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1285,73 +1285,140 @@ static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] = { PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3), }; -static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] = { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 1), +static const struct mtk_pin_field_calc mt8192_pin_rsel_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 2), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 2), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 2), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 2), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 2), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 2), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 2), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 2), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 2), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 2), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 2), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 2), }; -static const struct mtk_pin_field_calc mt8192_pin_e0_range[] = { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 1, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 19, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 16, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 4, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 13, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 1, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 10, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 28, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 7, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 25, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 4, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 22, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 1, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 4, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 4, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 10, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 1, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 4, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 1, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 7, 1), -}; - -static const struct mtk_pin_field_calc mt8192_pin_e1_range[] = { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 2, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 20, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 17, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 5, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 14, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 11, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 29, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 8, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 26, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 5, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 23, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 2, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 5, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 5, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 11, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 2, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 5, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 2, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 8, 1), +static const unsigned int mt8192_pull_type[] = { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PU_PD_TYPE,/*67*/ + MTK_PULL_PU_PD_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/ + MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*118*/ MTK_PULL_PU_PD_RSEL_TYPE,/*119*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*120*/ MTK_PULL_PU_PD_RSEL_TYPE,/*121*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*122*/ MTK_PULL_PU_PD_RSEL_TYPE,/*123*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*124*/ MTK_PULL_PU_PD_RSEL_TYPE,/*125*/ + MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_TYPE,/*127*/ + MTK_PULL_PU_PD_TYPE,/*128*/ MTK_PULL_PU_PD_TYPE,/*129*/ + MTK_PULL_PU_PD_TYPE,/*130*/ MTK_PULL_PU_PD_TYPE,/*131*/ + MTK_PULL_PU_PD_TYPE,/*132*/ MTK_PULL_PU_PD_TYPE,/*133*/ + MTK_PULL_PU_PD_TYPE,/*134*/ MTK_PULL_PU_PD_TYPE,/*135*/ + MTK_PULL_PU_PD_TYPE,/*136*/ MTK_PULL_PU_PD_TYPE,/*137*/ + MTK_PULL_PU_PD_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_TYPE,/*143*/ + MTK_PULL_PU_PD_TYPE,/*144*/ MTK_PULL_PU_PD_TYPE,/*145*/ + MTK_PULL_PU_PD_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/ + MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/ + MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/ + MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/ + MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/ + MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*160*/ MTK_PULL_PU_PD_RSEL_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/ + MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/ + MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PUPD_R1R0_TYPE,/*183*/ + MTK_PULL_PUPD_R1R0_TYPE,/*184*/ MTK_PULL_PUPD_R1R0_TYPE,/*185*/ + MTK_PULL_PUPD_R1R0_TYPE,/*186*/ MTK_PULL_PUPD_R1R0_TYPE,/*187*/ + MTK_PULL_PUPD_R1R0_TYPE,/*188*/ MTK_PULL_PUPD_R1R0_TYPE,/*189*/ + MTK_PULL_PUPD_R1R0_TYPE,/*190*/ MTK_PULL_PUPD_R1R0_TYPE,/*191*/ + MTK_PULL_PUPD_R1R0_TYPE,/*192*/ MTK_PULL_PUPD_R1R0_TYPE,/*193*/ + MTK_PULL_PUPD_R1R0_TYPE,/*194*/ MTK_PULL_PU_PD_TYPE,/*195*/ + MTK_PULL_PU_PD_TYPE,/*196*/ MTK_PULL_PU_PD_TYPE,/*197*/ + MTK_PULL_PU_PD_TYPE,/*198*/ MTK_PULL_PU_PD_TYPE,/*199*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*200*/ MTK_PULL_PU_PD_RSEL_TYPE,/*201*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*202*/ MTK_PULL_PU_PD_RSEL_TYPE,/*203*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*204*/ MTK_PULL_PU_PD_RSEL_TYPE,/*205*/ + MTK_PULL_PU_PD_TYPE,/*206*/ MTK_PULL_PU_PD_TYPE,/*207*/ + MTK_PULL_PU_PD_TYPE,/*208*/ MTK_PULL_PU_PD_TYPE,/*209*/ + MTK_PULL_PU_PD_TYPE,/*210*/ MTK_PULL_PU_PD_TYPE,/*211*/ + MTK_PULL_PU_PD_TYPE,/*212*/ MTK_PULL_PU_PD_TYPE,/*213*/ + MTK_PULL_PU_PD_TYPE,/*214*/ MTK_PULL_PU_PD_TYPE,/*215*/ + MTK_PULL_PU_PD_TYPE,/*216*/ MTK_PULL_PU_PD_TYPE,/*217*/ + MTK_PULL_PU_PD_TYPE,/*218*/ MTK_PULL_PU_PD_TYPE,/*219*/ }; @@ -1381,10 +1448,8 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8192_pin_pupd_range), [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8192_pin_r0_range), [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8192_pin_r1_range), - [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8192_pin_e1e0en_range), - [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8192_pin_e0_range), [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8192_pin_drv_adv_range), - [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8192_pin_e1_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8192_pin_rsel_range), }; static const struct mtk_pin_soc mt8192_data = { @@ -1394,6 +1459,7 @@ static const struct mtk_pin_soc mt8192_data = { .ngrps = ARRAY_SIZE(mtk_pins_mt8192), .base_names = mt8192_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt8192_pinctrl_register_base_names), + .pull_type = mt8192_pull_type, .eint_hw = &mt8192_eint_hw, .nfuncs = 8, .gpio_m = 0, @@ -1401,8 +1467,6 @@ static const struct mtk_pin_soc mt8192_data = { .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, .adv_drive_get = mtk_pinconf_adv_drive_get_raw, .adv_drive_set = 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=?unknown-8bit?q?=2Ecom=3E?= Subject: [PATCH v1 4/4] pinctrl: mediatek: fix the pinconf definition of some GPIO pins Date: Wed, 8 Jun 2022 13:39:09 +0800 Message-ID: <20220608053909.1252-5-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220608053909.1252-1-guodong.liu@mediatek.com> References: <20220608053909.1252-1-guodong.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_224218_568246_29512B78 X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove pin definitions that do not support the R0 & R1 pinconfig property Signed-off-by: Guodong Liu --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 60 ----------------------- 1 file changed, 60 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 1486c141ee8c..13784a92a536 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1107,24 +1107,10 @@ static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = { PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 31, 1), PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 31, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 31, 1), PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1), @@ -1137,12 +1123,6 @@ static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = { PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 31, 1), }; static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = { @@ -1164,24 +1144,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = { PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1), PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1), PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1), @@ -1194,12 +1160,6 @@ static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = { PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 1), }; static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { @@ -1221,24 +1181,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1), PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1), PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1), @@ -1251,12 +1197,6 @@ static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 3, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 7, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 1, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 3, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 1, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), }; static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] = {