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(unknown [104.36.31.105]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a312.dreamhost.com (Postfix) with ESMTPSA id 4LKh1X6kknz2W; Fri, 10 Jun 2022 19:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1654912977; bh=/EKdKMYQlkED0wOnzGNnwnCPCW0oniU3CZiV+Eb68zY=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=dxEqCjI26GaFGsxkgBCadqrLK7MZlXuCnEzoDYj495HaKx7gquDHEjOXjUxWUCYmI aeSZT4tDf9Y3e2QCnFfr9nN1xkWKrj7VkVYjqD87tkOO95/Iv+eJGwxfpVMpS4RP/a ZCiW5aySICRx/cUFKi1z9IDRLxlntPIOKt4bc5oFFIM5iI1LrgUqFs7QvPl5VRbxu0 Cnw0px3YUaAJisBIvSL90U6KB0OtYPwjYS7UFHxzDOCOT364G4r993vfY227k1HSOU ghVs0UVeLeLjrMXWtTxHW4D5HIxlBoaek55S0vk/dUInbPoXLZ8xIY6ZAoVR+fMKvT YSB0OoF9rB4Jw== From: Davidlohr Bueso To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, a.manzanares@samsung.com, dave@stgolabs.net Subject: [PATCH] cxl/port: Check for sane CXL.io values for device DVSEC Date: Fri, 10 Jun 2022 19:02:46 -0700 Message-Id: <20220611020246.140637-1-dave@stgolabs.net> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org These must always be set in the capability and control words. Explicitly check for these and identify any bogus setups while doing cxl_hdm_decode_init(). Signed-off-by: Davidlohr Bueso --- drivers/cxl/core/pci.c | 14 ++++++++++++-- drivers/cxl/cxlpci.h | 2 ++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c4c99ff7b55e..c69be8f120fc 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -367,12 +367,22 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm) if (rc) return rc; + if (!(cap & CXL_DVSEC_IO_CAPABLE)) { + dev_dbg(dev, "Not IO Capable\n"); + return -ENXIO; + } + + if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + dev_dbg(dev, "Not MEM Capable\n"); + return -ENXIO; + } + rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); if (rc) return rc; - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { - dev_dbg(dev, "Not MEM Capable\n"); + if (!(ctrl & CXL_DVSEC_IO_ENABLE)) { + dev_dbg(dev, "Not IO Enable\n"); return -ENXIO; } diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index fce1c11729c2..845f59288dc3 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -18,9 +18,11 @@ /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 #define CXL_DVSEC_CAP_OFFSET 0xA +#define CXL_DVSEC_IO_CAPABLE BIT(1) #define CXL_DVSEC_MEM_CAPABLE BIT(2) #define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) #define CXL_DVSEC_CTRL_OFFSET 0xC +#define CXL_DVSEC_IO_ENABLE BIT(1) #define CXL_DVSEC_MEM_ENABLE BIT(2) #define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) #define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))