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[213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:30 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 1/7] media: cedrus: h265: Fix flag name Date: Mon, 20 Jun 2022 19:55:11 +0200 Message-Id: <20220620175517.648767-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Bit 21 in register 0x24 (slice header info 1) actually represents negated version of low delay flag. This can be seen in vendor Cedar library source code. While this flag is not part of the standard, it can be found in reference HEVC implementation. Fix macro name and change it to flag. Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support") Signed-off-by: Jernej Skrabec --- drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 4 +++- drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 3 +-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 7b67cb4621cf..9ee6f0f111e5 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -576,7 +576,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) | VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) | - VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) | VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) | VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) | VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta); @@ -589,6 +588,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, slice_params->flags); + if (decode_params->num_poc_st_curr_after == 0) + reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_NOT_LOW_DELAY; + cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h index bdb062ad8682..d81f7513ade0 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h @@ -377,13 +377,12 @@ #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23) #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22) +#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_NOT_LOW_DELAY BIT(21) #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \ SHIFT_AND_MASK_BITS(v, 31, 28) #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \ SHIFT_AND_MASK_BITS(v, 27, 24) -#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \ - ((v) ? BIT(21) : 0) #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \ SHIFT_AND_MASK_BITS(v, 20, 16) #define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \ From patchwork Mon Jun 20 17:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12888002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 850C9CCA47F for ; Mon, 20 Jun 2022 17:55:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244327AbiFTRzk (ORCPT ); Mon, 20 Jun 2022 13:55:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244355AbiFTRzf (ORCPT ); Mon, 20 Jun 2022 13:55:35 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 937E719C13; Mon, 20 Jun 2022 10:55:33 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id g27so9043791wrb.10; Mon, 20 Jun 2022 10:55:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c+lhmhRazPbCiO0ZinItgn/yvpq/qsLzRHWrKJfMBAU=; b=ij7bpM7fYgafh4dGUzxUNkZ8mBe+1r3nO44hxCPnlMgcixxMJdfdSiXAdXE15WMCLM AyrqEh6M+p4d899WbwMSR4K1RQjNL5aRVO7l3tv9cR9JLGot1WiSXOLEbiRltLC+RO2+ PjAB3k7Kmhb4cHJueB/5F93qKDW8F4c03ykyisyEAs0apL6U6sI8E697cwDod0mwN3OB iRbkQyuE5SLRr75UEpV1KHoFr/k0KJfHAUBxKLMz0XPxkZG6MRWzsCvWcR+/uX+N8LLy qmR7mEMzZ6RcUeYBNDp1NSaL/BxEowh8eAc0djSZXcY/U+/uqkn9eEPONFRPL2r8jtTR L0bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c+lhmhRazPbCiO0ZinItgn/yvpq/qsLzRHWrKJfMBAU=; b=RlMnclPRKBJmTu00EWc16JwvaIG76LnKWvApYm8kKlMbt/eJFsKJg1Pqm/y+0HXvWr W43gpdJygwsxPTgxeKsjcUeoNSYZYv7LQ50Wk3C3PPkjSRSdMzyhb25696zWTWNeOFA/ LnW0Rj7fMr4LNfS8oh5gZUPKzHogfMJT45nJQYsyF3kGcKIUwYk3VKzXJ0SN77pm/QvU 3teZg6qqPEG6lxaZIXf02MuA2Yun7iRhHIcM9yZPEjAG6FBN+nkWUgO1nxekuAWfd22A UpolPidNM3wQeF3K60h7QMjxUogpVOt0eaOlFmJ10/158AD+VCLySPiYXQybniUkqs4j hSOg== X-Gm-Message-State: AJIora/ExAKe9pazhBYTbMmaqRBaNePVCJqOu3c7KsdNTV0eD7MCb35A a5XgwhYxFPBGpGILeuDbzO0= X-Google-Smtp-Source: AGRyM1ugVC+G+EV+zF7RaG1caUz4KMQyumBWu+cN6/oYPJe14QiJ+H9HFyA6JwaBXtZLXPwI5NYlbw== X-Received: by 2002:adf:f84b:0:b0:21b:8e43:b8ba with SMTP id d11-20020adff84b000000b0021b8e43b8bamr7141670wrq.155.1655747732210; Mon, 20 Jun 2022 10:55:32 -0700 (PDT) Received: from kista.localdomain (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:31 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 2/7] media: cedrus: h265: Fix logic for not low delay flag Date: Mon, 20 Jun 2022 19:55:12 +0200 Message-Id: <20220620175517.648767-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Now that we know real purpose of "not low delay" flag, logic for applying this flag should be fixed too. According to vendor and reference implementation, low delay is signaled when POC of current frame is lower than POC of at least one reference of a slice. Implement mentioned logic and invert it to conform to flag meaning. Also don't apply flag for I frames. They don't have any reference. This fixes decoding of 3 reference bitstreams. Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support") Signed-off-by: Jernej Skrabec --- .../staging/media/sunxi/cedrus/cedrus_h265.c | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 9ee6f0f111e5..46119912c387 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -301,6 +301,31 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx, } } +static int cedrus_h265_is_low_delay(struct cedrus_run *run) +{ + const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_hevc_dpb_entry *dpb; + s32 poc; + int i; + + slice_params = run->h265.slice_params; + poc = run->h265.decode_params->pic_order_cnt_val; + dpb = run->h265.decode_params->dpb; + + for (i = 0; i < slice_params->num_ref_idx_l0_active_minus1 + 1; i++) + if (dpb[slice_params->ref_idx_l0[i]].pic_order_cnt_val > poc) + return 1; + + if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_B) + return 0; + + for (i = 0; i < slice_params->num_ref_idx_l1_active_minus1 + 1; i++) + if (dpb[slice_params->ref_idx_l1[i]].pic_order_cnt_val > poc) + return 1; + + return 0; +} + static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { @@ -588,7 +613,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, slice_params->flags); - if (decode_params->num_poc_st_curr_after == 0) + if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I && !cedrus_h265_is_low_delay(run)) reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_NOT_LOW_DELAY; cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); From patchwork Mon Jun 20 17:55:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12888003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B2FC43334 for ; Mon, 20 Jun 2022 17:55:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244492AbiFTRzl (ORCPT ); Mon, 20 Jun 2022 13:55:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244357AbiFTRzf (ORCPT ); Mon, 20 Jun 2022 13:55:35 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA30E19C2F; Mon, 20 Jun 2022 10:55:34 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id q9so15692682wrd.8; Mon, 20 Jun 2022 10:55:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oDUyLN4Pryhtw9N4iCwOXaC7LwBCPSfNWeiXJOlMPkg=; b=j/IwIO3a0ts7j8gthEBmCMeJ6vuYBo7HD3mAfvcgjHRCoMpwlDgxlGwUcshfULkvl4 ux3FYylaS1HAhyCbCRfcmlKK1iAcVIKdHj+yrmEOFmbCiXy6V4a+wtYGsPZNyzriN7gj qibFoseY20ti4Hsd7U+99+ibAKfJP5EBKJdU/FlP9ttzN48lcL6Bq6/z2ymORhORcBwJ BXN+XPG9XT/9ERCFxVBGFR0BZ0k4DrArLCAsL4vyu6pZqBPvD491gJMHWamNmvy2eHEg mgeSu4G8QcNhmdcgLErLyKtI1w09RHh+nQTOnlXS8hnZ04a5zgRLlkN+ELVwpZTw1k7V lzEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oDUyLN4Pryhtw9N4iCwOXaC7LwBCPSfNWeiXJOlMPkg=; b=oqSF9K8yPZRDZmher/VL7emOa3TGo981XfDiVwQKUqoAqUePFlNvg25t4GXvsBx/sd 3LS2k5Wm8PVFgQuSoAjbzcYxqLMGDNbKCa4G4y5IblKrgNIXiVcId2pBvbopaiG1KdCo K52YHFQdGR6SuubieQ/Bg8DxYO/s2Xg7AKHhtMkXrQG1NfbMnvr5ixD13BFkjO7L5o6v 6iI3m/OM/JQOaNnmCaWnyFTfZL5oOBmklMhT6IcmrVsuETw55BBtoWL/LaO3a2qwi2aN 8Ph99I3v0rfbvFwwdoShV7LvwWnczcs4Rr2rb6mhZA+juz0loj81s4pLs6Xcu8SP0Tcv cdgQ== X-Gm-Message-State: AJIora98Qg9RXINEMB8DgMge9ex2dX4dhIbG523okHDAgqGOSFQ5EBEQ TQeojTgl61U3zkCNaE4TP08= X-Google-Smtp-Source: AGRyM1vzYBSQFI6blw/ovMZUI5R79+0X2OmRbBajL6gKqGWCQJxqwYvaZKB0wzV66Sh9rKiSy4aM9w== X-Received: by 2002:a5d:5c08:0:b0:219:e5de:72af with SMTP id cc8-20020a5d5c08000000b00219e5de72afmr23720384wrb.513.1655747733393; Mon, 20 Jun 2022 10:55:33 -0700 (PDT) Received: from kista.localdomain (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:33 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 3/7] media: cedrus: Improve error messages for controls Date: Mon, 20 Jun 2022 19:55:13 +0200 Message-Id: <20220620175517.648767-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Currently error messages when control creation fails are very sparse. Granted, user should never observe them. However, developer working on codecs can. In such cases additional information like which control creation failed and error number are very useful. Expand error messages with additional info. Signed-off-by: Jernej Skrabec Reviewed-by: Ezequiel Garcia --- drivers/staging/media/sunxi/cedrus/cedrus.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index b12219123a6b..99c87319d2b4 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -242,7 +242,8 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) v4l2_ctrl_handler_init(hdl, CEDRUS_CONTROLS_COUNT); if (hdl->error) { v4l2_err(&dev->v4l2_dev, - "Failed to initialize control handler\n"); + "Failed to initialize control handler: %d\n", + hdl->error); return hdl->error; } @@ -257,7 +258,9 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) NULL); if (hdl->error) { v4l2_err(&dev->v4l2_dev, - "Failed to create new custom control\n"); + "Failed to create %s control: %d\n", + v4l2_ctrl_get_name(cedrus_controls[i].cfg.id), + hdl->error); v4l2_ctrl_handler_free(hdl); kfree(ctx->ctrls); From patchwork Mon Jun 20 17:55:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12888004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CBC2C433EF for ; Mon, 20 Jun 2022 17:55:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244534AbiFTRzn (ORCPT ); Mon, 20 Jun 2022 13:55:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243937AbiFTRzh (ORCPT ); Mon, 20 Jun 2022 13:55:37 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1F8F15A12; Mon, 20 Jun 2022 10:55:35 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id i10so11943738wrc.0; Mon, 20 Jun 2022 10:55:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v1dAKvkkLglJ9uDTaYyQQ++nei7aPjDhg2NRvQrXzs4=; b=PXCuyOY2oGeqe/2u5291BK7g8iwGzcFWgQdxNTLpEHH5MebO0ENGpfV/osCNwwbFLr PKswyNH2KUJXyRp8MkFMIHG3szK5meQQGQxkkmkDvj5tkGmFM3Nfm3qEs1lWk3xvEbko X5yzXkjjtxNIX06ku0aHcKOIl9CcOCA8Q21DfiNxHRy2VsjOIZqYBLKYJtP7mU+AzgpP pxtvWwWsggyw6c4kkQtrSVDbmQrWL9XTalf5tj2tZZzir0tbyoxC7pY1Z9Q/M1biDvGt SGAUEuBoS1obEqxsf+jhO5uTNI8LbSb+MrgIonIyKDgKdZD4FO5nAwYqGNDK1odGUyj3 GDJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1dAKvkkLglJ9uDTaYyQQ++nei7aPjDhg2NRvQrXzs4=; b=tQcoYahw2kK1bdClDw3XOievBYUvuTgiOBMgVLo2oDdvA4hxkH7eGcwa5fzQw+eOh4 WTVN/xtuzRR6VnLIcVqkRol21wzxnaZk0Y0YC0IQEd7cF4HW87sby5Ml+5x5d2cQC65n gLpIjDxDbSm+bEV7xDUCETwx7UShYWkNQepxsiWCA7qaw5lZ4dY1uiTos8VlakHNNkjk QbytuehRJDmZgs3SsV+fvVFEFUfrMHEEhxmwkD9HpwkuSQRAzV2YBb2T5EFsprTtX7gv ReM/HlX7Wwg2U2nuQH/Ug8cV9KtdsD1E/r1tW6FyfrE9uNPEeFHeXx9Ir2rdwa5XzmOY eVfg== X-Gm-Message-State: AJIora88pKmPnuBGAK2O6cvDUixQ+UjFOUUIXFA+6AQBJHIMAQwuqNMA IUBqmS7Rz9DERijuzRm9QIQ= X-Google-Smtp-Source: AGRyM1vyZHQwsEYRHeXGomkhfnEuVX5Kk/SEGY68XLVA2CO6m/m9uFmxMRCt3nyAUTLTrl4yqMbXuA== X-Received: by 2002:a05:6000:ca:b0:21b:8082:7518 with SMTP id q10-20020a05600000ca00b0021b80827518mr17634297wrx.124.1655747734550; Mon, 20 Jun 2022 10:55:34 -0700 (PDT) Received: from kista.localdomain (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:34 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 4/7] media: cedrus: Add error handling for failed setup Date: Mon, 20 Jun 2022 19:55:14 +0200 Message-Id: <20220620175517.648767-5-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org During decoding setup stage for complex codecs like HEVC driver can detect inconsistent values in controls or some other task, like allocating memory, can fail. Currently setup stage has no way of signalling error. Change return type of setup callback to int and if returned value is not zero, skip decoding and finish job immediately with error flag. While currently there is only one place when setup can fail, it's expected that there will be more such cases in the future, when HEVC decoding is improved. Signed-off-by: Jernej Skrabec Reviewed-by: Ezequiel Garcia --- drivers/staging/media/sunxi/cedrus/cedrus.h | 2 +- .../staging/media/sunxi/cedrus/cedrus_dec.c | 21 ++++++++++++++----- .../staging/media/sunxi/cedrus/cedrus_h264.c | 5 +++-- .../staging/media/sunxi/cedrus/cedrus_h265.c | 8 +++---- .../staging/media/sunxi/cedrus/cedrus_mpeg2.c | 4 +++- .../staging/media/sunxi/cedrus/cedrus_vp8.c | 5 +++-- 6 files changed, 30 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index 3bc094eb497f..d2b697a9ded2 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -162,7 +162,7 @@ struct cedrus_dec_ops { void (*irq_clear)(struct cedrus_ctx *ctx); void (*irq_disable)(struct cedrus_ctx *ctx); enum cedrus_irq_status (*irq_status)(struct cedrus_ctx *ctx); - void (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run); + int (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run); int (*start)(struct cedrus_ctx *ctx); void (*stop)(struct cedrus_ctx *ctx); void (*trigger)(struct cedrus_ctx *ctx); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c index aabe6253078e..b0944abaacbd 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c @@ -28,6 +28,7 @@ void cedrus_device_run(void *priv) struct cedrus_dev *dev = ctx->dev; struct cedrus_run run = {}; struct media_request *src_req; + int error; run.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); run.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); @@ -89,16 +90,26 @@ void cedrus_device_run(void *priv) cedrus_dst_format_set(dev, &ctx->dst_fmt); - dev->dec_ops[ctx->current_codec]->setup(ctx, &run); + error = dev->dec_ops[ctx->current_codec]->setup(ctx, &run); + if (error) + v4l2_err(&ctx->dev->v4l2_dev, + "Failed to setup decoding job: %d\n", error); /* Complete request(s) controls if needed. */ if (src_req) v4l2_ctrl_request_complete(src_req, &ctx->hdl); - dev->dec_ops[ctx->current_codec]->trigger(ctx); + /* Trigger decoding if setup went well, bail out otherwise. */ + if (!error) { + dev->dec_ops[ctx->current_codec]->trigger(ctx); - /* Start the watchdog timer. */ - schedule_delayed_work(&dev->watchdog_work, - msecs_to_jiffies(2000)); + /* Start the watchdog timer. */ + schedule_delayed_work(&dev->watchdog_work, + msecs_to_jiffies(2000)); + } else { + v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, + ctx->fh.m2m_ctx, + VB2_BUF_STATE_ERROR); + } } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c index d8fb93035470..c345e67ba9bc 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c @@ -493,8 +493,7 @@ static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) reg & ~VE_H264_CTRL_INT_MASK); } -static void cedrus_h264_setup(struct cedrus_ctx *ctx, - struct cedrus_run *run) +static int cedrus_h264_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { struct cedrus_dev *dev = ctx->dev; @@ -510,6 +509,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, cedrus_write_frame_list(ctx, run); cedrus_set_params(ctx, run); + + return 0; } static int cedrus_h264_start(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 46119912c387..cfde4ccf6011 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -326,8 +326,7 @@ static int cedrus_h265_is_low_delay(struct cedrus_run *run) return 0; } -static void cedrus_h265_setup(struct cedrus_ctx *ctx, - struct cedrus_run *run) +static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { struct cedrus_dev *dev = ctx->dev; const struct v4l2_ctrl_hevc_sps *sps; @@ -385,8 +384,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); if (!ctx->codec.h265.mv_col_buf) { ctx->codec.h265.mv_col_buf_size = 0; - // TODO: Abort the process here. - return; + return -ENOMEM; } } @@ -703,6 +701,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, /* Enable appropriate interruptions. */ cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK); + + return 0; } static int cedrus_h265_start(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c index 5dad2f296c6d..4cfc4a3c8a7f 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c @@ -48,7 +48,7 @@ static void cedrus_mpeg2_irq_disable(struct cedrus_ctx *ctx) cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); } -static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) +static int cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { const struct v4l2_ctrl_mpeg2_sequence *seq; const struct v4l2_ctrl_mpeg2_picture *pic; @@ -185,6 +185,8 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) VE_DEC_MPEG_CTRL_MC_CACHE_EN; cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); + + return 0; } static void cedrus_mpeg2_trigger(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_vp8.c b/drivers/staging/media/sunxi/cedrus/cedrus_vp8.c index f4016684b32d..3f750d1795b6 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_vp8.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_vp8.c @@ -651,8 +651,7 @@ static void cedrus_vp8_irq_disable(struct cedrus_ctx *ctx) reg & ~VE_H264_CTRL_INT_MASK); } -static void cedrus_vp8_setup(struct cedrus_ctx *ctx, - struct cedrus_run *run) +static int cedrus_vp8_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { const struct v4l2_ctrl_vp8_frame *slice = run->vp8.frame_params; struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; @@ -855,6 +854,8 @@ static void cedrus_vp8_setup(struct cedrus_ctx *ctx, ctx->codec.vp8.last_sharpness_level = slice->lf.sharpness_level; } + + return 0; } static int cedrus_vp8_start(struct cedrus_ctx *ctx) From patchwork Mon Jun 20 17:55:15 2022 Content-Type: text/plain; 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[213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:35 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 5/7] media: cedrus: h265: Add a couple of error checks Date: Mon, 20 Jun 2022 19:55:15 +0200 Message-Id: <20220620175517.648767-6-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Now that we have infrastructure for reporting errors, let's add two checks, which will make sure slice can be actually decoded. Signed-off-by: Jernej Skrabec Reviewed-by: Ezequiel Garcia --- drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index cfde4ccf6011..99020b9f9ff8 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -435,9 +435,17 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) * instead of start of slice data. Padding is 8 bits at most (one bit set to 1 and * at most seven bits set to 0), so we have to inspect only one byte before slice data. */ + + if (slice_params->data_byte_offset == 0) + return -EOPNOTSUPP; + padding = (u8 *)vb2_plane_vaddr(&run->src->vb2_buf, 0) + slice_params->data_byte_offset - 1; + /* at least one bit must be set in that byte */ + if (*padding == 0) + return -EINVAL; + for (count = 0; count < 8; count++) if (*padding & (1 << count)) break; From patchwork Mon Jun 20 17:55:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12888005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8AF1C433EF for ; Mon, 20 Jun 2022 17:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244538AbiFTRzo (ORCPT ); Mon, 20 Jun 2022 13:55:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244442AbiFTRzj (ORCPT ); Mon, 20 Jun 2022 13:55:39 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A44A15A29; Mon, 20 Jun 2022 10:55:38 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id m39-20020a05600c3b2700b0039c511ebbacso8132086wms.3; Mon, 20 Jun 2022 10:55:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rO76farMqYrPQC4ew78x4uRO3kIuRntTwzkVO3g3BmE=; b=IXKYt1GNB0skST+g+G4WX5y6frV6Y4HqH2GhmT+UmjHsf9n/eI/8mQ/1U9DblJ6nA+ EuQQBR7A64ljTuDVW0sTn1xiDxxQCPWO8F5rfuzYDMXiCFM+o5ZCoJHN9uhhUWbNC/ma Cy12wOo2F6wvVmCZc8uA73rbiBazH+msWsg66pnnXJhV3hyoRqDw8eVrI/KkeWDFyNoj JUHYPoUJjygpC98Hd13+KqHXDnQEkd5ywSFlDtsbDwPzT5Tciop659ZSJ3q2yNV3IP+7 KaaYG2DOOU60fAyt7bmRps3R+IZzONdJS5MaxDw4ryX58jj8QbNzXmXO+wmzKVLghsqc dyBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rO76farMqYrPQC4ew78x4uRO3kIuRntTwzkVO3g3BmE=; b=Q8dapEcXeDZz/XPtLxF9JSaaYLWYdvDgc2WXdWYKgE+8TECsB/MwkwiZoCfOmz8RXe Mpt4sCAEic2twwtWxMMRtdjeCSMjGZLAgNdonLQToRs7EIMtRmP7Qgt3GZBHgVy5On8j Nq1s2iePR3XS6RG/cCDyzUKYsfAUqEH9uHdgqEcoxrHhSbEa02LEa7k3SVzk7Tzzo5tx 3MYrGyGoFPflFjJ9f8V58MNbUhKWrj2T7Sb7f/zrDnpG7FJrYE8gaYl7rttpMzCA4OIj IIMzX5VuawHo/C9DffAzE+/Jb031W0S/0KgrxmWxWRLjZ+3QdFnuojstaSu0aSiOm2eG 4Lcg== X-Gm-Message-State: AJIora8dSZ/4lwwjPwvKtJ3tzrN/OQIYctakPdWAuMBVybw2GIuYQCpT dh/1oSkBIOy7uFRVxxq54E7VPLXZZiM= X-Google-Smtp-Source: AGRyM1u30Dw+JFAP13t7yhgHTvIDNuEJxA8aQ+DfNlPldZrFipM6Pgrn21E14dvHe/90gjXmt5wvtA== X-Received: by 2002:a1c:4e15:0:b0:3a0:1990:afeb with SMTP id g21-20020a1c4e15000000b003a01990afebmr4215164wmh.137.1655747736907; Mon, 20 Jun 2022 10:55:36 -0700 (PDT) Received: from kista.localdomain (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:36 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 6/7] media: cedrus: Add helper for determining number of elements Date: Mon, 20 Jun 2022 19:55:16 +0200 Message-Id: <20220620175517.648767-7-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Now that controls can be dynamic arrays, we need to know how many elements are in such array. Add a helper for that. Signed-off-by: Jernej Skrabec Reviewed-by: Ezequiel Garcia --- drivers/staging/media/sunxi/cedrus/cedrus.c | 11 +++++++++++ drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index 99c87319d2b4..b855e608885c 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -232,6 +232,17 @@ void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id) return NULL; } +u32 cedrus_get_num_of_controls(struct cedrus_ctx *ctx, u32 id) +{ + unsigned int i; + + for (i = 0; ctx->ctrls[i]; i++) + if (ctx->ctrls[i]->id == id) + return ctx->ctrls[i]->elems; + + return 0; +} + static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) { struct v4l2_ctrl_handler *hdl = &ctx->hdl; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index d2b697a9ded2..15a1bdbf6a1f 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -261,5 +261,6 @@ vb2_to_cedrus_buffer(const struct vb2_buffer *p) } void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id); +u32 cedrus_get_num_of_controls(struct cedrus_ctx *ctx, u32 id); #endif From patchwork Mon Jun 20 17:55:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12888007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7873ACCA47F for ; Mon, 20 Jun 2022 17:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243887AbiFTRzs (ORCPT ); Mon, 20 Jun 2022 13:55:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243537AbiFTRzl (ORCPT ); Mon, 20 Jun 2022 13:55:41 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2209115A12; Mon, 20 Jun 2022 10:55:40 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id l2-20020a05600c4f0200b0039c55c50482so8157934wmq.0; Mon, 20 Jun 2022 10:55:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tAdXoNtdZqSJlZ2MXfBBTjpRxVvfcVETXQY7JSHULjw=; b=kCil/b2YxMcI/LVYfQ4tU0txJcgYVmIuNNYvnya8s/clEL/VYeagXGh1qVkbHST8Nt GhFkQWXTAgWVPPOF2B9HqmAP10J8QqTJ0eY9IAzh7AuQrkrUI5huLrOOFb/8n1TpMshN mSGjRcLa74wXVrEscb1ZqL5jjejmsgxXAHpDJ3JWuJWHa6zNiIk/R3NmvlhK5msRgX5H xZ6AcErbOWWeEYrzD+JXr4PJPuH3q92sgKMu+JwVtA2O98jwupgp7K4JjFDJUwZW9IN4 fPife9qlUSz3tKMRXiG02OUY/Do1cCmp8cspKqU77NwKCpbr/FSnSTHkcWCi6k1+SjaN SNFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tAdXoNtdZqSJlZ2MXfBBTjpRxVvfcVETXQY7JSHULjw=; b=tOBxOt+nZdCzwFASoWgULdxptX1f1Nu22l3oxmrLfk7AV4k3Km/mUScHrKt/g0VCDb 4ryhXwePp0Mioh0nQreAid4quG/7TWvqBCVRLWDGu85NdIQz4HRXSd5OiyT7RiDUTo5g 1VEzC7U3Dcp3iAXF29R+6dpuPgGf32dck+0hw2G+KRVrZ6PyLQ+nD2WSH71E7Tjlla/C HBMmh2v+bAxrL1McTmYHvQ0vgV4UIR8J04njpG5fb9vXc+mT9Jyu++/Qv0jiPypBiI3z DsPyvVtegewzju/nk1gscp8/YCd0IWlj8dGNrtq1vsWM0n9tF65KfAYZG9VEgEvVvsUy 3YrA== X-Gm-Message-State: AJIora+hoLfcdnHpOy+XoMGfUvGmN3v0TCpsrN1gSZiWWpbINSze0fNc 4dW5Se/5ez5fdY2UyJaWVZU= X-Google-Smtp-Source: AGRyM1sTT+Qv9xeBDp8yh0jsfBs7Yt/BBq4EV52+NqOwKAeegtB6y0gszD0QF/AnQ01tSEnm0mICdA== X-Received: by 2002:a05:600c:1991:b0:39c:88ba:2869 with SMTP id t17-20020a05600c199100b0039c88ba2869mr25262485wmq.14.1655747738659; Mon, 20 Jun 2022 10:55:38 -0700 (PDT) Received: from kista.localdomain (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id 184-20020a1c02c1000000b0039db31f6372sm19620752wmc.2.2022.06.20.10.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 10:55:38 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, samuel@sholland.org Cc: mchehab@kernel.org, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 7/7] media: cedrus: h265: Implement support for tiles Date: Mon, 20 Jun 2022 19:55:17 +0200 Message-Id: <20220620175517.648767-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620175517.648767-1-jernej.skrabec@gmail.com> References: <20220620175517.648767-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tiles are last remaining unimplemented functionality for HEVC. Implement it. Signed-off-by: Jernej Skrabec Reviewed-by: Ezequiel Garcia --- drivers/staging/media/sunxi/cedrus/cedrus.c | 10 ++ drivers/staging/media/sunxi/cedrus/cedrus.h | 4 + .../staging/media/sunxi/cedrus/cedrus_dec.c | 4 + .../staging/media/sunxi/cedrus/cedrus_h265.c | 108 +++++++++++++++++- 4 files changed, 120 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index b855e608885c..960a0130cd62 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -189,6 +189,16 @@ static const struct cedrus_control cedrus_controls[] = { }, .codec = CEDRUS_CODEC_H265, }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS, + /* maximum 256 entry point offsets per slice */ + .dims = { 256 }, + .max = 0xffffffff, + .step = 1, + }, + .codec = CEDRUS_CODEC_H265, + }, { .cfg = { .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index 15a1bdbf6a1f..084193019350 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -81,6 +81,8 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_slice_params *slice_params; const struct v4l2_ctrl_hevc_decode_params *decode_params; const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; + const u32 *entry_points; + u32 entry_points_count; }; struct cedrus_vp8_run { @@ -146,6 +148,8 @@ struct cedrus_ctx { ssize_t mv_col_buf_unit_size; void *neighbor_info_buf; dma_addr_t neighbor_info_buf_addr; + void *entry_points_buf; + dma_addr_t entry_points_buf_addr; } h265; struct { unsigned int last_frame_p_type; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c index b0944abaacbd..3b6aa78a2985 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c @@ -75,6 +75,10 @@ void cedrus_device_run(void *priv) V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); run.h265.scaling_matrix = cedrus_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run.h265.entry_points = cedrus_find_control_data(ctx, + V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS); + run.h265.entry_points_count = cedrus_get_num_of_controls(ctx, + V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS); break; case V4L2_PIX_FMT_VP8_FRAME: diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 99020b9f9ff8..275fff1ab3a4 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -326,6 +326,65 @@ static int cedrus_h265_is_low_delay(struct cedrus_run *run) return 0; } +static void cedrus_h265_write_tiles(struct cedrus_ctx *ctx, + struct cedrus_run *run, + unsigned int ctb_addr_x, + unsigned int ctb_addr_y) +{ + const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_ctrl_hevc_pps *pps; + struct cedrus_dev *dev = ctx->dev; + const u32 *entry_points; + u32 *entry_points_buf; + int i, x, tx, y, ty; + + pps = run->h265.pps; + slice_params = run->h265.slice_params; + entry_points = run->h265.entry_points; + entry_points_buf = ctx->codec.h265.entry_points_buf; + + for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { + if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x) + break; + + x += pps->column_width_minus1[tx] + 1; + } + + for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { + if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y) + break; + + y += pps->row_height_minus1[ty] + 1; + } + + cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0)); + cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, + ((y + pps->row_height_minus1[ty]) << 16) | + ((x + pps->column_width_minus1[tx]) << 0)); + + if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) { + for (i = 0; i < slice_params->num_entry_point_offsets; i++) + entry_points_buf[i] = entry_points[i]; + } else { + for (i = 0; i < slice_params->num_entry_point_offsets; i++) { + if (tx + 1 >= pps->num_tile_columns_minus1 + 1) { + x = 0; + tx = 0; + y += pps->row_height_minus1[ty++] + 1; + } else { + x += pps->column_width_minus1[tx++] + 1; + } + + entry_points_buf[i * 4 + 0] = entry_points[i]; + entry_points_buf[i * 4 + 1] = 0x0; + entry_points_buf[i * 4 + 2] = (y << 16) | (x << 0); + entry_points_buf[i * 4 + 3] = + ((y + pps->row_height_minus1[ty]) << 16) | + ((x + pps->column_width_minus1[tx]) << 0); + } + } +} + static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { struct cedrus_dev *dev = ctx->dev; @@ -336,9 +395,11 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) const struct v4l2_hevc_pred_weight_table *pred_weight_table; unsigned int width_in_ctb_luma, ctb_size_luma; unsigned int log2_max_luma_coding_block_size; + unsigned int ctb_addr_x, ctb_addr_y; dma_addr_t src_buf_addr; dma_addr_t src_buf_end_addr; u32 chroma_log2_weight_denom; + u32 num_entry_point_offsets; u32 output_pic_list_index; u32 pic_order_cnt[2]; u8 *padding; @@ -350,6 +411,15 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) slice_params = run->h265.slice_params; decode_params = run->h265.decode_params; pred_weight_table = &slice_params->pred_weight_table; + num_entry_point_offsets = slice_params->num_entry_point_offsets; + + /* + * If entry points offsets are present, we should get them + * exactly the right amount. + */ + if (num_entry_point_offsets && + num_entry_point_offsets != run->h265.entry_points_count) + return -ERANGE; log2_max_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3 + @@ -416,12 +486,19 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); /* Coding tree block address */ - reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); - reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); + ctb_addr_x = slice_params->slice_segment_addr % width_in_ctb_luma; + ctb_addr_y = slice_params->slice_segment_addr / width_in_ctb_luma; + reg = VE_DEC_H265_DEC_CTB_ADDR_X(ctb_addr_x); + reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(ctb_addr_y); cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); - cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); - cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); + if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) || + (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) { + cedrus_h265_write_tiles(ctx, run, ctb_addr_x, ctb_addr_y); + } else { + cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); + cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); + } /* Clear the number of correctly-decoded coding tree blocks. */ if (ctx->fh.m2m_ctx->new_frame) @@ -548,7 +625,9 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, pps->flags); - /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ + reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED, + V4L2_HEVC_PPS_FLAG_TILES_ENABLED, + pps->flags); reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, @@ -626,12 +705,14 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + pred_weight_table->delta_chroma_log2_weight_denom; - reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | + reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(num_entry_point_offsets) | VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); + cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8); + /* Decoded picture size. */ reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | @@ -728,6 +809,18 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) if (!ctx->codec.h265.neighbor_info_buf) return -ENOMEM; + ctx->codec.h265.entry_points_buf = + dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, + &ctx->codec.h265.entry_points_buf_addr, + GFP_KERNEL); + if (!ctx->codec.h265.entry_points_buf) { + dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h265.neighbor_info_buf, + ctx->codec.h265.neighbor_info_buf_addr, + DMA_ATTR_NO_KERNEL_MAPPING); + return -ENOMEM; + } + return 0; } @@ -748,6 +841,9 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) ctx->codec.h265.neighbor_info_buf, ctx->codec.h265.neighbor_info_buf_addr, DMA_ATTR_NO_KERNEL_MAPPING); + dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, + ctx->codec.h265.entry_points_buf, + ctx->codec.h265.entry_points_buf_addr); } static void cedrus_h265_trigger(struct cedrus_ctx *ctx)