From patchwork Tue Jun 21 09:28:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12888931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97B85C43334 for ; Tue, 21 Jun 2022 09:30:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348920AbiFUJ3E (ORCPT ); Tue, 21 Jun 2022 05:29:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348907AbiFUJ24 (ORCPT ); Tue, 21 Jun 2022 05:28:56 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B4E4BE3; Tue, 21 Jun 2022 02:28:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SvKQzYeqQpXfbFYFxEPpyyCxGztpFJcmej6KfEobmnjMA7BC1dsO265mwiGzF+E5YBqGT0u22bweEBRh0lU9RTRHp1NUlqi67Yof2/NOOt3Dvfb/UrmU7CW+DqJxYDa4ZI/cTJhpHacWXc5C3n2hX61axLwOlpC0TACAbymURVRMh5mdmZ0rJRf9oWDajgPfUisYN1aSfkEfS4dxrzl4M/FTWZ4KfkLoOgGBJcnCAwbi2I24Agy6rz/lyuec047Opy9LN2dtic+FBny1HTz2RM5t4Kabbaegpz+GV6XqAhH+MeCd585K5QPU+OQ+XHdDRPu7mM6um7RqFMy+yCJHcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oG4ViLGS9a9Ayg33rEzZZFSG5BJ46TmXXTBdqwLAb/8=; b=RS/IUeUWlHdLzg76qfE99rTOI/6I/v6woc0CdGvgnZm1gJUmlHK1m9rdqR76imK3X57Jre3MRJAb82S0aK8iWALibZ/kVWQvcn5cvckviSGS+OHxHSbVVbj4OmB/he/QrmrDLM9PpVdCTdjMA06sVlF+iaXru6r7j12hifRLke/dc76MR9RkFDkG92cq9xukRFtnLeLaMbGNNUdhVjvAXeMu8TSH1IN1D9cWDf3pzKICd34oxVqDYEBRz3oOY0nPZjyNF+5eBjVVVQobQb+zoqm7feRqMy6yRdwVm/FrsxdHLivZpoenEvjsd2Xx1HOXSUWBuqpML7OaThr9zVJD6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=intel.com smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oG4ViLGS9a9Ayg33rEzZZFSG5BJ46TmXXTBdqwLAb/8=; b=lZC+6VeO/sPSw+mvpjNP+1qM3N/ULTKs7uWJGwbGO4OmYjEI2otFnYO5RR+zDlLPDpVFEHbo87buy+olGZ5NfE9lE1qbxAz1ctlnJQaTN9wt4EGQoeesIgnhuc/0nit70bb3GhdVWATbNC1IxDfQOwyBhBqH3bYxN5+39dIWe+4= Received: from SN6PR05CA0013.namprd05.prod.outlook.com (2603:10b6:805:de::26) by SA0PR02MB7466.namprd02.prod.outlook.com (2603:10b6:806:ed::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.17; Tue, 21 Jun 2022 09:28:51 +0000 Received: from SN1NAM02FT0053.eop-nam02.prod.protection.outlook.com (2603:10b6:805:de:cafe::ba) by SN6PR05CA0013.outlook.office365.com (2603:10b6:805:de::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.10 via Frontend Transport; Tue, 21 Jun 2022 09:28:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; pr=C Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by SN1NAM02FT0053.mail.protection.outlook.com (10.97.4.115) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Tue, 21 Jun 2022 09:28:51 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 21 Jun 2022 02:28:47 -0700 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 21 Jun 2022 02:28:47 -0700 Envelope-to: git@xilinx.com, hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=45120 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o3aBi-000DOt-IK; Tue, 21 Jun 2022 02:28:46 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/3] fpga: manager: change status api prototype, don't use older Date: Tue, 21 Jun 2022 14:58:31 +0530 Message-ID: <20220621092833.1057408-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220621092833.1057408-1-nava.manne@xilinx.com> References: <20220621092833.1057408-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d0ae5fbd-c8eb-4498-f099-08da5368744b X-MS-TrafficTypeDiagnostic: SA0PR02MB7466:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Q/yT3HpCKtFDi9RcoiXRsGSs2uKsyHJGYfC8fytLgdF5NG8d5uz5hQwVV/RG0I0htfd/SfOY0mCQTWPaJffZb06+1mvd5fAkSeGNNkdTMovuCIHAQA0YUA2+4kZg55h1Y3LOBXl3MW9GORdTLDxDRLRr76lRZNrbI58w/st5AwkjxO+4sdN91/uVc5KRXIwNc6Z76LZOGu0g+8g/CNuhHGCYEHofMcpckwm74/+wZlonwIcMKeGtgkYWoaxwCUiDYVx5jsRyJ9x3aJH+cZ6TP2jHVjFsKMwYkSLS4QHjsuK8JAkWGVFulhYW6YYnMYbNhHcrXGJzcaMsxFiWdyzOnC58qOsMv7wbQ7MqlM7Xv8587stlfJwsaBkJMte6Iu53zqS1KxpK/mna3qGgjRJsWEVH+VE6Us1/abbSrVL6Ey/9qZjailG0XsCkwr1lDzsM2EwKhpDjDokpWpbfNT0eQx6AHuioP4MLUcEYhadmfc7X+AHQTr9aoKF/9hJVVWigbew/5JCixOgiCcQGg+K3cyuE8pYeadsnz4UXTED17xYoJxSF2PImEsNcTq0yWzcplZzAXTWCCtCbrIlocca93ShG7FvZiGHo8TyhF9YckxqB+j4TqQO81yvHdX5HY1A4vYm3CMZVzKuGBGK7rpWaeuBJLkxXXE87Y4sXpyqZ1KjY5hGxfI/2vipzorrWilRZA/hrI/dkERGFTuN7fpWEQjp+aS36pL+J6MfETJHGmwgHX64gK9pn0h9goltW4DGkQA1+Dxrkz55JDCuLg2qONyWhm6SXx/AqTfvsEWsmk0v6lqY47JY+pagHlVrG0CD6 X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230016)(4636009)(346002)(376002)(396003)(136003)(39860400002)(46966006)(36840700001)(40470700004)(8936002)(36756003)(9786002)(40480700001)(5660300002)(40460700003)(70586007)(82310400005)(2906002)(316002)(6636002)(70206006)(110136005)(186003)(83380400001)(426003)(2616005)(336012)(8676002)(921005)(7696005)(41300700001)(1076003)(478600001)(6666004)(47076005)(36860700001)(82740400003)(26005)(356005)(7636003)(102446001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2022 09:28:51.8403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0ae5fbd-c8eb-4498-f099-08da5368744b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7466 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Different vendors have different error sets defined by Hardware. If we always define the new bits when we cannot find an exact 1:1 mapping in the core the 64 bits would soon be used out. Also, it's hard to understand the mixture of different error sets. To address these issues updated the status interface to handle the vendor-specific messages in a generic way. With the updated status interface the vendor-specific driver files can independently handle the error messages. Signed-off-by: Nava kishore Manne --- Changes for v2: - New patch. drivers/fpga/dfl-fme-mgr.c | 20 ++++++++++---------- drivers/fpga/fpga-mgr.c | 24 +++++------------------- include/linux/fpga/fpga-mgr.h | 2 +- 3 files changed, 16 insertions(+), 30 deletions(-) diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index af0785783b52..5a8e6a41c85c 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -72,22 +72,22 @@ struct fme_mgr_priv { u64 pr_error; }; -static u64 pr_error_to_mgr_status(u64 err) +static ssize_t pr_error_to_mgr_status(u64 err, char *buf) { - u64 status = 0; + ssize_t len = 0; if (err & FME_PR_ERR_OPERATION_ERR) - status |= FPGA_MGR_STATUS_OPERATION_ERR; + len += sprintf(buf + len, "reconfig operation error\n"); if (err & FME_PR_ERR_CRC_ERR) - status |= FPGA_MGR_STATUS_CRC_ERR; + len += sprintf(buf + len, "reconfig CRC error\n"); if (err & FME_PR_ERR_INCOMPATIBLE_BS) - status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR; + len += sprintf(buf + len, "reconfig incompatible image\n"); if (err & FME_PR_ERR_PROTOCOL_ERR) - status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR; + len += sprintf(buf + len, "reconfig IP protocol error\n"); if (err & FME_PR_ERR_FIFO_OVERFLOW) - status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR; + len += sprintf(buf + len, "reconfig fifo overflow error\n"); - return status; + return len; } static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr) @@ -252,11 +252,11 @@ static int fme_mgr_write_complete(struct fpga_manager *mgr, return 0; } -static u64 fme_mgr_status(struct fpga_manager *mgr) +static ssize_t fme_mgr_status(struct fpga_manager *mgr, char *buf) { struct fme_mgr_priv *priv = mgr->priv; - return pr_error_to_mgr_status(priv->pr_error); + return pr_error_to_mgr_status(priv->pr_error, buf); } static const struct fpga_manager_ops fme_mgr_ops = { diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 08dc85fcd511..ae8de13a482e 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -38,10 +38,11 @@ static inline enum fpga_mgr_states fpga_mgr_state(struct fpga_manager *mgr) return FPGA_MGR_STATE_UNKNOWN; } -static inline u64 fpga_mgr_status(struct fpga_manager *mgr) +static inline ssize_t fpga_mgr_status(struct fpga_manager *mgr, char *buf) { if (mgr->mops->status) - return mgr->mops->status(mgr); + return mgr->mops->status(mgr, buf); + return 0; } @@ -460,23 +461,8 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { struct fpga_manager *mgr = to_fpga_manager(dev); - u64 status; - int len = 0; - - status = fpga_mgr_status(mgr); - - if (status & FPGA_MGR_STATUS_OPERATION_ERR) - len += sprintf(buf + len, "reconfig operation error\n"); - if (status & FPGA_MGR_STATUS_CRC_ERR) - len += sprintf(buf + len, "reconfig CRC error\n"); - if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR) - len += sprintf(buf + len, "reconfig incompatible image\n"); - if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR) - len += sprintf(buf + len, "reconfig IP protocol error\n"); - if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR) - len += sprintf(buf + len, "reconfig fifo overflow error\n"); - - return len; + + return fpga_mgr_status(mgr, buf); } static DEVICE_ATTR_RO(name); diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 0f9468771bb9..42c24426fb7f 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -154,7 +154,7 @@ struct fpga_manager_info { struct fpga_manager_ops { size_t initial_header_size; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); - u64 (*status)(struct fpga_manager *mgr); + ssize_t (*status)(struct fpga_manager *mgr, char *buf); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); From patchwork Tue Jun 21 09:28:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12888932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AD39C433EF for ; Tue, 21 Jun 2022 09:30:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348938AbiFUJ3F (ORCPT ); Tue, 21 Jun 2022 05:29:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348953AbiFUJ3D (ORCPT ); Tue, 21 Jun 2022 05:29:03 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2062.outbound.protection.outlook.com [40.107.93.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC82D10A; Tue, 21 Jun 2022 02:28:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YrpGaeF7KBCohxgPuxxETiYBRnRkwvFozGW04u1mDwahIq0PbeH5ymJTRmb2LOcQHbIyGPihHzdSkMXdzETGqVRwpadtF7CLD19T5N/ac6E/3lOMoeWaOMw73uRf0z3QCYDwzMIRSBo+eT1sRPmiheOAdfZTlyfHc0mCbtoACoOXyUg+oxgVz/yl2SSyM6bDrqNmurAnmt8g4FjtBC6QTpRPr5hWjkLXYfT3qCNd/yKP5vgtXMqA9I+pmwJ6u1fi6MdX/3p32FqaLkwP5UORscMt6uF9fNEyhtCMnM4PvyVPFf+t0zHDVXPuQmJY/Uw3zREmBc8aLqTb42Pyv4BGBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=M7K0ILwbCgICfMtH8hwDNrdO38tn2hjPqx673jRl/rg=; b=QQv29e7RqEjDPXztNkgAdFH8lyn1l7u1SIbaalGTg/vfY/Auy4BJRdVdfpZRNQkZ/j/9sMgyXuosMrYnfW1dQrBdiy+9pWulxqkzVQyJb3Pc4BEAwv3rE7p9F7bQq5R5tA8r3PesSCPejvYxP7qLq8xrGQEKsWEwtq/hg5+RgJKn0juNK9xD9XXILiya0a6GKLreQT/s8rwEedYMH6DtUHISoWWBGfUF0ftspygMTwzpQIeCr7DRSEbGRgdEFuDRv9lDXVnyJLUD9s5vh5Qb0sS68+sxB32rN4Xy0+y/Ylj+xelLFyJXwe7YfN6xyGM6doekDF9hEPmy7ntn7eH+hQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=intel.com smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M7K0ILwbCgICfMtH8hwDNrdO38tn2hjPqx673jRl/rg=; b=bvb0RSO57PIS91z7UOtJWPmvbg1vmI8S/PLV3sQmM1GSs7/Teng8VtBScSs/w5NAnaE1Svhtcl5ePGlwadlDMK/IFk1AaLillua2oWG2uPzO8W3hRCKXf+/0HB7kotL203FNGg53dyukTJZMKL5ovVeNiKtUPIPMDVp0YNpQX0M= Received: from SN6PR05CA0004.namprd05.prod.outlook.com (2603:10b6:805:de::17) by DM8PR02MB7991.namprd02.prod.outlook.com (2603:10b6:8:14::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.16; Tue, 21 Jun 2022 09:28:55 +0000 Received: from SN1NAM02FT0048.eop-nam02.prod.protection.outlook.com (2603:10b6:805:de:cafe::85) by SN6PR05CA0004.outlook.office365.com (2603:10b6:805:de::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.9 via Frontend Transport; Tue, 21 Jun 2022 09:28:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; pr=C Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by SN1NAM02FT0048.mail.protection.outlook.com (10.97.4.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Tue, 21 Jun 2022 09:28:54 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 21 Jun 2022 02:28:53 -0700 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 21 Jun 2022 02:28:53 -0700 Envelope-to: git@xilinx.com, hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=45120 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o3aBp-000DOt-16; Tue, 21 Jun 2022 02:28:53 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH v2 2/3] firmware: xilinx: Add pm api function for PL readback Date: Tue, 21 Jun 2022 14:58:32 +0530 Message-ID: <20220621092833.1057408-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220621092833.1057408-1-nava.manne@xilinx.com> References: <20220621092833.1057408-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 34fef55a-902d-4ca3-5cbf-08da53687628 X-MS-TrafficTypeDiagnostic: DM8PR02MB7991:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fhKp4Att0VOw1AeK2WMldLgIc/8lLblbOpamG2a33awrJhk+oj8WymdQJqVesj+O2Z6BLT7I6WiXYFL1hEcYPpvoD1UgO6w5q+veMYHobjV9Re9zuO8KH4mBwy7JrdgsQ/Y8bkEreZ0wGp2PYkRdwW7ijZ18rqDbYJ5f61WOeP+k8PK7H3OKElm0W6hs12PHB4mE22eKKYCqN/QHkBinoCKXTlwTTzlYpHb5NuGH7ijFMisrzP5BBLa4zwT3YEqshqNyitW71x3Nn+em0cIj7d2uGtnqEZVaevBbzQKn5XEMzZUoIb0iCs/v0kuald4c468vvSn1RxSN3OKGw261+Y4o0HXADFT+q8cogZGl/R6mWbkHxy1QutPPx283x3SoG611yma+fXFVjd+xWc9808ehqlhBJKawuq7KFeJk6WVo+HXDviaYcR2WfI3md/wGGnAsTVRNeo/KzbUwjOPQYf9gzgc1EtgYU6m0r8sCFgWM02k/ZrzDHUYv8Gklkb0HIwzSjSKYwyCiPP3GBxnwuYhRs2fuTPVuMw5CnYznkIEZ8H2xDFVQezjyMWQx3q3GjCb/+deaxO6pFFzTOQMJydEevkSjb6aoF/P//9xZKOXnLECdYk/c25ttrMtq8yjK41evNnsK1GvnTkpzgkYYUqSo71+QCQxiygIDZamYjF9U6rxlxm9KI2tYXCbayNBiIh3OH7Q/Iy3x1TvgM0kwf1SUx7sX6lUE+8AaZ/tgV576ze9kPS2XMdE4gOb+9EumGHc/7lh3iBASen5pu9NFq4+aORwxxsTT0S25H7o5aa7wcwIxHH6iZeJqw7S9T05Z X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230016)(4636009)(346002)(136003)(39860400002)(396003)(376002)(46966006)(36840700001)(40470700004)(478600001)(6636002)(110136005)(2906002)(316002)(26005)(921005)(8676002)(5660300002)(36756003)(2616005)(41300700001)(70206006)(9786002)(70586007)(8936002)(47076005)(336012)(426003)(186003)(40460700003)(7636003)(82740400003)(6666004)(7696005)(356005)(36860700001)(40480700001)(82310400005)(83380400001)(1076003)(102446001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2022 09:28:54.9626 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34fef55a-902d-4ca3-5cbf-08da53687628 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0048.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR02MB7991 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds PM API for performing PL configuration readback. It provides an interface to the pmufw to readback the FPGA configuration registers as well as configuration data. For more detailed info related to the configuration registers and configuration data refer ug570. Signed-off-by: Nava kishore Manne Reported-by: kernel test robot Reported-by: kernel test robot --- Changes for v2: - None. drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 14 ++++++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7977a494a651..40b99299b662 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -927,6 +927,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); +/** + * zynqmp_pm_fpga_read - Perform the fpga configuration readback + * @reg_numframes: Configuration register offset (or) Number of frames to read + * @phys_address: Physical Address of the buffer + * @readback_type: Type of fpga readback operation + * 0 - FPGA configuration register readback + * 1 - FPGA configuration data readback + * @value: Value to read + * + * This function provides access to xilfpga library to perform + * fpga configuration readback. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_fpga_read(const u32 reg_numframes, const phys_addr_t phys_address, + bool readback_type, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ, reg_numframes, + lower_32_bits(phys_address), + upper_32_bits(phys_address), readback_type, + ret_payload); + *value = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_read); + /** * zynqmp_pm_pinctrl_request - Request Pin from firmware * @pin: Pin number to request diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 1ec73d5352c3..7dc4981345dc 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -61,6 +61,10 @@ #define PM_LOAD_PDI 0x701 #define PDI_SRC_DDR 0xF +/* FPGA readback type */ +#define PM_FPGA_READ_CONFIG_REG 0x0U +#define PM_FPGA_READ_CONFIG_DATA 0x1U + /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration @@ -116,6 +120,7 @@ enum pm_api_id { PM_CLOCK_GETRATE = 42, PM_CLOCK_SETPARENT = 43, PM_CLOCK_GETPARENT = 44, + PM_FPGA_READ = 46, PM_SECURE_AES = 47, PM_FEATURE_CHECK = 63, }; @@ -468,6 +473,8 @@ int zynqmp_pm_feature(const u32 api_id); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); +int zynqmp_pm_fpga_read(const u32 reg_numframes, const phys_addr_t phys_address, + bool readback_type, u32 *value); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -733,6 +740,13 @@ static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, { return -ENODEV; } + +static int zynqmp_pm_fpga_read(const u32 reg_numframes, + const phys_addr_t phys_address, + bool readback_type, u32 *value); +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Tue Jun 21 09:28:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12888933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BACDEC43334 for ; Tue, 21 Jun 2022 09:31:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348870AbiFUJ3V (ORCPT ); Tue, 21 Jun 2022 05:29:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348928AbiFUJ3L (ORCPT ); Tue, 21 Jun 2022 05:29:11 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BEB8271C; Tue, 21 Jun 2022 02:29:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=innWu0GTv6FJJNhyXG3LiNZIA5x1zSTT+CeYjkvNLkG9h3SZOFmsVF/9wQlseBWjIJCv6tZXRmro+749sPu33eIUrVSUPU6LzBok+bakP5PrpG7izlek0eHgUYYDaGnVh7IXPOSPCh11sX1G6rV6/s0NkF/p+rQtdSnNxs+aW/PUuMQgaraZoxE82Dm6JksLcOXjFjNJXfOzYIomxleVQapTEi/2R2ue9S2wg6D4WnnwK/mRK7SqyP4fL8nIoTSD1wQ0oZTCc13Tn8LU3ZWZRarC8iKAPl1Cb8JT+Z77q8oA6AU9ODyiryEShosC9sc7P2rB7KrdVfN6LBbsqRWkoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=V5y0Pm1kQkbMHm0i2knoXvV31XRIf2UoMMdM07UuU5k=; b=edNGDdPrzPOHJLwQo6WDoAR5XBaEAGfSE/koDDd9s5duK1Qt6Ea4MaBhGxyYWD0qKhAbNI76N+u3F0xlqvRHRAPJlwaOzQyS1bFM2LOv9x9cfOPRYc0YcORD9f8zwqZgcKHMj1A7NdZ9TJTdlEIg/mROVvJnZJB7RI3zqhcDqCifngSiQ3vbdtCBwkPO2xCeY/hM6e+Mb5gm9VSlh8tWJLqGPVFRM+kL38Os/Gea+vHfj9eZh8ucVAFnILokgquYE9kSu/m77UUxOe0Wjj4GC9Ougnh45J/PrKBf0dZPjW+J4gj63V9Vx1rQhwIOHRF4U4HL1fgiuUzfln1cHutxUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=intel.com smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V5y0Pm1kQkbMHm0i2knoXvV31XRIf2UoMMdM07UuU5k=; b=FNl2M6cP5cj0k+2Y4kh1pWjXIK5psKwHi2mcGtAxdePS21yX3cDtKXB4eBs4tHXlMWGB3AD2h/LKA0hnuuFAzjmuOYB3GOp3qj+LD/Kdi0dZb+YdVPxHdtuoWvilEJiyoGDGkHFLBkSUQehHfAtAM/OgVIR9MYt/ekHhOo9c4eY= Received: from SA1PR05CA0011.namprd05.prod.outlook.com (2603:10b6:806:2d2::13) by SA2PR02MB7772.namprd02.prod.outlook.com (2603:10b6:806:149::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.18; Tue, 21 Jun 2022 09:29:08 +0000 Received: from SN1NAM02FT0010.eop-nam02.prod.protection.outlook.com (2603:10b6:806:2d2:cafe::8a) by SA1PR05CA0011.outlook.office365.com (2603:10b6:806:2d2::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.9 via Frontend Transport; Tue, 21 Jun 2022 09:29:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; pr=C Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by SN1NAM02FT0010.mail.protection.outlook.com (10.97.4.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Tue, 21 Jun 2022 09:29:08 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 21 Jun 2022 02:29:01 -0700 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 21 Jun 2022 02:29:01 -0700 Envelope-to: git@xilinx.com, hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=45120 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o3aBx-000DOt-70; Tue, 21 Jun 2022 02:29:01 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface Date: Tue, 21 Jun 2022 14:58:33 +0530 Message-ID: <20220621092833.1057408-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220621092833.1057408-1-nava.manne@xilinx.com> References: <20220621092833.1057408-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dd557fa9-1cb0-4d2b-a730-08da53687df4 X-MS-TrafficTypeDiagnostic: SA2PR02MB7772:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GL56llDNxqOQOaq70Zq0tMb0C9DvSC9y2s+t2zwpsq5RZERqle3nEyEmFkqvnqU4nga9oiEmY3s8IRttBAWOHhxwfb/9E3xMur6BrOnSVFk4L0beLWw3TWkcOGu57zovir5lJuA39hAM/fN1NtIWlJVYEw8ask+yCXPhLabenm9J1hu17t2BPWwKTb7Zk3w2cjnrCj2DFN0MMp17J2VFmZ6PeL5U3zADrgOmWMBPgR1qo20VdRclaGBICnHvG7Psi1ZYv21fqEkEQDId1TzW/ehbNsYMSK28hddgY/vfHAq52fo/ENN6hC+BmR6fa4QKxDYj+jcYphFF/CsgjQl2M8zbTWv8RW5ySD9Uce4C3nKGTZzY93/RK1DJYoD+WehYhfTaceQwqJFewYw0ONO4422azJRXD3WsciBf+KuQOGvU6cpPewAt7TVkP2Mg5Cdc67Vd4wE3ppkk9Y5G2NrM2WxuYX9hK/AcZZbJxOJ5r1i1jBLKxms2ipwcYLDPBimr5d3T8pKw/I3czJOzdhoQ4j4q8BwCVw6naftmwp9u/+uvl2sIlBvUcUEgaBC/4PYmucrOq4Jbm5DQsGbH4g1bkVgvlpph1NSnwf4Tze29kGWZZkgbQHYkuSoEFt7+Z8BDYzTdtzerp632Q0Q6amtrkfMUiFTZfmiq/pWB9K3uBNkl6gj9tRXMudOMURNcWQuc5B5nQiaDsVSR5O0Ots6SwPANwVedJ4a/iILnQr6V0ooxTZPeaJ0ypR0a57dCjGlDcb0myagR6+vouquAJi6uhUoeRDWVuWCgFIt6PcKvwHBoOD9RSfyRaqn8gf/8b8nW X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230016)(4636009)(376002)(136003)(396003)(39860400002)(346002)(46966006)(40470700004)(36840700001)(83380400001)(7636003)(47076005)(426003)(1076003)(336012)(921005)(82740400003)(356005)(6666004)(40480700001)(40460700003)(186003)(36860700001)(82310400005)(7696005)(70206006)(9786002)(26005)(110136005)(316002)(6636002)(478600001)(2906002)(2616005)(41300700001)(70586007)(8676002)(5660300002)(8936002)(36756003)(102446001)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2022 09:29:08.0455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd557fa9-1cb0-4d2b-a730-08da53687df4 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0010.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7772 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds status interface for zynqmp-fpga, It's a read only interface which allows the user to get the PL status. Usage: To read the PL configuration status cat /sys/class/fpga_manager//status Signed-off-by: Nava kishore Manne --- Changes for v2: - Updated status messages handling logic as suggested by Xu Yilun. drivers/fpga/zynqmp-fpga.c | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index c60f20949c47..e194bba91d3f 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -14,6 +14,19 @@ /* Constant Definitions */ #define IXR_FPGA_DONE_MASK BIT(3) +#define READ_DMA_SIZE 256U + +/* Error Register */ +#define IXR_FPGA_ERR_CRC_ERR BIT(0) +#define IXR_FPGA_ERR_SECURITY_ERR BIT(16) + +/* Signal Status Register. For details refer ug570 */ +#define IXR_FPGA_END_OF_STARTUP BIT(4) +#define IXR_FPGA_GST_CFG_B BIT(5) +#define IXR_FPGA_INIT_B_INTERNAL BIT(11) +#define IXR_FPGA_DONE_INTERNAL_SIGNAL BIT(13) + +#define IXR_FPGA_CONFIG_STAT_OFFSET 7U /** * struct zynqmp_fpga_priv - Private data structure @@ -77,8 +90,48 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) return FPGA_MGR_STATE_UNKNOWN; } +static ssize_t zynqmp_fpga_ops_status(struct fpga_manager *mgr, char *buf) +{ + unsigned int *kbuf, reg_val; + dma_addr_t dma_addr; + ssize_t len = 0; + int ret; + + kbuf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE, + &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = zynqmp_pm_fpga_read(IXR_FPGA_CONFIG_STAT_OFFSET, dma_addr, + PM_FPGA_READ_CONFIG_REG, ®_val); + if (ret) { + len += sprintf(buf + len, "firmware error\n"); + goto free_dmabuf; + } + + if (reg_val & IXR_FPGA_ERR_CRC_ERR) + len += sprintf(buf + len, "reconfig CRC error\n"); + if (reg_val & IXR_FPGA_ERR_SECURITY_ERR) + len += sprintf(buf + len, "reconfig security error\n"); + if (!(reg_val & IXR_FPGA_INIT_B_INTERNAL)) + len += sprintf(buf + len, "Device Initialization error\n"); + if (!(reg_val & IXR_FPGA_DONE_INTERNAL_SIGNAL)) + len += sprintf(buf + len, "Device internal signal error\n"); + if (!(reg_val & IXR_FPGA_GST_CFG_B)) + len += sprintf(buf + len, + "All I/Os are placed in High-Z state\n"); + if (!(reg_val & IXR_FPGA_END_OF_STARTUP)) + len += sprintf(buf + len, "Device sequence error\n"); + +free_dmabuf: + dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf, dma_addr); + + return len; +} + static const struct fpga_manager_ops zynqmp_fpga_ops = { .state = zynqmp_fpga_ops_state, + .status = zynqmp_fpga_ops_status, .write_init = zynqmp_fpga_ops_write_init, .write = zynqmp_fpga_ops_write, };