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[88.207.99.158]) by smtp.googlemail.com with ESMTPSA id b14-20020a056402084e00b0043565c79879sm10713114edz.43.2022.06.21.12.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 12:55:14 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable Date: Tue, 21 Jun 2022 21:55:10 +0200 Message-Id: <20220621195512.1760362-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_125519_874774_B32DF483 X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by: Robert Marko Reviewed-by: Dmitry Baryshkov --- Changes in v4: * Set 125MHz as the default if not set in qmp_phy_cfg --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index b2cd0cf965d8..66be854fe7f3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1284,6 +1284,9 @@ struct qmp_phy_cfg { /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; + + /* QMP PHY pipe clock interface rate */ + unsigned long pipe_clock_rate; }; /** @@ -2121,8 +2124,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) init.ops = &clk_fixed_rate_ops; - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate = 125000000; + /* + * Controllers using QMP PHY-s use 125MHz pipe clock interface + * unless other frequency is specified in the PHY config. + */ + if (qmp->phys[0]->cfg->pipe_clock_rate) + fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; + else + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; ret = devm_clk_hw_register(qmp->dev, &fixed->hw); From patchwork Tue Jun 21 19:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12889671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAF29C433EF for ; Tue, 21 Jun 2022 19:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=25RFxUTyDpkqaaewM/I3XkxivszyBMcOX6xxdxcpWDY=; b=st290ADNhAURv6 b9SLQNywcujzvWIISnr76L0fj83VJT9+qstTOzVpAxEAorDip41ltz+Do5SwPoIR4GL/PJHy8Np5N HW0yRExtiwROj37qKbEc+u0wVZcjCO5o+VpsyhLI2bH5I7wUnXwwxoSNzmm9gV8tMDz5g55YwsG6u dizFUzQKJdU47Qzjgbet0Bbtu0nuKmhbHqDGX4i6Fi/PRVrbRe9gT3CiONOnbw8+cKaoNa9HFihZS jLhYYs5U3WgFtVI5XSoABBFXQVvAo/CXBSRfVkBlWQnfy+kTFNP2xLnnAYy0iHPoEekE3IWlP8sLh SnUuVQgs0ZGmyLI0VKyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3jy9-006zqO-0h; Tue, 21 Jun 2022 19:55:25 +0000 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3jy3-006zmq-U2 for linux-phy@lists.infradead.org; Tue, 21 Jun 2022 19:55:22 +0000 Received: by mail-ed1-x52b.google.com with SMTP id e40so8285054eda.2 for ; Tue, 21 Jun 2022 12:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v7nxHvlawisf1+yiWy1FwkyOpuVc183YG++a4GngDmg=; b=Of9IoRCLVu5v+Z5ddV72KVppR+laNfguuEbqBT5OxjDsIhtr+p6dJ/ayxexE+Sp95w AL7Usr1LVie3Eb1navS8t/NjDHi785NBlKMjwQxUfqRXb7nlwke06jd4rqynA3G/byjs Grk2pg+h1sHX1kPsFz8cNXb8NIuw2a9m8NtV4Utxid4HcOR+aO8saZiBTI8ym9I7po1C /JBOAqF6Dr83/efUf7dTKR/C9wzPKahL9hsqG7xg78iMZai05Or3WvaUV9+nSqUrgESO 8Gp6NjYLslicqBfYbhOtT/V1hdNpF3p1pEZWqLX5VQ21b1qmvNkSc5vFhkKs88zKnkP2 IcHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v7nxHvlawisf1+yiWy1FwkyOpuVc183YG++a4GngDmg=; b=fZEDqK6fgo2LRi0xrbWivNfnsUouCfLiG7WBxJFthh22FHYzndI5zmCEGo8SiN47/M yL3yXfgtjzqRulIiKpXMCyYacT3WMh6QlGfx7j4xntryoCPSfYg+fJgnGSIsBocPXVPL /6E7wX+FxzW2M5po3oD0aNbuYRWn9CaE0WKX8VHepQtlcciQUGzB6t03JRQvIszWY+Pa 0gopIROXBH+6vdCKFB8fqGgF7qrskIcndRPZ2TacVRPMNIYRUFiF6dIzo4BYmqTeUxp+ W7H3mSBzpFAnfgfr9xGq8qwqBGFm6Db0pvBtibZJUuWN55tFU9eWwqhQFfyGbkvXJVtc T2Ag== X-Gm-Message-State: AJIora9awxJtaal3QBc1lI59FnWwoeusnC8w5dd8JdxrvA1aJzohI/0/ y4N74YQi0EHNT8cO+oP8pw8= X-Google-Smtp-Source: AGRyM1ulGRkk8/kYxv1RJHx/pF7nhbd80DwOp0kNIGeWuw+yvL/4Hu1TFD9TVkzAJDaXo9RG9b8lFA== X-Received: by 2002:a05:6402:354d:b0:435:93f9:fc0b with SMTP id f13-20020a056402354d00b0043593f9fc0bmr6587948edd.288.1655841316086; Tue, 21 Jun 2022 12:55:16 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-158.xnet.hr. [88.207.99.158]) by smtp.googlemail.com with ESMTPSA id b14-20020a056402084e00b0043565c79879sm10713114edz.43.2022.06.21.12.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 12:55:15 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v4 2/3] dt-bindings: phy: qcom,qmp: add IPQ8074 PCIe Gen3 PHY binding Date: Tue, 21 Jun 2022 21:55:11 +0200 Message-Id: <20220621195512.1760362-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621195512.1760362-1-robimarko@gmail.com> References: <20220621195512.1760362-1-robimarko@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_125519_996000_B8D23C7B X-CRM114-Status: UNSURE ( 8.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, document the bindings for the Gen3 one. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 8b850c5ab116..220788ce215f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy @@ -312,6 +313,7 @@ allOf: contains: enum: - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy then: properties: From patchwork Tue Jun 21 19:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12889672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C84C3C43334 for ; Tue, 21 Jun 2022 19:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o1kVpdvZVTppvpPR7E0c2pRH4KoYvFUUtwx9GgBCXhM=; b=A5E837PHO5bHDy QWlPy7XbyK6ODxonzzSzTWkqtErVSWOWxIlVTt9ianF7E9f2nbBy0+PsqOZ5HpZZHbnNbWqWiFGb3 LfgrSMX6zMMiGONNZ++cLLJuw5KMyljRMJzSgnTo6U6ybAlUYQfwKURvQDG0SKLwiXiQkfz4eqXBb jdB0LfboWbTfLwZ2PFQHIYrbDZKqPks+ZgxxmTmYByN3kwjxNn+mnn1XQBSbFsN8tPl2HsplxT5uK 4kUwWw9yQ7TBxQBEb+uCGpHyuqlmr5cDOSi4dYmqaX2BXwgNQzf3GoRVry/9BOaKrKG3a8A0zWJLd bDI+b9ZdCgO42/5XqW0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3jy9-006zqY-5o; Tue, 21 Jun 2022 19:55:25 +0000 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3jy3-006zn4-Tr for linux-phy@lists.infradead.org; Tue, 21 Jun 2022 19:55:23 +0000 Received: by mail-ed1-x531.google.com with SMTP id o9so11598553edt.12 for ; Tue, 21 Jun 2022 12:55:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H/ZG3fROItdiM7fC7fGeB2kOWBE6C7UJMUMDTzcLnLw=; b=bCTt3+5ntZGQrNn9uWfci8xxbg9EyWeDNHHziaxfbw7colSfC71xSz/5ZuCoUZpMEB gO1tSbb5R1wUGoigRWQwyMgG5p8/C2c31/h1BfVcjS0gQei6/7G9sF7Qo8b40Uuw6F1+ pLswUyvpoKSvhS0RsZ68oHWWbkrk7irpruMVPC9oHr8FozabiO9MAn09BVWhsE0fzEMV kiG1cC2FFF1qUVPpGqm7z7iJXaTUJpgGC6/W4d1fZZEcOySXEtYEAlszTo4Xpnalp3qa Kq0At5YgABB71H5cU+fAthF9HUyiBmuW4INvzdLZJZcnA+neXLeJrOQrmriSb1oi1sDk eWKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H/ZG3fROItdiM7fC7fGeB2kOWBE6C7UJMUMDTzcLnLw=; b=ZCRXUJd2FeYOOCAowtoO5Ipv8SITUOd5sIYEaZZhLR0NiR1feLLoOZRsZ0SHE4OQMI qCQAAPR/qVVL5vEzsJCXfOBHchRyfPORns+fqWWcAy9VBS83oheM/O5hzqLjxT4v0Z5F 4aw5qiVKgSokr1JGMb97np9+E+lJ5t4Zq/rcRdYnAnun6J7duBja5RoH84SvzMpkS7SB jc1+KrY+LSt/SJZoO0hIfYHZ6wXNPADxdEFw5Exg35WPzhOCrEQjnPocGN6zQHts32XU iCx02j5f1DrpNToM5c0ZqNGbFEhw0gQvn85OtCWRllKhO4B5mpoHACvqIQ0+7UOoxUKM SIvQ== X-Gm-Message-State: AJIora9BzE3WaF2I6IiqPJNn34/eL8z1irNtdD9BFBLTCZiW26u4xQkT RBtzMULfhQZhcN0ckabm3Ys= X-Google-Smtp-Source: AGRyM1vEvlsk4wgNGbR9VANjID97nsc8Syg001ol89Hq3zEzJLk2Rkh4eK9/NSoI7XQaPkrRLAbvIw== X-Received: by 2002:a05:6402:4384:b0:435:8cd7:8b48 with SMTP id o4-20020a056402438400b004358cd78b48mr10533421edc.283.1655841317156; Tue, 21 Jun 2022 12:55:17 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-158.xnet.hr. [88.207.99.158]) by smtp.googlemail.com with ESMTPSA id b14-20020a056402084e00b0043565c79879sm10713114edz.43.2022.06.21.12.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 12:55:16 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 3/3] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support Date: Tue, 21 Jun 2022 21:55:12 +0200 Message-Id: <20220621195512.1760362-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621195512.1760362-1-robimarko@gmail.com> References: <20220621195512.1760362-1-robimarko@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_125520_019184_0D3E7901 X-CRM114-Status: GOOD ( 12.40 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, so add the support for the Gen3 one. It uses the same register layout as IPQ6018. Signed-off-by: Robert Marko Reviewed-by: Dmitry Baryshkov --- Changes in v3: * Remove parsing QMP pipe clock rate from DT, and instead use the rate as set in the PHY config Changes in v2: * Rebase onto next-20220621 to apply on the refactored driver * Remove non existant has_phy_com_ctrl and has_lane_rst --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 160 +++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 66be854fe7f3..8e6b3ed07394 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -450,6 +450,133 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), }; +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9), + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42), + QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb), + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), +}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -1424,6 +1551,36 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; +static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), + .tx_tbl = ipq8074_pcie_gen3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), + .rx_tbl = ipq8074_pcie_gen3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), + .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), + .clk_list = ipq8074_pciephy_clk_l, + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = ipq_pciephy_gen3_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ + + .pipe_clock_rate = 250000000, +}; + static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, @@ -2265,6 +2422,9 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { }, { .compatible = "qcom,ipq8074-qmp-pcie-phy", .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", + .data = &ipq8074_pciephy_gen3_cfg, }, { .compatible = "qcom,ipq6018-qmp-pcie-phy", .data = &ipq6018_pciephy_cfg,