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(unknown [104.36.31.105]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a316.dreamhost.com (Postfix) with ESMTPSA id 4LSHkk3HV0z2n; Tue, 21 Jun 2022 13:13:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1655842383; bh=8KPyrK4qTJmhET6C28NIGcqXGbT/X/diSCKe69qw4NE=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=eYymlIO2XmOrppHTU3OEIr/W82/B03X8k/1zpG6CRJ8eQgREq90FGoGsO2NbP6onH DGdG+AerImRAZzbhBDw98PPX88jmXdq/7exRwIE//VvRCj2uH2a8LPJaAUqr7zL6El csozTIiv0i6gzD5BgfLroUi4EPnNUMTFGej6XTI2p9CH9PwHcArzVPpNMMesGqyGZT oJUADS2gUb+J5a0U//q81+7b2HrKCN7xyzEJc5B58F5LMwBpB7iTPcvkeM1g0nx44R 8A+EKV6UXiCCGUz41mUX/hI45GZkdC8uvB3prOaYf/YhivnsL8IrPskS+8xRKd8kvb jjnYNzqe2B5pg== From: Davidlohr Bueso To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, ira.weiny@intel.com, vishal.l.verma@intel.com, a.manzanares@samsung.com, dave@stgolabs.net, linux-kernel@vger.kernel.org Subject: [PATCH] cxl/acpi: Verify CHBS consistency Date: Tue, 21 Jun 2022 13:12:59 -0700 Message-Id: <20220621201259.1547474-1-dave@stgolabs.net> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Similarly to verifying the cfwms, have a cxl_acpi_chbs_verify(), as described by the CXL T3 Memory Device Software Guide for CXL 2.0 platforms. Also while at it, tuck the rc check for nvdimm bridge into the pmem branch. Signed-off-by: Davidlohr Bueso --- drivers/cxl/acpi.c | 64 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 40286f5df812..33b5f362c9f1 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -187,14 +187,65 @@ static int add_host_bridge_uport(struct device *match, void *arg) struct cxl_chbs_context { struct device *dev; unsigned long long uid; + struct cxl_port *root_port; resource_size_t chbcr; }; +static inline bool range_overlaps(struct range *r1, struct range *r2) +{ + return r1->start <= r2->end && r2->start <= r1->end; +} + +static int cxl_acpi_chbs_verify(struct cxl_chbs_context *cxt, + struct acpi_cedt_chbs *chbs) +{ + struct device *dev = cxt->dev; + struct cxl_dport *dport; + struct cxl_port *root_port = cxt->root_port; + struct range chbs_range = { + .start = chbs->base, + .end = chbs->base + chbs->length - 1, + }; + + if (chbs->cxl_version > 1) { + dev_err(dev, "CHBS Unsupported CXL Version\n"); + return -EINVAL; + } + + if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) + return 0; + + if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL20 && + (chbs->length != ACPI_CEDT_CHBS_LENGTH_CXL20)) { + dev_err(dev, "Platform does not support CXL 2.0\n"); + return -EINVAL; + } + + device_lock(&root_port->dev); + list_for_each_entry(dport, &root_port->dports, list) { + struct range dport_range = { + .start = dport->component_reg_phys, + .end = dport->component_reg_phys + + CXL_COMPONENT_REG_BLOCK_SIZE - 1, + }; + + if (range_overlaps(&chbs_range, &dport_range)) { + device_unlock(&root_port->dev); + dev_err(dev, "CHBS overlapping Base and Length pair\n"); + return -EINVAL; + } + } + device_unlock(&root_port->dev); + + return 0; +} + static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg, const unsigned long end) { struct cxl_chbs_context *ctx = arg; struct acpi_cedt_chbs *chbs; + int ret; if (ctx->chbcr) return 0; @@ -203,6 +254,11 @@ static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg, if (ctx->uid != chbs->uid) return 0; + + ret = cxl_acpi_chbs_verify(ctx, chbs); + if (ret) + return ret; + ctx->chbcr = chbs->base; return 0; @@ -232,6 +288,7 @@ static int add_host_bridge_dport(struct device *match, void *arg) ctx = (struct cxl_chbs_context) { .dev = host, .uid = uid, + .root_port = root_port, }; acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx); @@ -321,11 +378,12 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (rc < 0) return rc; - if (IS_ENABLED(CONFIG_CXL_PMEM)) + if (IS_ENABLED(CONFIG_CXL_PMEM)) { rc = device_for_each_child(&root_port->dev, root_port, add_root_nvdimm_bridge); - if (rc < 0) - return rc; + if (rc < 0) + return rc; + } /* In case PCI is scanned before ACPI re-trigger memdev attach */ return cxl_bus_rescan();