From patchwork Wed Jun 22 15:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12891082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC471C433EF for ; Wed, 22 Jun 2022 15:59:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D71F410E331; Wed, 22 Jun 2022 15:59:38 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 831D410E06D; Wed, 22 Jun 2022 15:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655913577; x=1687449577; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+oWawLW5x76eQ8FSPMfpqs+KiYOP18G37bBE13XEY3c=; b=fCwKjesB+mU0DiHwIbGt+qi6PaaEwYn2JQVFYz+meTUIYjNSA3hyShQw UFl2A/jPJdhFfUOTPvJBpNwJChncg4vYmhvX1hx4IeQjr5jKiNZqHzrE2 JeNk6W4yqrR9UgOrqC5wO7jqUFY3zq5MWPkBCCE4Fw9TyfSXvJDK3pGft 3z7fBk/J2Vgrj4OBgdwpRXfMghuoYKFkICvlfPHsVM7ssROFV2cpywFQp I516/z//enEN7Q/T7m8IOORledrVgAMSMi+yhG8Y8vWf7MGkrdrcVtjOE gjJErZjvW4aooE2SiVo/DVEgL9dbZlRP0sco2DeO4lrpN3GLbHGhapCkh Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="366780722" X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="366780722" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2022 08:59:36 -0700 X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="677620734" Received: from conormag-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.201.124]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2022 08:59:35 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH] drm/i915: tweak the ordering in cpu_write_needs_clflush Date: Wed, 22 Jun 2022 16:59:19 +0100 Message-Id: <20220622155919.355081-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Gwan-gyeong Mun Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For imported dma-buf objects we leave the object as cache_coherent = 0 across all platforms, which is reasonable given that have no clue what the memory underneath is, and its not like the driver can ever manually clflush the pages anyway (like with i915_gem_clflush_object) for such objects. However on discrete we choose to treat cache_dirty = true as a programmer error, leading to a warning. The simplest fix looks to be to just change the ordering in cpu_write_needs_clflush to prevent ever setting cache_dirty for dma-buf objects on discrete. Fixes: d028a7690d87 ("drm/i915/dmabuf: Fix prime_mmap to work when using LMEM") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5266 Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Gwan-gyeong Mun Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 3e5d6057b3ef..1674b0c5802b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -35,12 +35,12 @@ bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj) if (obj->cache_dirty) return false; - if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) - return true; - if (IS_DGFX(i915)) return false; + if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) + return true; + /* Currently in use by HW (display engine)? Keep flushed. */ return i915_gem_object_is_framebuffer(obj); }