From patchwork Wed Jun 22 18:50:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D27BC43334 for ; Wed, 22 Jun 2022 18:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377004AbiFVStU (ORCPT ); Wed, 22 Jun 2022 14:49:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376901AbiFVStQ (ORCPT ); Wed, 22 Jun 2022 14:49:16 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E4793190F; Wed, 22 Jun 2022 11:49:14 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id j5-20020a05600c1c0500b0039c5dbbfa48so171853wms.5; Wed, 22 Jun 2022 11:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JD3CVhGzKJhodjIuzbpzEj7UlthG3ar21iKOAqvLQWM=; b=oUqmK21G3oZkJSHALOK5ExZoZYR16MMpn6p/2TTR6XaiEed3ycYvMLlh6EaOzzOI5o Nu6QE6R0u3A1PxhowLKnisWwmnDE5Wys5ZFDW5Ix7p8AdvA9AoX7zPZZk/NcrE+DnN3h ef/7u+vba2ib5acU2Z+oi1XVzj6qnH87VMajAYbwisc93FqzqbLRu9DNCgIx/F5O2qX7 glKKupcTPaYgygvdthQi6BwZ+o0jGcir1otko8COacrHRPtkTdmNqTNKRUNKrs69zK1f y0zHID0ICEpn6IXiLTa4/xecwLEPG9Udl3af8OLQ6nEjdUvrKmY7qa0w2+D57crLDu1b eo/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JD3CVhGzKJhodjIuzbpzEj7UlthG3ar21iKOAqvLQWM=; b=HigK2ulrzSxfMDDC105wGcDoLzeazBYC9RDLv8I7iMmb3Ck3a3cGxBSgaQGTpJXsxP v7+8GlAUweoJB+swy137XhDOw2uw6UzirWT/lHrabtDbEz//RrlxdmS/eCxdA+QQe7IJ m8sF19NBEpu1LNk6Rh70yySkOZwCa3p3NV9k+/4+Av038j/jZ1hWqdczhecYRLphj+dF KJ8DlA4jSL5wXh6kQyKcPPh8Y9d210otbyMj+ejbLq+ukhPx9OyOh8X/jrkp98gsjM5o v4w8isfoBmUgNqtIoNNQrtx3YPQZE211+5Q8M2zSx0v7k1yc98d0iKH6zG7CeX3/l8VB 4uzw== X-Gm-Message-State: AOAM531+h1uo/3pWtWqSui33vGf99OrTAOP+8eHO0MBsIgVINKGYmU0P 98XjC8SDwFRSDuQtufM3Gpw= X-Google-Smtp-Source: ABdhPJwbSyiTrTY4YBQUfINu5k4GadZYjwdDcZ0/jFR5c5k+WAzLMBPnYUV25uKeZLddPIzVZIbiew== X-Received: by 2002:a05:600c:4fd2:b0:39b:893e:ff79 with SMTP id o18-20020a05600c4fd200b0039b893eff79mr47380325wmq.73.1655923752715; Wed, 22 Jun 2022 11:49:12 -0700 (PDT) Received: from localhost (92.40.170.233.threembb.co.uk. [92.40.170.233]) by smtp.gmail.com with ESMTPSA id bp17-20020a5d5a91000000b0021b9870049dsm6015489wrb.82.2022.06.22.11.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 11:49:12 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org Cc: paul@crapouillou.net, maz@kernel.org, andy.shevchenko@gmail.com, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] pinctrl: ingenic: Use irqd_to_hwirq() Date: Wed, 22 Jun 2022 19:50:09 +0100 Message-Id: <20220622185010.2022515-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220622185010.2022515-1-aidanmacdonald.0x0@gmail.com> References: <20220622185010.2022515-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Instead of accessing ->hwirq directly, use irqd_to_hwirq(). Suggested-by: Andy Shevchenko Acked-by: Marc Zyngier Reviewed-by: Paul Cercueil Reviewed-by: Andy Shevchenko Signed-off-by: Aidan MacDonald --- drivers/pinctrl/pinctrl-ingenic.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 1ca11616db74..69e0d88665d3 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3393,7 +3393,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - int irq = irqd->hwirq; + irq_hw_number_t irq = irqd_to_hwirq(irqd); if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); @@ -3405,7 +3405,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - int irq = irqd->hwirq; + irq_hw_number_t irq = irqd_to_hwirq(irqd); if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); @@ -3417,7 +3417,7 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - int irq = irqd->hwirq; + irq_hw_number_t irq = irqd_to_hwirq(irqd); if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); @@ -3433,7 +3433,7 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - int irq = irqd->hwirq; + irq_hw_number_t irq = irqd_to_hwirq(irqd); ingenic_gpio_irq_mask(irqd); @@ -3449,7 +3449,7 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - int irq = irqd->hwirq; + irq_hw_number_t irq = irqd_to_hwirq(irqd); bool high; if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && @@ -3477,6 +3477,7 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + irq_hw_number_t irq = irqd_to_hwirq(irqd); switch (type) { case IRQ_TYPE_EDGE_BOTH: @@ -3498,12 +3499,12 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) * best we can do is to set up a single-edge interrupt and then * switch to the opposing edge when ACKing the interrupt. */ - bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); + bool high = ingenic_gpio_get_value(jzgc, irq); type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; } - irq_set_type(jzgc, irqd->hwirq, type); + irq_set_type(jzgc, irq, type); return 0; } @@ -3668,20 +3669,22 @@ static const struct pinctrl_ops ingenic_pctlops = { static int ingenic_gpio_irq_request(struct irq_data *data) { struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + irq_hw_number_t irq = irqd_to_hwirq(data); int ret; - ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); + ret = ingenic_gpio_direction_input(gpio_chip, irq); if (ret) return ret; - return gpiochip_reqres_irq(gpio_chip, data->hwirq); + return gpiochip_reqres_irq(gpio_chip, irq); } static void ingenic_gpio_irq_release(struct irq_data *data) { struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + irq_hw_number_t irq = irqd_to_hwirq(data); - return gpiochip_relres_irq(gpio_chip, data->hwirq); + return gpiochip_relres_irq(gpio_chip, irq); } static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, From patchwork Wed Jun 22 18:50:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F032CCA481 for ; Wed, 22 Jun 2022 18:49:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377056AbiFVStU (ORCPT ); Wed, 22 Jun 2022 14:49:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376918AbiFVStR (ORCPT ); Wed, 22 Jun 2022 14:49:17 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E60BC31917; Wed, 22 Jun 2022 11:49:15 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id o8so24706309wro.3; Wed, 22 Jun 2022 11:49:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DqFQG0CU8wtdroHFAZ6bAEVb5kwNC8YHs7EBfsOyGTE=; b=dkGTYPc1bdYnSwGmeGjAEVF250w9M54Jr41s7xjjWmr1xoijLuaMIuTcb2t/eM35w6 HtlesbcBnA1t7vg6OptOG9oQ9X4j0pt5K+2k9/tDM5usGv1h4s3ErM+um0RuMdRY/Spm R6IP2blAreFB1gSVp8T9iNdzucCIhcCY7C06RtESae+iE3xAAKiEDn9DNF1nUXxv9QHK 8RX2/hID9p695bZgAWgCTKegqssjF0dgGyQ8ycnC4CLFoQ2mSWFidn3Zcj+Zs4Bwu0Hu e/ZSr50H183t5LPZ4SeCbHj5A4vOYppCgx4tiqrCfrin06OtWwV8tP9aOCojjtkoFx3O w9Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DqFQG0CU8wtdroHFAZ6bAEVb5kwNC8YHs7EBfsOyGTE=; b=FXZ1IbxE6DOPrywf0GNR7jnil8mSg/wnkq4zq6L+2WTgnMvJrOij4Fog7pPDEqBIfM iVMPhjwmT0dkvO5IDabl+hdInZECbYcsqWuzcj8BEOg/n2T4OtBfA0/SmpjFjXYG5E/B 4dJB23WgVnMXvIrZ4Nj/MLmxav9ryRymqJ00BZxXLydJbCOR7mSLFvZ6kZQbHUsn6BKd HSpz91yj1N4qL3LMNPYUhATNmWSQH9uLwHzhsM+s8LDrREg8hFXNE8HUuDDAGLdiQBCx EjdnNLhGWuo1C8xXRZuJEmLrWAVRpL7Ub2pqOVkebBst4sJq/hhn2+mow+37Sexu1qWN kHBg== X-Gm-Message-State: AJIora+hfNx3nXc8abSxnV/6jejxFv2mUJQ+MqCrchCv72xwCNjfjw4O l6TosR9vHe2mQy69FArYyok= X-Google-Smtp-Source: AGRyM1vkB15KESXtruheH66NvVNQPfrMR+Ebv7PozqjW0fgpTFmRvOOMoCed61LAjw+FsF1ZtIW/XA== X-Received: by 2002:a5d:4e83:0:b0:21b:9dee:d109 with SMTP id e3-20020a5d4e83000000b0021b9deed109mr4859661wru.430.1655923754540; Wed, 22 Jun 2022 11:49:14 -0700 (PDT) Received: from localhost (92.40.170.233.threembb.co.uk. [92.40.170.233]) by smtp.gmail.com with ESMTPSA id 1-20020a05600c248100b0039c5ab7167dsm177431wms.48.2022.06.22.11.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 11:49:13 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org Cc: paul@crapouillou.net, maz@kernel.org, andy.shevchenko@gmail.com, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] pinctrl: ingenic: Convert to immutable irq chip Date: Wed, 22 Jun 2022 19:50:10 +0100 Message-Id: <20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220622185010.2022515-1-aidanmacdonald.0x0@gmail.com> References: <20220622185010.2022515-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Update the driver to use an immutable IRQ chip to fix this warning: "not an immutable chip, please consider fixing it!" Preserve per-chip labels by adding an ->irq_print_chip() callback. Acked-by: Marc Zyngier Reviewed-by: Paul Cercueil Reviewed-by: Andy Shevchenko Signed-off-by: Aidan MacDonald --- drivers/pinctrl/pinctrl-ingenic.c | 41 ++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 69e0d88665d3..3a9ee9c8af11 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "core.h" @@ -135,7 +136,6 @@ struct ingenic_pinctrl { struct ingenic_gpio_chip { struct ingenic_pinctrl *jzpc; struct gpio_chip gc; - struct irq_chip irq_chip; unsigned int irq, reg_base; }; @@ -3419,6 +3419,8 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); irq_hw_number_t irq = irqd_to_hwirq(irqd); + gpiochip_enable_irq(gc, irq); + if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) @@ -3443,6 +3445,8 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); + + gpiochip_disable_irq(gc, irq); } static void ingenic_gpio_irq_ack(struct irq_data *irqd) @@ -3687,6 +3691,27 @@ static void ingenic_gpio_irq_release(struct irq_data *data) return gpiochip_relres_irq(gpio_chip, irq); } +static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + + seq_printf(p, "%s", gpio_chip->label); +} + +static const struct irq_chip ingenic_gpio_irqchip = { + .irq_enable = ingenic_gpio_irq_enable, + .irq_disable = ingenic_gpio_irq_disable, + .irq_unmask = ingenic_gpio_irq_unmask, + .irq_mask = ingenic_gpio_irq_mask, + .irq_ack = ingenic_gpio_irq_ack, + .irq_set_type = ingenic_gpio_irq_set_type, + .irq_set_wake = ingenic_gpio_irq_set_wake, + .irq_request_resources = ingenic_gpio_irq_request, + .irq_release_resources = ingenic_gpio_irq_release, + .irq_print_chip = ingenic_gpio_irq_print_chip, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, +}; + static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, int pin, int func) { @@ -4175,20 +4200,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, if (!jzgc->irq) return -EINVAL; - jzgc->irq_chip.name = jzgc->gc.label; - jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; - jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; - jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; - jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; - jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; - jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; - jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; - jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; - jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; - jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; - girq = &jzgc->gc.irq; - girq->chip = &jzgc->irq_chip; + gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip); girq->parent_handler = ingenic_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),