From patchwork Fri Jun 24 09:00:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 12894206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45285C43334 for ; Fri, 24 Jun 2022 09:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=tZ2CusS22X3KBslKel/+/JpF2lKtxGPN8sESaCmFaNA=; b=MHh9Pobkt6PBVc tE0/M1IGrHlPvSmssZpApuWkwkXoJKfnEdWqqyQ0xNcAX/K2A+GXm5CaHgyCCwQInORbHWFbfHJxS IaWyEeSwRJaPKxwZjhmQNUWnMTY2YIYjy0g5nPABIYPTUjKVqDcTlmnmOQ87by51YpFkoUS+7AUBq OJRGhJ0FtdHvaB4/VLgm48Pt0Wf5WyViHPX9PP8N/o119DG9bN/rw+hLkD5CWjHKTjtQVlnPXFzSW AnBZfrSoeuE4vjA5yWwrq50mv2xdrC8M/DhbSwKAoKW2yXXEjHoDACPNHuBTKgSK3iq7+Z8asubD/ CKUUM3xHseefWdBFnNrw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4fCU-001KIY-Cq; Fri, 24 Jun 2022 09:02:02 +0000 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4fCR-001KEY-6S for linux-arm-kernel@lists.infradead.org; Fri, 24 Jun 2022 09:02:00 +0000 Received: by mail-wm1-x331.google.com with SMTP id 189so445813wmz.2 for ; Fri, 24 Jun 2022 02:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DYqi+SGcB0+t2X+VYlC5fZRvt40T3yhMiNazUS1RDXg=; b=KTYM3gqN0dbVx0MMpORszENXRVGhqUN/bTd+qbPxDHuW4jPEtauSJwiVkn98ROISpr idy6ijgKO6qKA0rE95x5zivQtOETae5BhPw1v4j0c646Qc/6i3unmDqArgdPI4e9hLoI MN7bC75nrHoxtLMWdIi+tXEHI52cjL61npeOLG1TP5owvNFkVxOdSauASv73mvfrKQoq C9GYBei1j3zCBHlu99Mgwc9i+BZdlSqTur0naohCBXLYYvvI6PddLqqEsIKEJG737wjB bE3EmaCI6ft4CWSLe+XkdpKbapkmLgcd/j3BheqsousuJcAcVv1ZysNs4ymDF0mTouMn NcSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DYqi+SGcB0+t2X+VYlC5fZRvt40T3yhMiNazUS1RDXg=; b=ABne1YnKtoKjSrw8u1wFjR4jPck7flb1GMlTAM2WK6R2M/6D8mp7M03Cj5bDNBctoj beOt4IEmh5kr9aAppiFRyRPPb7eaEHjo+2wYDxZr9sQeu4+VzqDwXhLweqb6PHFnPqhp vqps6S0mokhQ0rWcBgqW2Z1B9JhRgekaxVLpsgab5aM4LlO5r35DBjT0j0fbrRBWItox x9uzxMEyGkLA0/+9i0AmXiJS0z5Kpz3afnuNG0AtKdIWjaznWnhjTeyRYlZiVfKEY6/E dF58H+Mh/eIra6zeaQ5RWUngUgwzBr/loPnkspHsZkRurYI6VQMEaJSZq7BgexECNEMP KsMQ== X-Gm-Message-State: AJIora9KVNvnE4PP6RA69vrRcbII5rpq2rGaxR8oajtWnCLnvEQMR7dj DhwCchHD8vVKQrytFbEejoRsoA== X-Google-Smtp-Source: AGRyM1vJblVpTyNWcE6m4PbaUdDUJM1SUYRY98T5uH//0OhEeRyez3qBnHqTgu2Krcaa4KOZaxCo9A== X-Received: by 2002:a05:600c:3b1f:b0:3a0:2f82:7d6b with SMTP id m31-20020a05600c3b1f00b003a02f827d6bmr2476743wms.3.1656061315059; Fri, 24 Jun 2022 02:01:55 -0700 (PDT) Received: from lmecxl1178.lme.st.com ([2a04:cec0:11eb:7fe2:cb1a:9cd7:1545:5dfc]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c1c0900b0039c7f790f6asm6717084wms.30.2022.06.24.02.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 02:01:54 -0700 (PDT) From: Etienne Carriere To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org, Alexandre Torgue , Maxime Coquelin , Krzysztof Kozlowski , Rob Herring , Etienne Carriere Subject: [PATCH] ARM: dts: stm32: fix pwr regulators references to use scmi Date: Fri, 24 Jun 2022 11:00:55 +0200 Message-Id: <20220624090055.569400-1-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220624_020159_308026_0EC8B716 X-CRM114-Status: GOOD ( 10.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR regulators through SCMI service. This is needed since enabling secure only access to RCC clock and reset controllers also enables secure access only on PWR voltage regulators reg11, reg18 and usb33 hence these must also be accessed through SCMI Voltage Domain protocol. This change applies on commit [2] that already corrects issues from commit [1]. Cc: Alexandre Torgue Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com Signed-off-by: Etienne Carriere Acked-by: Etienne Carriere Tested-by: Etienne Carriere --- arch/arm/boot/dts/stm32mp15-scmi.dtsi | 52 ++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 1 + arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 1 + 3 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi index e90cf3acd0b3..d2afb6667479 100644 --- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi @@ -27,6 +27,37 @@ scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; }; }; @@ -45,3 +76,24 @@ scmi_shm: scmi-sram@0 { }; }; }; + +®11 { + status = "disabled"; +}; + +®18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts index 03226a596904..97e4f94b0a24 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -35,6 +35,7 @@ &cryp1 { }; &dsi { + phy-dsi-supply = <&scmi_reg18>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts index 7842384ddbe4..3b9dd6f4ccc9 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -36,6 +36,7 @@ &cryp1 { }; &dsi { + phy-dsi-supply = <&scmi_reg18>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; };