From patchwork Fri Jun 24 09:08:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 12894227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ABCDC433EF for ; Fri, 24 Jun 2022 09:09:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230477AbiFXJJe (ORCPT ); Fri, 24 Jun 2022 05:09:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231365AbiFXJJX (ORCPT ); Fri, 24 Jun 2022 05:09:23 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A06E4EF74 for ; Fri, 24 Jun 2022 02:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656061761; x=1687597761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZKZs43CHcT22X/6Y5MnTtOwktTXOynRraWEPmaAvKg0=; b=KuDcNRgqIWsRuJWwrPlts1KTU1A3XMytUW1m/+rbkENAarEo9JBafg/J pxZPUC68PrsnSE2yvTcYmYm8S+y5LMktAK1y5pY/JEfpf1a2eCUxAkUI+ zKec0K3m/2gIWLzPeWgNqRWWFHrmxVZSJhyqKlfwlHh0Ot7zSE6LR9CuE mdZKvEVu/zNlLAMw/s8g8cAvF2V6YPuMk7zptjey/EHZxHjFLRqn2Mhru MbVDaAQkzM3MQ4oQQb+sksfbKozMWsq1VjY3ogR0Lx2qbL0lRi8j1DiKF 4N5ayT8wlp3+lTM8fGbvnVB+elr8Fx6wBKH9uopmkC79lKdc4DZl776TZ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10387"; a="278509307" X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="278509307" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="539222082" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, Yang Weijiang Subject: [PATCH v3 1/3] x86: Don't overwrite bits 11 and 12 of MSR_IA32_MISC_ENABLE Date: Fri, 24 Jun 2022 05:08:26 -0400 Message-Id: <20220624090828.62191-2-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220624090828.62191-1-weijiang.yang@intel.com> References: <20220624090828.62191-1-weijiang.yang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Paolo Bonzini Bits 11 and 12 of MSR_IA32_MISC_ENABLE represent the configuration of the vPMU, and latest KVM does not allow the guest to modify them. Adjust kvm-unit-tests to avoid failures. Signed-off-by: Paolo Bonzini Signed-off-by: Yang Weijiang --- x86/msr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/x86/msr.c b/x86/msr.c index 44fbb3b..8bf38ef 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -19,6 +19,7 @@ struct msr_info { bool is_64bit_only; const char *name; unsigned long long value; + unsigned long long keep; }; @@ -27,6 +28,8 @@ struct msr_info { #define MSR_TEST(msr, val, only64) \ { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64 } +#define MSR_TEST_RO_BITS(msr, val, only64, ro) \ + { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64, .keep = ro } struct msr_info msr_info[] = { @@ -34,7 +37,8 @@ struct msr_info msr_info[] = MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), + // read-only: 11, 12 + MSR_TEST_RO_BITS(MSR_IA32_MISC_ENABLE, 0x400c50009, false, 0x1800), MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), MSR_TEST(MSR_FS_BASE, addr_64, true), MSR_TEST(MSR_GS_BASE, addr_64, true), @@ -59,6 +63,8 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) */ if (msr->index == MSR_EFER) val |= orig; + else + val = (val & ~msr->keep) | (orig & msr->keep); wrmsr(msr->index, val); r = rdmsr(msr->index); wrmsr(msr->index, orig); From patchwork Fri Jun 24 09:08:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 12894225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CDD5C433EF for ; Fri, 24 Jun 2022 09:09:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230519AbiFXJJY (ORCPT ); Fri, 24 Jun 2022 05:09:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230338AbiFXJJV (ORCPT ); Fri, 24 Jun 2022 05:09:21 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6140A4EF7F for ; Fri, 24 Jun 2022 02:09:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656061760; x=1687597760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CgU0Fz/PQzuayBUIM5JbTAos8rVfs+5wDKXz0rUiW1c=; b=RFkF1u6UtEgzEUOTfX7EjQ+iuV+0Edr0287Bu7A0N3Vfj2dchaT4lXcO jAAz1T8yiG7RMkRSDIy+ONvZteGZX00Vh1rHwCw3Nl39NQkQ+KMwPxkID 3XMHU1RNvDw7Nid3rESfcdyR3cSi1s+skVuPZyo6DEJ8Bq1SREaDejACs Bs7J+HBO+9eFaAa8ExrxT80SoUUrpdSoe2xL6SnCa5+4TfWzjD2GTZjdm hPWxAWGjBurMweuG0lufX9I2xU9093Sx2jhg1ZS7/IYuq0MpBu4HtlwZO x2jdHB+xD368QlE+M4yPQEma+FmTMuKsXEKKI6zmdvNtKhOiEgNZxGt/7 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10387"; a="278509305" X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="278509305" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="539222086" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, Yang Weijiang Subject: [PATCH v3 2/3] x86: Skip perf related tests when platform cannot support Date: Fri, 24 Jun 2022 05:08:27 -0400 Message-Id: <20220624090828.62191-3-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220624090828.62191-1-weijiang.yang@intel.com> References: <20220624090828.62191-1-weijiang.yang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add helpers to check whether MSR_CORE_PERF_GLOBAL_CTRL and rdpmc are supported in KVM. When pmu is disabled with enable_pmu=0, reading MSR_CORE_PERF_GLOBAL_CTRL or executing rdpmc leads to #GP, so skip related tests in this case to avoid test failure. Signed-off-by: Yang Weijiang --- lib/x86/processor.h | 10 ++++++++++ x86/vmx_tests.c | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 9a0dad6..70b9193 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -690,4 +690,14 @@ static inline bool cpuid_osxsave(void) return cpuid(1).c & (1 << (X86_FEATURE_OSXSAVE % 32)); } +static inline u8 pmu_version(void) +{ + return cpuid(10).a & 0xff; +} + +static inline bool has_perf_global_ctrl(void) +{ + return pmu_version() > 1; +} + #endif diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 4d581e7..3cf0776 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -944,6 +944,14 @@ static void insn_intercept_main(void) continue; } + if (insn_table[cur_insn].flag == CPU_RDPMC) { + if (!!pmu_version()) { + printf("\tFeature required for %s is not supported.\n", + insn_table[cur_insn].name); + continue; + } + } + if (insn_table[cur_insn].disabled) { printf("\tFeature required for %s is not supported.\n", insn_table[cur_insn].name); @@ -7490,6 +7498,11 @@ static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, static void test_load_host_perf_global_ctrl(void) { + if (!has_perf_global_ctrl()) { + report_skip("test_load_host_perf_global_ctrl"); + return; + } + if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); return; @@ -7502,6 +7515,11 @@ static void test_load_host_perf_global_ctrl(void) static void test_load_guest_perf_global_ctrl(void) { + if (!has_perf_global_ctrl()) { + report_skip("test_load_guest_perf_global_ctrl"); + return; + } + if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); return; From patchwork Fri Jun 24 09:08:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 12894226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAEA2C433EF for ; Fri, 24 Jun 2022 09:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231373AbiFXJJb (ORCPT ); Fri, 24 Jun 2022 05:09:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231247AbiFXJJW (ORCPT ); Fri, 24 Jun 2022 05:09:22 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 122B34F1DD for ; Fri, 24 Jun 2022 02:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656061761; x=1687597761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5UgISola8I03cHb1gjJsUYZEvKvIFeYtnshjcKfjKrE=; b=aOLj0tWEEbFXVe1MSndm2VKrfl95w1c9kkwQSEylRCgTQux+Wkn9wJYm oVq4ifyNIGSJwCdXjvDvQS6zzyTcPc7u0G3DI8AlBqsO6n3nHMQs9ZmVQ xD+L5Aoo5Ik3TtOIvXGOQ0oviPziKwTilsAmd4eD97UMX9fgbqa8dkgt3 hXRnskHkW1rbhYaJby14+A870O2ErBD4xGygvZk1VlDMivhiYoY2YWedh godGswzFr7YTWkeWeIPROHU2ke3r9blxkg0TMMUQsBlIWkQuezTPQ5zmK oX6tvaKZ0j7iSaTurcxv6rfX8BxqdshdPkUVqLx8PE3OZZJMnp0MB7gsX g==; X-IronPort-AV: E=McAfee;i="6400,9594,10387"; a="278509306" X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="278509306" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 X-IronPort-AV: E=Sophos;i="5.92,218,1650956400"; d="scan'208";a="539222088" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 02:09:19 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, Yang Weijiang Subject: [PATCH v3 3/3] x86: Check platform vPMU capabilities before run lbr tests Date: Fri, 24 Jun 2022 05:08:28 -0400 Message-Id: <20220624090828.62191-4-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220624090828.62191-1-weijiang.yang@intel.com> References: <20220624090828.62191-1-weijiang.yang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Use new helper to check whether pmu is available and Perfmon/Debug capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to avoid test failure. The issue can be captured when enable_pmu=0. Signed-off-by: Yang Weijiang --- lib/x86/processor.h | 2 +- x86/pmu_lbr.c | 32 +++++++++++++------------------- 2 files changed, 14 insertions(+), 20 deletions(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 70b9193..bb917b0 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -193,7 +193,7 @@ static inline bool is_intel(void) #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) - +#define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) static inline bool this_cpu_has(u64 feature) { diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c index 688634d..497df1e 100644 --- a/x86/pmu_lbr.c +++ b/x86/pmu_lbr.c @@ -15,6 +15,7 @@ #define MSR_LBR_SELECT 0x000001c8 volatile int count; +u32 lbr_from, lbr_to; static noinline int compute_flag(int i) { @@ -38,18 +39,6 @@ static noinline int lbr_test(void) return 0; } -union cpuid10_eax { - struct { - unsigned int version_id:8; - unsigned int num_counters:8; - unsigned int bit_width:8; - unsigned int mask_length:8; - } split; - unsigned int full; -} eax; - -u32 lbr_from, lbr_to; - static void init_lbr(void *index) { wrmsr(lbr_from + *(int *) index, 0); @@ -63,7 +52,7 @@ static bool test_init_lbr_from_exception(u64 index) int main(int ac, char **av) { - struct cpuid id = cpuid(10); + u8 version = pmu_version(); u64 perf_cap; int max, i; @@ -74,19 +63,24 @@ int main(int ac, char **av) return 0; } - perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); - eax.full = id.a; - - if (!eax.split.version_id) { + if (!version) { printf("No pmu is detected!\n"); return report_summary(); } + + if (!this_cpu_has(X86_FEATURE_PDCM)) { + printf("Perfmon/Debug Capabilities MSR isn't supported\n"); + return report_summary(); + } + + perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); + if (!(perf_cap & PMU_CAP_LBR_FMT)) { - printf("No LBR is detected!\n"); + printf("(Architectural) LBR is not supported.\n"); return report_summary(); } - printf("PMU version: %d\n", eax.split.version_id); + printf("PMU version: %d\n", version); printf("LBR version: %ld\n", perf_cap & PMU_CAP_LBR_FMT); /* Look for LBR from and to MSRs */