From patchwork Fri Jun 24 17:15:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 12894900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA9F1CCA473 for ; Fri, 24 Jun 2022 17:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbiFXRP1 (ORCPT ); Fri, 24 Jun 2022 13:15:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbiFXRP1 (ORCPT ); Fri, 24 Jun 2022 13:15:27 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE51463634; Fri, 24 Jun 2022 10:15:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656090927; x=1687626927; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=1no4VHAGF1U1GUsWuXmPq+Xyz6dJE8ewgEUyCmjoW4U=; b=nsAW5nQI2PuSTbIWbsNm/DqHnS8AM9NdNZJG+Cbm1mh6ipPe4KMHwK39 F5a4fYrAw/H1ZDrCuFMmYkELGkU2e8QeTxX4LtPuahv3Sg4K/mYmc5fsa U3ckMRCiVGZMP4m1HmIO7zklZ4Rp2b1sxhSQNkPg5+X19zqLznwQKBAr3 o=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 24 Jun 2022 10:15:26 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 10:15:25 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:25 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:24 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v1 1/3] drm/msm/dp: move struc of msm_display_info to msm_drv.h Date: Fri, 24 Jun 2022 10:15:10 -0700 Message-ID: <1656090912-18074-2-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> References: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With current implementation, communication between interface driver and upper mdss encoder layer are implemented through function calls. This increase code complexity. Since struct msm_display_info contains msm generic display information, it can be expended to contains more useful information, such as widebus and dcs, in future to serve as communication channel purpose between interface driver and upper mdss encoder layer so that existing function calls can be eliminated. This patch more struct msm_display_info to msm_drv.h to be visible by whole msm scope. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 20 -------------------- drivers/gpu/drm/msm/msm_drv.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 781d41c..6b604c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -19,26 +19,6 @@ #define IDLE_TIMEOUT (66 - 16/2) /** - * struct msm_display_info - defines display properties - * @intf_type: DRM_MODE_ENCODER_ type - * @capabilities: Bitmask of display flags - * @num_of_h_tiles: Number of horizontal tiles in case of split interface - * @h_tile_instance: Controller instance used per tile. Number of elements is - * based on num_of_h_tiles - * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is - * used instead of panel TE in cmd mode panels - * @dsc: DSC configuration data for DSC-enabled displays - */ -struct msm_display_info { - int intf_type; - uint32_t capabilities; - uint32_t num_of_h_tiles; - uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; - bool is_te_using_watchdog_timer; - struct msm_display_dsc_config *dsc; -}; - -/** * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to * @encoder: encoder pointer * @crtc: crtc pointer diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index fdbaad5..f9c263b 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -106,11 +106,30 @@ struct msm_drm_thread { struct kthread_worker *worker; }; +<<<<<<< HEAD /* DSC config */ struct msm_display_dsc_config { struct drm_dsc_config *drm; }; +/** + * struct msm_display_info - defines display properties + * @intf_type: DRM_MODE_ENCODER_ type + * @capabilities: Bitmask of display flags + * @num_of_h_tiles: Number of horizontal tiles in case of split interface + * @h_tile_instance: Controller instance used per tile. Number of elements is + * based on num_of_h_tiles + * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is + * used instead of panel TE in cmd mode panels + */ +struct msm_display_info { + int intf_type; + uint32_t capabilities; + uint32_t num_of_h_tiles; + uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; + bool is_te_using_watchdog_timer; +}; + struct msm_drm_private { struct drm_device *dev; From patchwork Fri Jun 24 17:15:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 12894901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1450C433EF for ; Fri, 24 Jun 2022 17:15:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232025AbiFXRPa (ORCPT ); Fri, 24 Jun 2022 13:15:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232022AbiFXRP2 (ORCPT ); Fri, 24 Jun 2022 13:15:28 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 128DD63631; Fri, 24 Jun 2022 10:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656090928; x=1687626928; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=NddpGk/hbDeyIsIAOJl8eVnfk95qc1EZrjqf8uaTXws=; b=Gt027N5ryn7AFUP0kVmtF/Tl+N7ozyN6hpC7Q/u9RlHvoM+QkzHwpIFN MxfZyXs8n5yYjBOwf37w7bYoVSxaiMDB17Kg1wd2kplcxnrViWxN6hr4X W/KLBYWwLfLqvGoQwzgUEut8uqvM6SVMOoQY204YwRe5m7FFco9M6FyeW 0=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Jun 2022 10:15:27 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 10:15:27 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:26 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:26 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v1 2/3] drm/msm/dp: decoupling dp->id out of dp controller_id at scxxxx_dp_cfg table Date: Fri, 24 Jun 2022 10:15:11 -0700 Message-ID: <1656090912-18074-3-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> References: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Current the index (dp->id) of DP descriptor table (scxxxx_dp_cfg[]) are tightly coupled with DP controller_id. This means DP use controller id 0 must be placed at first entry of DP descriptor table (scxxxx_dp_cfg[]). Otherwise the internal INTF will mismatch controller_id. This will cause controller kickoff wrong interface timing engine and cause dpu_encoder_phys_vid_wait_for_commit_done vblank timeout error. This patch add controller_id field into struct msm_dp_desc to break the tightly coupled relationship between index (dp->id) of DP descriptor table with DP controller_id. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 ++++++++++------ drivers/gpu/drm/msm/dp/dp_display.c | 30 +++++++++++++++++++++++------- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 2b9d931..8feeb89 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -615,7 +615,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, struct dpu_kms *dpu_kms) { struct drm_encoder *encoder = NULL; - struct msm_display_info info; + struct msm_display_info *info; int rc; int i; @@ -637,11 +637,15 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, return rc; } - info.num_of_h_tiles = 1; - info.h_tile_instance[0] = i; - info.capabilities = MSM_DISPLAY_CAP_VID_MODE; - info.intf_type = encoder->encoder_type; - rc = dpu_encoder_setup(dev, encoder, &info); + info = &priv->info[i]; + info->intf_type = encoder->encoder_type; + /* + * info->capabilities, info->num_of_h_tiles and + * info->h_tile_instance are populated at + * dp_display_bind() + */ + + rc = dpu_encoder_setup(dev, encoder, info); if (rc) { DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", encoder->base.id, rc); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index da5c03a..a87a9d8 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -77,6 +77,7 @@ struct dp_display_private { int irq; unsigned int id; + unsigned int controller_id; /* state variables */ bool core_initialized; @@ -123,6 +124,7 @@ struct dp_display_private { struct msm_dp_desc { phys_addr_t io_start; unsigned int connector_type; + unsigned int controller_id; bool wide_bus_en; }; @@ -133,31 +135,38 @@ struct msm_dp_config { static const struct msm_dp_config sc7180_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0 }, }, .num_descs = 1, }; static const struct msm_dp_config sc7280_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, + { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, + .controller_id = MSM_DP_CONTROLLER_1, .wide_bus_en = true }, }, .num_descs = 2, }; static const struct msm_dp_config sc8180x_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - [MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP }, + {.io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP, + .controller_id = MSM_DP_CONTROLLER_2 }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0 }, + { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_1 }, }, .num_descs = 3, }; static const struct msm_dp_config sm8350_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0 }, }, .num_descs = 1, }; @@ -260,10 +269,16 @@ static int dp_display_bind(struct device *dev, struct device *master, struct dp_display_private *dp = dev_get_dp_display_private(dev); struct msm_drm_private *priv = dev_get_drvdata(master); struct drm_device *drm = priv->dev; + struct msm_display_info *info; dp->dp_display.drm_dev = drm; priv->dp[dp->id] = &dp->dp_display; + info = &priv->info[dp->id]; + info->num_of_h_tiles = 1; + info->h_tile_instance[0] = dp->controller_id; + info->capabilities = MSM_DISPLAY_CAP_VID_MODE; + rc = dp->parser->parse(dp->parser); if (rc) { DRM_ERROR("device tree parsing failed\n"); @@ -1308,6 +1323,7 @@ static int dp_display_probe(struct platform_device *pdev) dp->pdev = pdev; dp->name = "drm_dp"; dp->dp_display.connector_type = desc->connector_type; + dp->controller_id = desc->controller_id; dp->wide_bus_en = desc->wide_bus_en; dp->dp_display.is_edp = (dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f9c263b..71ab699 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -150,6 +150,8 @@ struct msm_drm_private { struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; + struct msm_display_info info[MSM_DP_CONTROLLER_COUNT]; + /* when we have more than one 'msm_gpu' these need to be an array: */ struct msm_gpu *gpu; From patchwork Fri Jun 24 17:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 12894902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BD5CCCA473 for ; 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Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Jun 2022 10:15:29 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2022 10:15:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:28 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 24 Jun 2022 10:15:27 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v1 3/3] drm/msm/dp: place edp at head of drm bridge chain to fix screen corruption Date: Fri, 24 Jun 2022 10:15:12 -0700 Message-ID: <1656090912-18074-4-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> References: <1656090912-18074-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The msm_dp_modeset_init() is used to attach DP driver to drm bridge chain. msm_dp_modeset_init() is executed in the order of index (dp->id) of DP descriptor table. Currently, DP is placed at first entry (dp->id = 0) of descriptor table and eDP is placed at secondary entry (dp->id = 1 ) of descriptor table. This means DP will be placed at head of bridge chain and eDP will be placed right after DP at bridge chain. Drm screen update is happen sequentially in the order from head to tail of bridge chain. Therefore external DP display will have screen updated happen before primary eDP display if external DP display presented. This is wrong screen update order and cause one frame time screen corruption happen at primary display during external DP plugged in. This patch place eDP at first entry (dp->id = 0) of descriptor table and place DP at secondary entry (dp->id = 1) to have primary eDP locate at head of bridge chain. This correct screen update order and eliminated the one frame time screen corruption happen d at primary display. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index a87a9d8..2755ff3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -143,10 +143,10 @@ static const struct msm_dp_config sc7180_dp_cfg = { static const struct msm_dp_config sc7280_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, - .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .controller_id = MSM_DP_CONTROLLER_1, .wide_bus_en = true }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, }, .num_descs = 2, };