From patchwork Mon Jun 27 05:12:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12896201 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3422CCA47E for ; Mon, 27 Jun 2022 05:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231635AbiF0FNE (ORCPT ); Mon, 27 Jun 2022 01:13:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbiF0FNC (ORCPT ); Mon, 27 Jun 2022 01:13:02 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F013888; Sun, 26 Jun 2022 22:13:01 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 005F65C019D; Mon, 27 Jun 2022 01:13:01 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Mon, 27 Jun 2022 01:13:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1656306780; x= 1656393180; bh=6AYLrxKS1kGzYaCKlRypTFspscTKmPnJSs3erP6wz1w=; b=k dOF4mlRrncMvmxqTBXFJv0uZzvqiAuA+WGEzPTn1W4cS/eLTvrJDBvrEZZp2bSwZ u8/u7FBDthN7jNyokEAYT9XDrp57cBNVFkxbzELBBeVpTl4PKRfPYfZ9EWzrEvEL mNapWNuvdj65vengO3Q33z9Csoim9rZ6aUYx704JQrdrzeLc5j3/X9MJBwD30gOl OT2ZdySuFgrZag3Fum3cqIQn9DrkZq+1gt27KmR/m6kLAhRtJOEfCAwabJpC5+Y2 jewJHdzY51M/RV1VykQ5FcXQ4+7H9mFxrN2Q7apOUOEKd3Y5GmtI6diXBfjG0NFw DGTU/YyVdMUZBHPvUadfA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1656306780; x= 1656393180; bh=6AYLrxKS1kGzYaCKlRypTFspscTKmPnJSs3erP6wz1w=; b=E shgTd6PCY3pBsBTMsG1M4fmh046VCXqVhwm76Mn1oFAI53fiehbtRxEGH/xj4jYt Rq6Vmk1fh56mWkECA6TugPJBhiw3PhdDjUHnkmc/Cm4gNf8Y/QJII1XuFmYJ0aqu LUUSJ8feloAHkrGq7CcT82KL3D6QtvDmdTUn3r/EODHfQ8vsGfl0sJneLiqsk/Zb wc9Q53+dZpq2hcqlBA72o4jBWK4yvXNrEJUGcEqysqs+jmx47CIv3/Aa0BJ29EYw fz+aIJCmbX5bcqZLtZxJd45PiZ3s1JRDT1dFE0V9Wlu71zB9T0XDb/kGGe/QfQcu n0YFwQ+R+SYDG8WmW8xzg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudeggedgkeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpefurghm uhgvlhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenuc ggtffrrghtthgvrhhnpeefueevueeffeelheelhfelgeelgffgieekffevteefveejueei teeugfefieehleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 27 Jun 2022 01:13:00 -0400 (EDT) From: Samuel Holland To: Lad Prabhakar , Prabhakar , Marc Zyngier , Sagar Kadam , Paul Walmsley , Palmer Dabbelt Cc: linux-renesas-soc@vger.kernel.org, Guo Ren , Geert Uytterhoeven , Thomas Gleixner , Biju Das , Samuel Holland , Albert Ou , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Mon, 27 Jun 2022 00:12:55 -0500 Message-Id: <20220627051257.38543-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220627051257.38543-1-samuel@sholland.org> References: <20220627051257.38543-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RISC-V PLIC specification unfortunately allows PLIC implementations to ignore edges seen while an edge-triggered interrupt is being handled: Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. For PLICs with that misfeature, software needs to know the trigger type of each interrupt. This allows it to work around the issue by completing edge-triggered interrupts before handling them. Such a workaround is required to avoid missing any edges. The T-HEAD C9xx PLIC is an example of a PLIC with this behavior. Signed-off-by: Samuel Holland Reviewed-by: Guo Ren --- .../sifive,plic-1.0.0.yaml | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..3c589cbca851 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -26,9 +26,13 @@ description: with priority below this threshold will not cause the PLIC to raise its interrupt line leading to the context. - While the PLIC supports both edge-triggered and level-triggered interrupts, - interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + The PLIC supports both edge-triggered and level-triggered interrupts. For + edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges + seen while an interrupt handler is active; the PLIC may either queue them or + ignore them. In the first case, handlers are oblivious to the trigger type, so + it is not included in the interrupt specifier. In the second case, software + needs to know the trigger type, so it can reorder the interrupt flow to avoid + missing interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -65,7 +69,8 @@ properties: const: 0 '#interrupt-cells': - const: 1 + minimum: 1 + maximum: 2 interrupt-controller: true @@ -91,6 +96,24 @@ required: - interrupts-extended - riscv,ndev +allOf: + - if: + properties: + compatible: + contains: + enum: + - thead,c900-plic + + then: + properties: + '#interrupt-cells': + const: 2 + + else: + properties: + '#interrupt-cells': + const: 1 + additionalProperties: false examples: From patchwork Mon Jun 27 05:12:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12896202 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07F83C433EF for ; Mon, 27 Jun 2022 05:13:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231859AbiF0FNE (ORCPT ); Mon, 27 Jun 2022 01:13:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231561AbiF0FND (ORCPT ); Mon, 27 Jun 2022 01:13:03 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC0902BFB; Sun, 26 Jun 2022 22:13:02 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 2CD7A5C00E5; Mon, 27 Jun 2022 01:13:02 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Mon, 27 Jun 2022 01:13:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm3; t=1656306782; x=1656393182; bh=90 4GOKdujIzG+lXqqN6R8S+IQA88lTLYQXPZ4MZDHfo=; b=gU6c+UQZzR1bHbD0Y0 Y1X5WqhqLKS2qzLBp6VZODkeZTrum83ll8H11JMZ3hPJdIlMIzviMLlvreyxm39G zmxRkOjWWX39Nov4ktAzMPh9SjtFNnLpZ9+5xrMeZ3k67mmUHUuChpCQeK/rGi51 E1BdZKd8zhnufI/psv9K3IIDMlGkMZbKTKHxwYDodzik0xc2ZpwlTtUNVYl6tqGV /+1UCT+31x1SbGGI+KApCZFrFGyKegDem+YT5OvrOgI3zY9WMS1uR2UCZd4OU6q7 cvQis7mIeu5Y7uCZisuWXc0fQAte/LdGtFhSYYKNqxt0brOkfOyiqr3ZpULTg4VI pWxQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; t=1656306782; x=1656393182; bh=904GOKdujIzG+ lXqqN6R8S+IQA88lTLYQXPZ4MZDHfo=; b=O74T68806yX33KKUD/DLjemFcyheQ WOrRA8Sit4G5xnWAJRPum7J+ml7yChGFvIurCkLTbl2QYtFrQGMdKGnzjaZzgsn4 NTNagGAUUrvBld67vpyIHVRSsrEnoUtiOPsPeE28P7ByB7B7igOjUwL9HAmV0gzR qgGyK2IW4bVtRa/UfmqkowomlRWrr5a5idXa3LceRjE4zd4i/dPBtvaJ177nyvEo 3jg5V6nrQ2DfWhdt4rHT7eNho5ONrUFfYncFk7w0564IIKULY18x1RzBRGzyM5uW 8T5l56IQyEnasax99fyg8ENHS8GJFduf88PfSAAStZYBPfeIaY/mbU8Hg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudeggedgkeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepkeeuueeuheelgeeuhfeutdelieffveetieeftdfgfeeiteekudet leeuueeljeevnecuffhomhgrihhnpehgihhthhhusgdrtghomhenucevlhhushhtvghruf hiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhhohhllhgr nhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 27 Jun 2022 01:13:01 -0400 (EDT) From: Samuel Holland To: Lad Prabhakar , Prabhakar , Marc Zyngier , Sagar Kadam , Paul Walmsley , Palmer Dabbelt Cc: linux-renesas-soc@vger.kernel.org, Guo Ren , Geert Uytterhoeven , Thomas Gleixner , Biju Das , Samuel Holland , Albert Ou , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 2/3] irqchip/sifive-plic: Name the chip more generically Date: Mon, 27 Jun 2022 00:12:56 -0500 Message-Id: <20220627051257.38543-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220627051257.38543-1-samuel@sholland.org> References: <20220627051257.38543-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The interface for SiFive's PLIC was adopted and clarified by RISC-V as the standard PLIC interface. Now that several PLIC implementations by different vendors share this same interface, it is somewhat misleading to report "SiFive PLIC" to userspace, when no SiFive hardware may be present. This is especially the case when some implementations are subtly incompatible with the binding and behavior of the SiFive PLIC, yet are similar enough to share a driver. Signed-off-by: Samuel Holland Reviewed-by: Guo Ren --- drivers/irqchip/irq-sifive-plic.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bb87e4c3b88e..90515865af08 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -28,6 +28,11 @@ * The largest number supported by devices marked as 'sifive,plic-1.0.0', is * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged * Spec. + * + * The PLIC behavior and memory map is futher formalized as an official RISC-V + * specification: + * + * https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc */ #define MAX_DEVICES 1024 @@ -177,12 +182,12 @@ static void plic_irq_eoi(struct irq_data *d) } static struct irq_chip plic_chip = { - .name = "SiFive PLIC", - .irq_mask = plic_irq_mask, - .irq_unmask = plic_irq_unmask, - .irq_eoi = plic_irq_eoi, + .name = "PLIC", + .irq_mask = plic_irq_mask, + .irq_unmask = plic_irq_unmask, + .irq_eoi = plic_irq_eoi, #ifdef CONFIG_SMP - .irq_set_affinity = plic_set_affinity, + .irq_set_affinity = plic_set_affinity, #endif }; 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Mon, 27 Jun 2022 01:13:02 -0400 (EDT) From: Samuel Holland To: Lad Prabhakar , Prabhakar , Marc Zyngier , Sagar Kadam , Paul Walmsley , Palmer Dabbelt Cc: linux-renesas-soc@vger.kernel.org, Guo Ren , Geert Uytterhoeven , Thomas Gleixner , Biju Das , Samuel Holland , Albert Ou , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 3/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Date: Mon, 27 Jun 2022 00:12:57 -0500 Message-Id: <20220627051257.38543-4-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220627051257.38543-1-samuel@sholland.org> References: <20220627051257.38543-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The T-HEAD PLIC ignores additional edges seen while an edge-triggered interrupt is being handled. Because of this behavior, the driver needs to complete edge-triggered interrupts in the .irq_ack callback before handling them, instead of in the .irq_eoi callback afterward. Otherwise, it could miss some interrupts. Co-developed-by: Lad Prabhakar Signed-off-by: Lad Prabhakar Signed-off-by: Samuel Holland --- Changes in v1: - Use a flag for enabling the changes instead of a variant ID - Use handle_edge_irq instead of handle_fasteoi_ack_irq - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL drivers/irqchip/irq-sifive-plic.c | 76 +++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 90515865af08..462a93b4b088 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -69,6 +69,7 @@ struct plic_priv { struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; + bool needs_edge_handling; }; struct plic_handler { @@ -86,6 +87,9 @@ static int plic_parent_irq __ro_after_init; static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); +static struct irq_chip plic_edge_chip; +static struct irq_chip plic_chip; + static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) { u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); @@ -181,6 +185,40 @@ static void plic_irq_eoi(struct irq_data *d) } } +static int plic_irq_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct plic_priv *priv = irq_data_get_irq_chip_data(d); + + if (!priv->needs_edge_handling) + return IRQ_SET_MASK_OK_NOCOPY; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + irq_set_chip_handler_name_locked(d, &plic_edge_chip, + handle_edge_irq, NULL); + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_set_chip_handler_name_locked(d, &plic_chip, + handle_fasteoi_irq, NULL); + break; + default: + return -EINVAL; + } + + return IRQ_SET_MASK_OK; +} + +static struct irq_chip plic_edge_chip = { + .name = "PLIC", + .irq_ack = plic_irq_eoi, + .irq_mask = plic_irq_mask, + .irq_unmask = plic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = plic_set_affinity, +#endif + .irq_set_type = plic_irq_set_type, +}; + static struct irq_chip plic_chip = { .name = "PLIC", .irq_mask = plic_irq_mask, @@ -189,8 +227,22 @@ static struct irq_chip plic_chip = { #ifdef CONFIG_SMP .irq_set_affinity = plic_set_affinity, #endif + .irq_set_type = plic_irq_set_type, }; +static int plic_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct plic_priv *priv = d->host_data; + + if (priv->needs_edge_handling) + return irq_domain_translate_twocell(d, fwspec, hwirq, type); + else + return irq_domain_translate_onecell(d, fwspec, hwirq, type); +} + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { @@ -211,7 +263,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int type; struct irq_fwspec *fwspec = arg; - ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); if (ret) return ret; @@ -225,7 +277,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, } static const struct irq_domain_ops plic_irqdomain_ops = { - .translate = irq_domain_translate_onecell, + .translate = plic_irq_domain_translate, .alloc = plic_irq_domain_alloc, .free = irq_domain_free_irqs_top, }; @@ -286,8 +338,9 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } -static int __init plic_init(struct device_node *node, - struct device_node *parent) +static int __init __plic_init(struct device_node *node, + struct device_node *parent, + bool needs_edge_handling) { int error = 0, nr_contexts, nr_handlers = 0, i; u32 nr_irqs; @@ -298,6 +351,8 @@ static int __init plic_init(struct device_node *node, if (!priv) return -ENOMEM; + priv->needs_edge_handling = needs_edge_handling; + priv->regs = of_iomap(node, 0); if (WARN_ON(!priv->regs)) { error = -EIO; @@ -415,6 +470,17 @@ static int __init plic_init(struct device_node *node, return error; } +static int __init plic_init(struct device_node *node, + struct device_node *parent) +{ + return __plic_init(node, parent, false); +} IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */ + +static int __init plic_edge_init(struct device_node *node, + struct device_node *parent) +{ + return __plic_init(node, parent, true); +} +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);