From patchwork Mon Jun 27 11:21:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 12896530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7838DCCA47F for ; Mon, 27 Jun 2022 11:35:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gvVfiFEDebwAupZTmoSg/Bg07fia62gK8q3lE47Jetc=; b=xWVIoz7uDkxbci p8Uhzdw6SuiwSagOdkCfEkmfWqD0b3FGDiaNKsq8/pFUkk7C5PI8l8Hy+jFkLWU0R4y9YUa+332je i5QdePdV1/QB4vQgieDdcyy58XgZN+9cNHABxeKSB4hDuc2f9KCbXFPJqyftN94Y+3Fz2xJ6JdbBC sDA7TqrYt57TDrB5JawRCIxrh/JjheWWnyk02uai6DztDwVRCZvXcsnJRsJ0cS8p+kW9rxq+p16LA rHvY3R8vjZ8p9X25/ROPNFiSjjJadn/Cc67r0HN/r462+cgTKD3LfYoUQ4VTG/SkqAvod9Xeh1mwx tHRnGIQg45UiBKow/PIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5n0A-000Xk7-1S; Mon, 27 Jun 2022 11:33:59 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5mzz-000Xep-Kc for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2022 11:33:52 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id F0782B81123; Mon, 27 Jun 2022 11:33:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 197D1C3411D; Mon, 27 Jun 2022 11:33:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1656329624; bh=EKjiFdz5wKXQSYJz52RrgGycxoztEmSVeHuuY5EtJzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DGkl2t6eoFumfYSfN6v38jM55JWdzzR5gTV5+rEYeUUFsy58cK+QKWTfiEU6vY8FK 5VzbBqHuvvnngdW4OZqxA0qWVuDrBq7aCG3h3XjShmeRXIE18hIUtSeSVqwXrNAuY5 /EBvEqH8+MQUhAZnUElP/04ltQsjVSuSvdsMbMj0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ali Saidi , German Gomez , Leo Yan , Alexander Shishkin , Andrew Kilroy , Benjamin Herrenschmidt , James Clark , Jiri Olsa , John Garry , Kajol Jain , Li Huafei , linux-arm-kernel@lists.infradead.org, Mark Rutland , Mathieu Poirier , Namhyung Kim , Nick Forrington , Peter Zijlstra , Will Deacon , Arnaldo Carvalho de Melo , Sasha Levin Subject: [PATCH 5.15 060/135] perf arm-spe: Dont set data source if its not a memory operation Date: Mon, 27 Jun 2022 13:21:07 +0200 Message-Id: <20220627111939.899189916@linuxfoundation.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220627111938.151743692@linuxfoundation.org> References: <20220627111938.151743692@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_043348_103776_3FB2A50E X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Leo Yan [ Upstream commit 51ba539f5bdb5a8cc7b1dedd5e73ac54564a7602 ] Except for memory load and store operations, ARM SPE records also can support other operation types, bug when set the data source field the current code assumes a record is a either load operation or store operation, this leads to wrongly synthesize memory samples. This patch strictly checks the record operation type, it only sets data source only for the operation types ARM_SPE_LD and ARM_SPE_ST, otherwise, returns zero for data source. Therefore, we can synthesize memory samples only when data source is a non-zero value, the function arm_spe__is_memory_event() is useless and removed. Fixes: e55ed3423c1bb29f ("perf arm-spe: Synthesize memory event") Reviewed-by: Ali Saidi Reviewed-by: German Gomez Signed-off-by: Leo Yan Tested-by: Ali Saidi Cc: Alexander Shishkin Cc: alisaidi@amazon.com Cc: Andrew Kilroy Cc: Benjamin Herrenschmidt Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Leo Yan Cc: Li Huafei Cc: linux-arm-kernel@lists.infradead.org Cc: Mark Rutland Cc: Mathieu Poirier Cc: Namhyung Kim Cc: Nick Forrington Cc: Peter Zijlstra Cc: Will Deacon Link: http://lore.kernel.org/lkml/20220517020326.18580-5-alisaidi@amazon.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/arm-spe.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 235549bb28b9..569e1b8ad0ab 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -312,26 +312,16 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -#define SPE_MEM_TYPE (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \ - ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \ - ARM_SPE_REMOTE_ACCESS) - -static bool arm_spe__is_memory_event(enum arm_spe_sample_type type) -{ - if (type & SPE_MEM_TYPE) - return true; - - return false; -} - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) { union perf_mem_data_src data_src = { 0 }; if (record->op == ARM_SPE_LD) data_src.mem_op = PERF_MEM_OP_LOAD; - else + else if (record->op == ARM_SPE_ST) data_src.mem_op = PERF_MEM_OP_STORE; + else + return 0; if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { data_src.mem_lvl = PERF_MEM_LVL_L3; @@ -435,7 +425,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq) return err; } - if (spe->sample_memory && arm_spe__is_memory_event(record->type)) { + /* + * When data_src is zero it means the record is not a memory operation, + * skip to synthesize memory sample for this case. + */ + if (spe->sample_memory && data_src) { err = arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err;