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Tue, 28 Jun 2022 13:44:33 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epcas2p2116480d15be87cb723855b7a39ced6dc~8r0S80Et20047300473epcas2p2O; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220628044432epsmtrp17233c4708f4314e1d46d75949becec61~8r0S4CmhY2149721497epsmtrp16; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) X-AuditID: b6c32a45-45bff700000025c2-88-62ba87315f55 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id E4.70.08905.0378AB26; Tue, 28 Jun 2022 13:44:32 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epsmtip17aed2d3d4ebf3a8d035ebbb4d93f689f~8r0Sp_eIV2861828618epsmtip1i; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v2 1/4] spi: s3c64xx: support loopback mode Date: Tue, 28 Jun 2022 13:42:19 +0900 Message-Id: <20220628044222.152794-2-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628044222.152794-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKJsWRmVeSWpSXmKPExsWy7bCmha5h+64kg78fuCwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pm YKhraGlhrqSQl5ibaqvk4hOg65aZA3SdkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUg JafAvECvODG3uDQvXS8vtcTK0MDAyBSoMCE748nfl2wFC4Qqvl+/w9jA2MnfxcjJISFgIvHz 1gT2LkYuDiGBHYwSHyb/YIVwPjFK7L/zihHC+cYocfH1ciaYli9/JrNAJPYyStyadJkZwvnI KDH7yT+wKjYBXYktzyHaRQRuMkpMP9vHBOIwC9xglNg7Yz0jSJWwgLXEu7+v2UBsFgFViaa2 dcwgNq+AvcSfta0sEPvkJTbM7wWLcwo4SCy4vZ0RokZQ4uTMJ2A1zEA1zVtng50hITCRQ+L4 nlnsEM0uEl+e32GGsIUlXh3fAhWXknjZ3wZlF0ssnfWJCaK5gVHi8rZfbBAJY4lZz9qBtnEA bdCUWL9LH8SUEFCWOHILai+fRMfhv+wQYV6JjjYhiEZ1iQPbp0OdLyvRPeczK4TtIdH28Dg4 gIQEJjNKvLtpNYFRYRaSb2Yh+WYWwt4FjMyrGMVSC4pz01OLjQoM4XGcnJ+7iRGcXrVcdzBO fvtB7xAjEwfjIUYJDmYlEd6FZ3YmCfGmJFZWpRblxxeV5qQWH2I0BYb1RGYp0eR8YILPK4k3 NLE0MDEzMzQ3MjUwVxLn9UrZkCgkkJ5YkpqdmlqQWgTTx8TBKdXANNPAQTLcZj1HYorLvp8d l63Yny1nDvItapC5Xt226HVTWHZZr1u7iLxT7+wHfq4pL18+nDr7euHddMOqfRdfuV+a5/hg 3rWm7183cl99EPlsxc2v5WfaBEUjUtjX/gpjPTQvbfnJZ+vZ/7LrrXjoH3XqzZ43Zg8sja6b zbpm3J6143207Bnl/MKrsdanzizlkj3au8BprSJ74BKBwzUsGuqeB5lOPOuNm7fhsM/jWk3v E1MKl4cvunWkpYKZbdOXQ8KebFKSBpu51UpfXDZ7e/azaJbulG3y9hVukl6r7/v7bNWRDgrr nKBRIPUzoDKG4YD6oZufynq8LqoKVb3TK15zoOfTxKW5PvVzH+2br8RSnJFoqMVcVJwIABMt uRA4BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWy7bCSnK5B+64kg6ftihYP5m1js1j84zmT xdSHT9gsLu/Xtph/5ByrRd+Lh8wWe19vZbfY9Pgaq8WM8/uYLBo/3mS3aN17hN2B2+P6kk/M HptWdbJ53Lm2h81j85J6j74tqxg9Pm+SC2CL4rJJSc3JLEst0rdL4Mp48vclW8ECoYrv1+8w NjB28ncxcnJICJhIfPkzmaWLkYtDSGA3o8Tmhv/MEAlZiWfvdrBD2MIS91uOsILYQgLvGSWO XxIFsdkEdCW2PH/FCNIsInCbUeJv4zY2EIdZ4A6jxKPle5hAqoQFrCXe/X3NBmKzCKhKNLWt A9vAK2Av8WdtKwvEBnmJDfN7weKcAg4SC25vZ4TYZi+xfudaVoh6QYmTM5+A1TMD1Tdvnc08 gVFgFpLULCSpBYxMqxglUwuKc9Nziw0LDPNSy/WKE3OLS/PS9ZLzczcxguNAS3MH4/ZVH/QO MTJxMB5ilOBgVhLhXXhmZ5IQb0piZVVqUX58UWlOavEhRmkOFiVx3gtdJ+OFBNITS1KzU1ML UotgskwcnFINTHF2zbPz3mzzzWL5fyf905mAm65s0ouvTPqn96L+vnkl4wfW1Ufn+S9yaLRP 97Cd379n5k4+dZsDKqbLmTklnyQd23jfsf7129X3cw4lx3n7mP3MeTv3y6v8My8Yyx9IhGk8 dp082Urz9G2FE6unOO8QeNv8QYBTZZnMNJHfCV8vvmjWKzt3L2v5c8nVLw7cMmbqWr/ic+rp Iv4JmxpC7k0LdU6YNknoEcsZwZVTf/spZW2b17zfsXuFZtwZYYb6JTynHV4fWVkV7JicKhay JrO+/dz3ru2K6S4ap2yyci59sAgz3VllLx4rd8yE4WFcgVk2w++Fz95KHTdPiez3/Lns37X3 MxrtHm/82H9aca4SS3FGoqEWc1FxIgB5xk3C8gIAAA== X-CMS-MailID: 20220628044432epcas2p2116480d15be87cb723855b7a39ced6dc X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220628044432epcas2p2116480d15be87cb723855b7a39ced6dc References: <20220628044222.152794-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_214444_417971_AEE63EA2 X-CRM114-Status: GOOD ( 20.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Modern exynos SoCs can support self loopback mode via setting BIT(3) of MODE_CFG register. Previous SoCs don't have the bit so we need to add has_loopback field in the s3c64xx_spi_port_config. Exynos Auto v9 SoC has the bit and it will define the field to "true". When it is set, SPI_LOOP mode will be marked. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanho Park Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7f0faf0d75d9..b3c50c7665fc 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -59,6 +59,7 @@ #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) #define S3C64XX_SPI_MODE_4BURST (1<<0) @@ -135,6 +136,7 @@ struct s3c64xx_spi_dma_data { * @clk_from_cmu: True, if the controller does not include a clock mux and * prescaler unit. * @clk_ioclk: True if clock is present on this device + * @has_loopback: True if loopback mode can be supported * * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but * differ in some aspects such as the size of the fifo and spi bus clock @@ -149,6 +151,7 @@ struct s3c64xx_spi_port_config { bool high_speed; bool clk_from_cmu; bool clk_ioclk; + bool has_loopback; }; /** @@ -659,6 +662,9 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) break; } + if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) + val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; + writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { @@ -1148,6 +1154,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) SPI_BPW_MASK(8); /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + if (sdd->port_conf->has_loopback) + master->mode_bits |= SPI_LOOP; master->auto_runtime_pm = true; if (!is_polling(sdd)) master->can_dma = s3c64xx_spi_can_dma; From patchwork Tue Jun 28 04:42:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 12897639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC474C433EF for ; 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Tue, 28 Jun 2022 13:44:32 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epsmtip1f70fcd8482e010ed119cdb03a9eef5af~8r0SvnclO2875028750epsmtip1d; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Date: Tue, 28 Jun 2022 13:42:20 +0900 Message-Id: <20220628044222.152794-3-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628044222.152794-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKJsWRmVeSWpSXmKPExsWy7bCmha5h+64kgw1zeSwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pm YKhraGlhrqSQl5ibaqvk4hOg65aZA3SdkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUg JafAvECvODG3uDQvXS8vtcTK0MDAyBSoMCE7Y8mzDpaCRToVj551szYwrlHuYuTkkBAwkWjY uouxi5GLQ0hgB6PE1ds7mSCcT4wSt06sYYNwvjFKXLuxiRmm5cL5p8wQib2MEu++LYZq+cgo Mf9eIyNIFZuArsSW56/ABosI3GSUmH62D6yKWeAGo8TeGeuBMhwcwgJhEpNfuII0sAioSqzo +skOYvMK2EscutIKtU5eYsP8XjCbU8BBYsHt7YwQNYISJ2c+YQGxmYFqmrfOBjtJQqCXQ2LO +f1QzS4Sffd6WCFsYYlXx7ewQ9hSEp/f7WWDsIslls76xATR3MAocXnbL6iEscSsZ+1ghzIL aEqs36UPYkoIKEscuQW1l0+i4/Bfdogwr0RHmxBEo7rEge3TWSBsWYnuOZ+hLvCQmHJ8Bwsk sCYzSvSvm8k8gVFhFpJ3ZiF5ZxbC4gWMzKsYxVILinPTU4uNCgzhcZycn7uJEZxetVx3ME5+ +0HvECMTB+MhRgkOZiUR3oVndiYJ8aYkVlalFuXHF5XmpBYfYjQFBvZEZinR5Hxggs8riTc0 sTQwMTMzNDcyNTBXEuf1StmQKCSQnliSmp2aWpBaBNPHxMEp1cBkyiZ83e/wNMVVE5x8zvVW m34y6FVVXnmy9a1bYYpya6v2/RnB4lPL5pXsqLb60b7xQbvYvalTTx+dG+b2cPJZt1udx9tX qfEX8e+puPvJ3md+6NTrSn7Zc501Tk3pNNW8sse799JJfsd/z7WmtC+yFPGQkY6/n+Czoc1o VemTh3VrLsz8Mj9vkWT0o1cyxq/cUwt3fl0b5Z68u3jLug7OBRf5GVkeccnInri3fIfGlp0s F+ep1h/xrrvzqWC3WJKjhI5Jqvk8WwsR33865UXrTgeY3y1m9/vBI5Y664q3mCDb94d+YkJe Jc7bGV70fGgumf/bf/2WBJfv2V+XLn00szk9PfXP+xcHHDcqzDqvxFKckWioxVxUnAgALoR2 7jgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSnK5B+64kgyvf1CwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWxWWTkpqTWZZapG+XwJWx5FkHS8EinYpHz7pZ GxjXKHcxcnJICJhIXDj/lLmLkYtDSGA3o8S671NZIRKyEs/e7WCHsIUl7rccYYUoes8osWvF C7AEm4CuxJbnrxhBEiICtxkl/jZuYwNxmAXuMEo8Wr6HCaRKWCBEYvXsCSwgNouAqsSKrp9g 3bwC9hKHrrQyQ6yQl9gwvxfM5hRwkFhwezsjiC0EVLN+51pWiHpBiZMzn4DNYQaqb946m3kC o8AsJKlZSFILGJlWMUqmFhTnpucWGxYY5qWW6xUn5haX5qXrJefnbmIER4KW5g7G7as+6B1i ZOJgPMQowcGsJMK78MzOJCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8F7pOxgsJpCeWpGanphak FsFkmTg4pRqYzneU+2evntRgX+N87Cxn1oJIvb2JewXf/Pra7jJV7sI/C+3VAb558rFHDdyW 7nwmEuYvYdK/gFdzunRcROcpC5fJwa9WL1DblTed8TJ70CKWY+79JQLrjP9++HguVHanrvaS 1SrrlE/6avnx+U5n9c/2eeKT8S/h8MzT4nOfbZoe4GE1z2tnoYjS8f9P+HM9XOvOvPvlEx5f uF01VUl5xm4xG5P3O/evnJjwkv170uJT7+8kRoWdbb0wfdqklIQz2227PlWdbS0vDn4dtmib kWFIr0Tt97M71tiq+23fs2dR6H5Hrzelj77tlnPjlHM54PmHW27ys4P3Z2YarNo0keet1zL+ a5unCpq6q1xYrMRSnJFoqMVcVJwIAHbzTMzzAgAA X-CMS-MailID: 20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28 References: <20220628044222.152794-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_214446_530056_1FBE34FB X-CRM114-Status: GOOD ( 21.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Modern exynos SoCs such as Exynos Auto v9 has different internal clock divider, for example "4". To support this internal value, this adds clk_div of the s3c64xx_spi_port_config and assign "2" as the default value to existing s3c64xx_spi_port_config. Signed-off-by: Chanho Park --- drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b3c50c7665fc..51a0e830441b 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. + * @clk_div: Internal clock divider, if not specified, use 2 as the default. * @quirks: Bitmask of known quirks * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. * @clk_from_cmu: True, if the controller does not include a clock mux and @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config { int rx_lvl_offset; int tx_st_done; int quirks; + int clk_div; bool high_speed; bool clk_from_cmu; bool clk_ioclk; @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) void __iomem *regs = sdd->regs; int ret; u32 val; + u32 div = sdd->port_conf->clk_div; /* Disable Clock */ if (!sdd->port_conf->clk_from_cmu) { @@ -668,16 +671,15 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* The src_clk clock is divided internally by 2 */ - ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); + ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); if (ret) return ret; - sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); val &= ~S3C64XX_SPI_PSR_MASK; - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) & S3C64XX_SPI_PSR_MASK); writel(val, regs + S3C64XX_SPI_CLK_CFG); @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_csinfo *cs = spi->controller_data; struct s3c64xx_spi_driver_data *sdd; int err; + u32 div = 2; sdd = spi_master_get_devdata(spi->master); if (spi->dev.of_node) { @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) pm_runtime_get_sync(&sdd->pdev->dev); + div = sdd->port_conf->clk_div; + /* Check if we can provide the requested rate */ if (!sdd->port_conf->clk_from_cmu) { u32 psr, speed; /* Max possible */ - speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); + speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); if (spi->max_speed_hz > speed) spi->max_speed_hz = speed; - psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; + psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; psr &= S3C64XX_SPI_PSR_MASK; if (psr == S3C64XX_SPI_PSR_MASK) psr--; - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz < speed) { if (psr+1 < S3C64XX_SPI_PSR_MASK) { psr++; @@ -914,7 +919,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } } - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz >= speed) { spi->max_speed_hz = speed; } else { @@ -1396,6 +1401,7 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { .fifo_lvl_mask = { 0x7f }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, .high_speed = true, }; @@ -1403,12 +1409,14 @@ static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7F }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, }; @@ -1416,6 +1424,7 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1425,6 +1434,7 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1434,6 +1444,7 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = true, @@ -1444,6 +1455,7 @@ static struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = false, From patchwork Tue Jun 28 04:42:21 2022 Content-Type: text/plain; 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Tue, 28 Jun 2022 04:44:32 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220628044432epsmtrp1eed3b2aefe2c2d2f867134caf623435e~8r0TB6cwg2149721497epsmtrp17; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) X-AuditID: b6c32a46-0a3ff700000025b2-ab-62ba8731902c Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 66.70.08905.0378AB26; Tue, 28 Jun 2022 13:44:32 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epsmtip1579e51ade53adfd5cfd996c440a255c8~8r0S1G5bG2861828618epsmtip1j; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v2 3/4] dt-bindings: samsung,spi: define exynosautov9 compatible Date: Tue, 28 Jun 2022 13:42:21 +0900 Message-Id: <20220628044222.152794-4-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628044222.152794-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGJsWRmVeSWpSXmKPExsWy7bCmha5h+64kg0vveSwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pm YKhraGlhrqSQl5ibaqvk4hOg65aZA3SdkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUg JafAvECvODG3uDQvXS8vtcTK0MDAyBSoMCE7Y8rOJraCNZwV85q2MjUwtrN3MXJySAiYSEx6 cQfI5uIQEtjBKPH45hImCOcTo8SNO++hMt8YJX6sus0C07LxehcbRGIvo8SOk2uhnI+MEte2 n2UEqWIT0JXY8vwVI0hCROAmo8T0s31gg5kFbjBK7J2xHqxKWCBIYtaN92A2i4CqxI1td9hA bF4Be4nrj1ZB7ZOX2DC/lxnE5hRwkFhwezsjRI2gxMmZT8BqmIFqmrfOZgZZICHQyyFx59tF qGYXiUsbljBC2MISr45vgfpbSuJlfxuUXSyxdNYnJojmBkaJy9t+sUEkjCVmPWsHauYA2qAp sX6XPogpIaAsceQW1F4+iY7Df9khwrwSHW1CEI3qEge2T4e6QFaie85nVgjbQ2JOx0IWSGhN ZpSYMq+dZQKjwiwk78xC8s4shMULGJlXMYqlFhTnpqcWGxUYwSM5OT93EyM4wWq57WCc8vaD 3iFGJg7GQ4wSHMxKIrwLz+xMEuJNSaysSi3Kjy8qzUktPsRoCgzsicxSosn5wBSfVxJvaGJp YGJmZmhuZGpgriTO65WyIVFIID2xJDU7NbUgtQimj4mDU6qB6cycfedz8pexze06bGIXUTD5 1svbcwM/yqY7WadpPOY+tsb2e1vF9kUzfXSnts4JiT9k8uHXIbWp6yLDP12Nn6nSbrTiFbdH 7rKNYmHLM+SPBPitUgpl80kOYWG4y5526PVpEcUu73OTXx6+5+doc3xDT84c2Zzi7b2ycYkt sVZf903I+vhtiqW1aPlm36D5tydd81wt772IZcOzb+oM4rlbmF9kxPTVL20JcdrGu+dh4cW8 w3tkDRkcj/22cWq6/yvgs7BYjVp4i6xNxkWhObx3439l838/O18k3MfkrN9yqQkrORLnLfDS E5k0j6Xni7NI8ZcV3Sm9DjzOLrxXrkyPPD8zcG55mYr7JAMtJZbijERDLeai4kQA+g8iizkE AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWy7bCSnK5B+64kg7079CwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWxWWTkpqTWZZapG+XwJUxZWcTW8Eazop5TVuZ Ghjb2bsYOTkkBEwkNl7vYuti5OIQEtjNKLGppYERIiEr8ezdDqgiYYn7LUdYQWwhgfeMEk82 iYLYbAK6Eluev2IEaRYRuM0o8bdxG9gkZoE7jBKPlu9h6mLk4BAWCJB438sM0sAioCpxY9sd NhCbV8Be4vqjVSwQC+QlNsyHqOEUcJBYcHs7I8Qye4n1O9eyQtQLSpyc+QSsnhmovnnrbOYJ jAKzkKRmIUktYGRaxSiZWlCcm55bbFhgmJdarlecmFtcmpeul5yfu4kRHAVamjsYt6/6oHeI kYmD8RCjBAezkgjvwjM7k4R4UxIrq1KL8uOLSnNSiw8xSnOwKInzXug6GS8kkJ5YkpqdmlqQ WgSTZeLglGpg8g2+WXhSLP9Zhb20nDD//06Lk/P65/6fLvzq2+nyGSLsXgZ+xRMOvln//E+J b9BUrk1dB6wlfB3eGJ7U3qYT8kaw8fzJN6Knll/xic2c+ENJc+/WhWk5Ngnh3gtq+7c/bGKb dGmK9q7M3L0+V8wkSxfI3j717/vL9Cxv4bMfI264p/Ee3Dlt95fZysU+74/O7jy+T8yjJe9l 3ac5d3LfGzC+M+LPPriuY/M7finO4LZzmndkQzj3FzlP4GZNS2APnbtOxyzoOo+Kc+K005un zNRace5ak9HqxtqJT2d4Pspk+Csa2vX4Y8a5ZRtC3+c49jk+mceYu9r31rllH+boqhbYKN2s nLnr792g/R17xJRYijMSDbWYi4oTAZTy4F7xAgAA X-CMS-MailID: 20220628044432epcas2p3781648b3cade1dcac6b8e0f3899d7299 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220628044432epcas2p3781648b3cade1dcac6b8e0f3899d7299 References: <20220628044222.152794-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_214446_491463_FD9846E7 X-CRM114-Status: GOOD ( 15.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Define "samsung,exynosautov9-spi" for Exynos Auto v9's spi. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanho Park Reviewed-by: Andi Shyti --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index a50f24f9359d..d51ee3e6d604 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -21,6 +21,7 @@ properties: - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos5433-spi + - samsung,exynosautov9-spi - tesla,fsd-spi - const: samsung,exynos7-spi deprecated: true @@ -85,7 +86,9 @@ allOf: properties: compatible: contains: - const: samsung,exynos5433-spi + enum: + - samsung,exynos5433-spi + - samsung,exynosautov9-spi then: properties: clocks: From patchwork Tue Jun 28 04:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 12897637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D3D8C43334 for ; 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Tue, 28 Jun 2022 13:44:32 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epsmtip18800ee082a259ae04efbd064ce9e58d9~8r0S8wBq_2875128751epsmtip1a; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v2 4/4] spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC Date: Tue, 28 Jun 2022 13:42:22 +0900 Message-Id: <20220628044222.152794-5-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628044222.152794-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCJsWRmVeSWpSXmKPExsWy7bCmha5h+64kgytzRSwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pm YKhraGlhrqSQl5ibaqvk4hOg65aZA3SdkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUg JafAvECvODG3uDQvXS8vtcTK0MDAyBSoMCE74+zNDvaCh3wVP+6eYGpgnMLTxcjJISFgIrGj +RpLFyMXh5DADkaJnS8usEI4nxglThxdwwpSJSTwjVHi0vxkmI69J98xQRTtZZTYPq8dquMj o8TVEwvYQKrYBHQltjx/xQiSEBG4ySgx/WwfWAuzwA1Gib0z1jOCVAkLREq0fbrCAmKzCKhK LO9dD9bNK2AvcfHuMRaIffISG+b3MoPYnAIOEgtub2eEqBGUODnzCVgNM1BN89bZzCALJAQm ckhcbp/IBNHsInHk8ypmCFtY4tXxLewQtpTEy/42KLtYYumsT0wQzQ2MEpe3/WKDSBhLzHrW DrSNA2iDpsT6XfogpoSAssSRW1B7+SQ6Dv9lhwjzSnS0CUE0qksc2D4d6nxZie45n1khbA+J xq4PTJAgncwo8W5rzARGhVlIvpmF5JtZCHsXMDKvYhRLLSjOTU8tNiowhEdxcn7uJkZwctVy 3cE4+e0HvUOMTByMhxglOJiVRHgXntmZJMSbklhZlVqUH19UmpNafIjRFBjWE5mlRJPzgek9 ryTe0MTSwMTMzNDcyNTAXEmc1ytlQ6KQQHpiSWp2ampBahFMHxMHp1QD096VksXfLorfTDoT Ur2Xp8z7dpbKF5mv/lqcV5XLf5W9n/fwtq6yUCrfPa/48kOm04sffXU81btt7m3JZ37JwZMY I3RWa24ISVpTrit2UHmV3NG0R88slrmz91ecdb+jfKr3pMiH+AyJtxeu3jDuFp7z8GYji42l qtHS6qP6O5aVXjuR3G7K8mDlq8lX+Srm/9ZVDJ76z8P2Z968FVOdCo8WL3ifJP9Ea9vfC2mP rFOFN68JzhTbPa3izJtLL9IeqWSEnZjQ2NndVxCduWt+YMnsLU6/DvvMNjG+818hrf/stLbK afKzF9U8OJ+aLVO4brt5pfXZyMQui58bPR3VLnHduvzvAKfvuWdpVsnFNkosxRmJhlrMRcWJ AIal9Nk3BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSnK5B+64kgwUrTCwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWxWWTkpqTWZZapG+XwJVx9mYHe8FDvoofd08w NTBO4eli5OSQEDCR2HvyHVMXIxeHkMBuRonfV76xQyRkJZ692wFlC0vcbznCClH0nlHi3eEm VpAEm4CuxJbnrxhBEiICtxkl/jZuYwNxmAXuMEo8Wr6HCaRKWCBcYtajhWCjWARUJZb3rmcD sXkF7CUu3j3GArFCXmLD/F5mEJtTwEFiwe3tjCC2EFDN+p1rWSHqBSVOznwCVs8MVN+8dTbz BEaBWUhSs5CkFjAyrWKUTC0ozk3PLTYsMMxLLdcrTswtLs1L10vOz93ECI4ELc0djNtXfdA7 xMjEwXiIUYKDWUmEd+GZnUlCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeS90nYwXEkhPLEnNTk0t SC2CyTJxcEo1MF14bvR0f630Vf0z63b6/P6dlFu1+5vikm3HjgfemP/qpkHU+43tO5dlM+ke ay64dmzbzDlPaq2V/2x6eD04+X3C0yWfNRxP3XB/5fH26PU4weVPCnp2qSoLNXldV//J9mPS rontQUIxoSuP9X0Uf7Htg5/o/cmLv+SbaTj2M/7YwXk/tUmLvVj24Efp2Yl12YbSV583eYgU fNhYdOTdL7e1Jmsn786bot6WndV2o/9j69SeWcsjPCT4mC8fvP9pUmWgFcNal9cHfd+o2juz 5Bjee3hn1x8BlaIFU6NqX9kXezvezDh6cgXbE+k9Z1hua1neb3eu++B89ltuxfWG2hd6VzYt Fmqs6gueorQ+/OskJZbijERDLeai4kQARnCwRfMCAAA= X-CMS-MailID: 20220628044432epcas2p2e2b4c0d52f11c0bf543c537e819224bc X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220628044432epcas2p2e2b4c0d52f11c0bf543c537e819224bc References: <20220628044222.152794-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_214446_535100_0FFF3AD4 X-CRM114-Status: GOOD ( 17.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add exynosautov9 spi port configuration. It supports up to 12 spis so MAX_SPI_PORTS should be increased from 6 to 12. It has DIV_4 as the default internal clock divider and an internal loopback mode to run a loopback test. Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 51a0e830441b..0c9e19889809 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -18,7 +18,7 @@ #include -#define MAX_SPI_PORTS 6 +#define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -1451,6 +1451,19 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .clk_ioclk = true, + .has_loopback = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset = 15, @@ -1492,6 +1505,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos5433-spi", .data = (void *)&exynos5433_spi_port_config, }, + { .compatible = "samsung,exynosautov9-spi", + .data = (void *)&exynosautov9_spi_port_config, + }, { .compatible = "tesla,fsd-spi", .data = (void *)&fsd_spi_port_config, },