From patchwork Tue Jun 28 08:17:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12897883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65A5BC433EF for ; Tue, 28 Jun 2022 08:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+/pxjovqJMuR5ljCTVnLUvKwST7AQPGYfU4RwdpoCO8=; b=VzT6q0qV+kW9Ko 1UkU7Nx9H3CQ0PbgcbgbbS+0B0os5f+H8wpsL/uO2zyN1yCdEGYY4RFXczEOHHMtFzoPl9qpo2D/z mr/jgMxclYDlhUDNnbfXw/+JsJlempUAlSkDtCTKrBtu3wa7WQppAM6QBL3XNtgG6anncE7krT+aB 5Skmif0b+s7FiWfSjqbL3oa4h9rksMG0xnMPjABjEbnYQjXeKE+h5ORSWS8Jo4aXIqqTJIxDqFLuE IKD3wMF+GwKfjXfb9Knva26KkMtC/L4MD7UXrxgihmngsbyDwXpSQ/n3DRP5z1yWhUGOKDbaJhN9B RRrvqtpaGYzomZGlf53A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66Pa-005Bcy-2c; Tue, 28 Jun 2022 08:17:30 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66PW-005BbR-SK for linux-riscv@lists.infradead.org; Tue, 28 Jun 2022 08:17:28 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1A8856119B; Tue, 28 Jun 2022 08:17:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 532B8C341CB; Tue, 28 Jun 2022 08:17:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404245; bh=wuMCLxNzxYSmxOh5v/SBPcUTtvTDqjGgAdULUenQIXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pPb+/fENqMFaNUkZi6ql3d0fdSuDA7WTP/Lpo5BBmMl376GJTJ5wk6oq5bjBKJujt AUAkSyTrMojK8B6lta+rMW/hVbpHJ4EbCDBZ3s1u2HDX6r9aytN5JiiJVFIfKbSUVJ MDsa4DdyVpOAxrwZre4pbBxEtJENcdfdbbsl9zJETI27O4EeiRcHd5ox2nguiOMi57 7swCaCeIbQK/SbiHBmRrq/8mj7XWoj0oMDQfLt/ldfv4beWX37ef27Zq27Hh9ugOtg 9n1Ut6VjS0R+FmzLF8AhoEfAsSOtt/Dcz0LJCEAhgal1ah9yWzcfIo1IDAIzhgeCFi KH3mqQj9ea+aw== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 1/5] asm-generic: ticket-lock: Remove unnecessary atomic_read Date: Tue, 28 Jun 2022 04:17:03 -0400 Message-Id: <20220628081707.1997728-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011726_990683_325975B1 X-CRM114-Status: GOOD ( 11.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Remove unnecessary atomic_read in arch_spin_value_unlocked(lock), because the value has been in lock. This patch could prevent arch_spin_value_unlocked contend spin_lock data again. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Arnd Bergmann Cc: Palmer Dabbelt --- include/asm-generic/spinlock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h index fdfebcb050f4..f1e4fa100f5a 100644 --- a/include/asm-generic/spinlock.h +++ b/include/asm-generic/spinlock.h @@ -84,7 +84,9 @@ static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock) static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { - return !arch_spin_is_locked(&lock); + u32 val = lock.counter; + + return ((val >> 16) == (val & 0xffff)); } #include From patchwork Tue Jun 28 08:17:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12897884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99CFAC433EF for ; Tue, 28 Jun 2022 08:17:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pQCwTuDaAM4gIeo1Uq9TAFrRJ86eh75iXuWQH9q90gI=; b=YA1IqDeFTQAlfO 3cnQ8GKGSrQzLEdau+k3veEaeMzy1XWSLMfl1mmoB5UC+pHKC/ENlhNqFSFs4II+vYEYgzE3lU2JB bt7bdgbxB53eV3x5IMHniOTPFxat98Lkm7lN+R8Jg6evrWj9T9JXWteWPD0H5f68CPCDI+ylJat2K BgejMKwXwuWrL6ohsAOYnOQ4/KTW1WKS+utV+etGPQ3ieheBivMkl3xDvAJbSi8cF1fK/h1iNb28u hKuA+cuPEy57zr7SEAl2iJyxyVWSGQsingZjHv4khqytvGcyDg1b3Lh9tuIuuM6Hz0on9S5xbT2Rz dYLBQxqftZfLNypK9IhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66Pd-005BeW-8A; Tue, 28 Jun 2022 08:17:33 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66PZ-005BcR-Cf for linux-riscv@lists.infradead.org; Tue, 28 Jun 2022 08:17:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0315361212; Tue, 28 Jun 2022 08:17:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD2CFC341CD; Tue, 28 Jun 2022 08:17:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404248; bh=56vDPTinccyutph1yZKj95E6BJocnFoqUhaAVIL62sY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rCEAC2SBigqijBYp6OMMgxbh8KeqZedwJGPUR2YIkNilXQ8x+tBKFTFu/dOWr+kMk Xhq8Ws2xj/0/xP2QqoXjbxKwDb77EYzbKnbsjE/pbPvh40jjLrlkPqHI3MFJGyDlV+ XMfPNr0BF0vT76lkHYN6s+phQ95nHfr10FEf7cerv0ksBEhoWD7FDTS7AHz3DBthiP ijjAVggUMRpy/4a6UEuGWuVts9kikdkNj8NNUKqOTQpqU67h5JIy4futCp8RaZfnDg I3P4SMxDF+Ht0AKrEFoK/9a6MQQLd4tNRNR903q3XUgGoi2gJpTiZqPU/k9LNeL3oM kC1Zu91Wbs/wg== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 2/5] asm-generic: ticket-lock: Use the same struct definitions with qspinlock Date: Tue, 28 Jun 2022 04:17:04 -0400 Message-Id: <20220628081707.1997728-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011729_570774_CB52EBAA X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Let ticket_lock use the same struct definitions with qspinlock, and then we could move to combo spinlock (combine ticket & queue). Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Arnd Bergmann Cc: Palmer Dabbelt --- include/asm-generic/spinlock.h | 16 ++++++++-------- include/asm-generic/spinlock_types.h | 12 ++---------- 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h index f1e4fa100f5a..4caeb8cebe53 100644 --- a/include/asm-generic/spinlock.h +++ b/include/asm-generic/spinlock.h @@ -32,7 +32,7 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock) { - u32 val = atomic_fetch_add(1<<16, lock); + u32 val = atomic_fetch_add(1<<16, &lock->val); u16 ticket = val >> 16; if (ticket == (u16)val) @@ -46,45 +46,45 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock) * have no outstanding writes due to the atomic_fetch_add() the extra * orderings are free. */ - atomic_cond_read_acquire(lock, ticket == (u16)VAL); + atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL); smp_mb(); } static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock) { - u32 old = atomic_read(lock); + u32 old = atomic_read(&lock->val); if ((old >> 16) != (old & 0xffff)) return false; - return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */ + return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */ } static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) { u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); smp_store_release(ptr, (u16)val + 1); } static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock) { - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); return ((val >> 16) != (val & 0xffff)); } static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock) { - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); return (s16)((val >> 16) - (val & 0xffff)) > 1; } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { - u32 val = lock.counter; + u32 val = lock.val.counter; return ((val >> 16) == (val & 0xffff)); } diff --git a/include/asm-generic/spinlock_types.h b/include/asm-generic/spinlock_types.h index 8962bb730945..f534aa5de394 100644 --- a/include/asm-generic/spinlock_types.h +++ b/include/asm-generic/spinlock_types.h @@ -3,15 +3,7 @@ #ifndef __ASM_GENERIC_SPINLOCK_TYPES_H #define __ASM_GENERIC_SPINLOCK_TYPES_H -#include -typedef atomic_t arch_spinlock_t; - -/* - * qrwlock_types depends on arch_spinlock_t, so we must typedef that before the - * include. - */ -#include - -#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0) +#include +#include #endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */ From patchwork Tue Jun 28 08:17:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12897912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE8F0C43334 for ; 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Tue, 28 Jun 2022 08:19:21 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66Pf-005BeP-TO for linux-riscv@lists.infradead.org; Tue, 28 Jun 2022 08:17:41 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 355A4B81D12; Tue, 28 Jun 2022 08:17:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C93ACC341C8; Tue, 28 Jun 2022 08:17:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404251; bh=Ff1W2padqNEGnlp4EIi4Fy64JmW9kRjF1/cl2+7Ky3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n8QiMoK8ZdSz+GxqAv8Z2XDdz1Ng3XR3AuUc8N+3nejjToYoMpavzerYLKhO8OoMs LjNNk4X7I13v1BKjESxet2/Gg2ho8FhU2Fh2zxJtLwIEjfhFQMyZMRaPKJfK69lg6P pzAulekaNRGTxQTJ+/a00jw/OW6phjURGxu+l2VrTtvtiNH5dc+oQ771y2LX+zZAr7 op3A++IRhO7WlkAVnXHU5nt5drQqTVD8hDjolXbzTNdDrofQHVV0T11vi2JPmiDC8D jOZjWYqwFy4rbaDKuu4nW3F06MA/QcLZ6X12SlON47n9Q82BiLOt2y81Fv8HWqpXWl 1WhUg2hhtQgzQ== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 3/5] asm-generic: ticket-lock: Move into ticket_spinlock.h Date: Tue, 28 Jun 2022 04:17:05 -0400 Message-Id: <20220628081707.1997728-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011736_410315_C5EABDA1 X-CRM114-Status: GOOD ( 20.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Move ticket-lock definition into an independent file. It's a preparation patch for the following combo spinlock. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Arnd Bergmann Cc: Palmer Dabbelt --- include/asm-generic/spinlock.h | 44 ++----------- include/asm-generic/ticket_spinlock.h | 92 +++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 37 deletions(-) create mode 100644 include/asm-generic/ticket_spinlock.h diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h index 4caeb8cebe53..f41dc7c2b900 100644 --- a/include/asm-generic/spinlock.h +++ b/include/asm-generic/spinlock.h @@ -27,66 +27,36 @@ #ifndef __ASM_GENERIC_SPINLOCK_H #define __ASM_GENERIC_SPINLOCK_H -#include -#include +#include static __always_inline void arch_spin_lock(arch_spinlock_t *lock) { - u32 val = atomic_fetch_add(1<<16, &lock->val); - u16 ticket = val >> 16; - - if (ticket == (u16)val) - return; - - /* - * atomic_cond_read_acquire() is RCpc, but rather than defining a - * custom cond_read_rcsc() here we just emit a full fence. We only - * need the prior reads before subsequent writes ordering from - * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we - * have no outstanding writes due to the atomic_fetch_add() the extra - * orderings are free. - */ - atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL); - smp_mb(); + ticket_spin_lock(lock); } static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock) { - u32 old = atomic_read(&lock->val); - - if ((old >> 16) != (old & 0xffff)) - return false; - - return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */ + return ticket_spin_trylock(lock); } static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) { - u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - u32 val = atomic_read(&lock->val); - - smp_store_release(ptr, (u16)val + 1); + ticket_spin_unlock(lock); } static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock) { - u32 val = atomic_read(&lock->val); - - return ((val >> 16) != (val & 0xffff)); + return ticket_spin_is_locked(lock); } static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock) { - u32 val = atomic_read(&lock->val); - - return (s16)((val >> 16) - (val & 0xffff)) > 1; + return ticket_spin_is_contended(lock); } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { - u32 val = lock.val.counter; - - return ((val >> 16) == (val & 0xffff)); + return ticket_spin_value_unlocked(lock); } #include diff --git a/include/asm-generic/ticket_spinlock.h b/include/asm-generic/ticket_spinlock.h new file mode 100644 index 000000000000..83e769398eea --- /dev/null +++ b/include/asm-generic/ticket_spinlock.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * 'Generic' ticket-lock implementation. + * + * It relies on atomic_fetch_add() having well defined forward progress + * guarantees under contention. If your architecture cannot provide this, stick + * to a test-and-set lock. + * + * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a + * sub-word of the value. This is generally true for anything LL/SC although + * you'd be hard pressed to find anything useful in architecture specifications + * about this. If your architecture cannot do this you might be better off with + * a test-and-set. + * + * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence + * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with + * a full fence after the spin to upgrade the otherwise-RCpc + * atomic_cond_read_acquire(). + * + * The implementation uses smp_cond_load_acquire() to spin, so if the + * architecture has WFE like instructions to sleep instead of poll for word + * modifications be sure to implement that (see ARM64 for example). + * + */ + +#ifndef __ASM_GENERIC_TICKET_SPINLOCK_H +#define __ASM_GENERIC_TICKET_SPINLOCK_H + +#include +#include + +static __always_inline void ticket_spin_lock(arch_spinlock_t *lock) +{ + u32 val = atomic_fetch_add(1<<16, &lock->val); + u16 ticket = val >> 16; + + if (ticket == (u16)val) + return; + + /* + * atomic_cond_read_acquire() is RCpc, but rather than defining a + * custom cond_read_rcsc() here we just emit a full fence. We only + * need the prior reads before subsequent writes ordering from + * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we + * have no outstanding writes due to the atomic_fetch_add() the extra + * orderings are free. + */ + atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL); + smp_mb(); +} + +static __always_inline bool ticket_spin_trylock(arch_spinlock_t *lock) +{ + u32 old = atomic_read(&lock->val); + + if ((old >> 16) != (old & 0xffff)) + return false; + + return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */ +} + +static __always_inline void ticket_spin_unlock(arch_spinlock_t *lock) +{ + u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); + u32 val = atomic_read(&lock->val); + + smp_store_release(ptr, (u16)val + 1); +} + +static __always_inline int ticket_spin_is_locked(arch_spinlock_t *lock) +{ + u32 val = atomic_read(&lock->val); + + return ((val >> 16) != (val & 0xffff)); +} + +static __always_inline int ticket_spin_is_contended(arch_spinlock_t *lock) +{ + u32 val = atomic_read(&lock->val); + + return (s16)((val >> 16) - (val & 0xffff)) > 1; +} + +static __always_inline int ticket_spin_value_unlocked(arch_spinlock_t lock) +{ + u32 val = lock.val.counter; + + return ((val >> 16) == (val & 0xffff)); +} + +#endif /* __ASM_GENERIC_TICKET_SPINLOCK_H */ From patchwork Tue Jun 28 08:17:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12897911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE2AEC43334 for ; Tue, 28 Jun 2022 08:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 28 Jun 2022 08:17:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5ECF3C341CD; Tue, 28 Jun 2022 08:17:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404255; bh=g2ZuhGG3HGmk8tNNjHUSt2Kmg34WaNBVGxTmVm8cja8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MSSOjJGt1ih1Cn49RlFQ/mtXij9nI3mrKbgo/KUAzz6M+7lTMN4r27STXJaA/mTi+ 9WAi8FJ0XOu4hKOYkc7ten0V8/0J8PX34tTOJYp+r30fJYMsof+mcRCAlvrpveTfcp ZQfTMKJN/h9W9mVUufrYPoa7kY/FJsHeUqujR0nRYMpKER5/VJID8BMAGkPGvMHAWf h35douftA+2TFVW5mZ0py8HMNHQbV8TAqVThnvMbRbNj1wZf2e8Ir4b9+gEm1fJIzt IpvoSjw84UWafAvDo/wbXmsYRvEOGAgfxAhawgHotgOJarvwsIyepz+KPcRiqeOaGA uVJ+dnjRebBbw== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 4/5] asm-generic: spinlock: Add combo spinlock (ticket & queued) Date: Tue, 28 Jun 2022 04:17:06 -0400 Message-Id: <20220628081707.1997728-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011736_384910_8F050FA2 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Some architecture has a flexible requirement on the type of spinlock. Some LL/SC architectures of ISA don't force micro-arch to give a strong forward guarantee. Thus different kinds of memory model micro-arch would come out in one ISA. The ticket lock is suitable for exclusive monitor designed LL/SC micro-arch with limited cores and "!NUMA". The queue-spinlock could deal with NUMA/large-scale scenarios with a strong forward guarantee designed LL/SC micro-arch. So, make the spinlock a combo with feature. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Arnd Bergmann Cc: Palmer Dabbelt --- include/asm-generic/spinlock.h | 43 ++++++++++++++++++++++++++++++++-- kernel/locking/qspinlock.c | 2 ++ 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h index f41dc7c2b900..a9b43089bf99 100644 --- a/include/asm-generic/spinlock.h +++ b/include/asm-generic/spinlock.h @@ -28,34 +28,73 @@ #define __ASM_GENERIC_SPINLOCK_H #include +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS +#include +#include + +DECLARE_STATIC_KEY_TRUE(use_qspinlock_key); +#endif + +#undef arch_spin_is_locked +#undef arch_spin_is_contended +#undef arch_spin_value_unlocked +#undef arch_spin_lock +#undef arch_spin_trylock +#undef arch_spin_unlock static __always_inline void arch_spin_lock(arch_spinlock_t *lock) { - ticket_spin_lock(lock); +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + queued_spin_lock(lock); + else +#endif + ticket_spin_lock(lock); } static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock) { +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + return queued_spin_trylock(lock); +#endif return ticket_spin_trylock(lock); } static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) { - ticket_spin_unlock(lock); +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + queued_spin_unlock(lock); + else +#endif + ticket_spin_unlock(lock); } static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock) { +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + return queued_spin_is_locked(lock); +#endif return ticket_spin_is_locked(lock); } static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock) { +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + return queued_spin_is_contended(lock); +#endif return ticket_spin_is_contended(lock); } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS + if (static_branch_likely(&use_qspinlock_key)) + return queued_spin_value_unlocked(lock); +#endif return ticket_spin_value_unlocked(lock); } diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 65a9a10caa6f..b7f7436f42f6 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -566,6 +566,8 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) } EXPORT_SYMBOL(queued_spin_lock_slowpath); +DEFINE_STATIC_KEY_TRUE_RO(use_qspinlock_key); + /* * Generate the paravirt code for queued_spin_unlock_slowpath(). */ From patchwork Tue Jun 28 08:17:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12897913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41E1DCCA485 for ; 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Tue, 28 Jun 2022 08:19:28 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o66Pi-005BjT-QF for linux-riscv@lists.infradead.org; Tue, 28 Jun 2022 08:17:41 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 172216119B; Tue, 28 Jun 2022 08:17:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CA11C341D2; Tue, 28 Jun 2022 08:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404257; bh=JqFV7DDNcb2WtTvmttuWFUJZ9dF8mrvDgNDPOvXP7pA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rZR/udrPjDgzmkasgazVKW71Q9L1U5Yjlg/JVDM6SdzaSlvUopcYpr9dc6xSEc31P C+mks00E0l3UgLpbDgIPLOqcai4O+QxWFAQhWcTMiJP1t5fBVEwa3GWgtGhr9YRbPd CRjt6CzzDbbB4bkTasOiEYyZWLNaneAphwHtNdfWOKlyR0sOvvNXOyyII5V6htUsQs iKEq/BOVfrVj3oH7BfrqV0KM9XBNcte8NY4F5VaabAgy+SE9rhyOijzfCwgFHTRFnk PWUUHOoFQsIY2lr2ZJVmVBp8bFroMD684CF9QeAIwOkizmECbLgbu4tne9RR52zoBR t5f2o0RaYkDng== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 5/5] riscv: Add qspinlock support Date: Tue, 28 Jun 2022 04:17:07 -0400 Message-Id: <20220628081707.1997728-6-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011739_063952_C9E2E444 X-CRM114-Status: GOOD ( 14.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Enable qspinlock by the requirements mentioned in a8ad07e5240c9 ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). - RISC-V atomic_*_release()/atomic_*_acquire() are implemented with own relaxed version plus acquire/release_fence for RCsc synchronization. - RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions). Some riscv cores such as BOOMv3 & XiangShan could provide strict & strong forward guarantee (The cache line would be kept in an exclusive state for Backoff cycles, and only this core's interrupt could break the LR/SC pair). - RISC-V provides cheap atomic_fetch_or_acquire() with RCsc. - RISC-V only provides relaxed xchg16 to support qspinlock. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Waiman Long Cc: Arnd Bergmann Cc: Palmer Dabbelt --- arch/riscv/Kconfig | 9 +++++++++ arch/riscv/include/asm/Kbuild | 2 ++ arch/riscv/include/asm/cmpxchg.h | 17 +++++++++++++++++ arch/riscv/kernel/setup.c | 4 ++++ 4 files changed, 32 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32ffef9f6e5b..47e12ab9c822 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -333,6 +333,15 @@ config NODES_SHIFT Specify the maximum number of NUMA Nodes available on the target system. Increases memory reserved to accommodate various tables. +config RISCV_USE_QUEUED_SPINLOCKS + bool "Using queued spinlock instead of ticket-lock" + depends on SMP && MMU + select ARCH_USE_QUEUED_SPINLOCKS + default y + help + Make sure your micro arch LL/SC has a strong forward progress guarantee. + Otherwise, stay at ticket-lock. + config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 504f8b7e72d4..2cce98c7b653 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -2,7 +2,9 @@ generic-y += early_ioremap.h generic-y += flat.h generic-y += kvm_para.h +generic-y += mcs_spinlock.h generic-y += parport.h +generic-y += qspinlock.h generic-y += spinlock.h generic-y += spinlock_types.h generic-y += qrwlock.h diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 12debce235e5..492104d45a23 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -17,6 +17,23 @@ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 2: { \ + u32 temp; \ + u32 shif = ((ulong)__ptr & 2) ? 16 : 0; \ + u32 mask = 0xffff << shif; \ + __ptr = (__typeof__(ptr))((ulong)__ptr & ~(ulong)2); \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " and %1, %0, %z3\n" \ + " or %1, %1, %z4\n" \ + " sc.w %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + : "=&r" (__ret), "=&r" (temp), "+A" (*__ptr) \ + : "rJ" (~mask), "rJ" (__new << shif) \ + : "memory"); \ + __ret = (__ret & mask) >> shif; \ + break; \ + } \ case 4: \ __asm__ __volatile__ ( \ " amoswap.w %0, %2, %1\n" \ diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index f0f36a4a0e9b..b9b234157a66 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -295,6 +295,10 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif +#if !defined(CONFIG_NUMA) && defined(CONFIG_QUEUED_SPINLOCKS) + static_branch_disable(&use_qspinlock_key); +#endif + riscv_fill_hwcap(); apply_boot_alternatives(); }