From patchwork Tue Jun 28 12:44:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01765C43334 for ; Tue, 28 Jun 2022 12:45:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345220AbiF1MpW (ORCPT ); Tue, 28 Jun 2022 08:45:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233434AbiF1MpU (ORCPT ); Tue, 28 Jun 2022 08:45:20 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14B45193ED; Tue, 28 Jun 2022 05:45:19 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id fd6so17390766edb.5; Tue, 28 Jun 2022 05:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qAna91f+tExWr/xWBecqjF79wZKKeqItDZrQk9dt538=; b=Sblb9A+txozzU3Urkkt5DVK0X8vW5h35NCjvQGnC8IdzJP8IskPVuBwJkTMIpo6mBf 9Y5qFSvLioo2V1KgLZ6VMzanYI2xnoroG+Klqq1GbrwkDhhnpQALto2hVW/qjzKrb6Hb wyKQPCkPVP3ICPyfXH9YhIbtUuRqWmS7tW+dWPxpdqkDNvhiSeM8PJUWBJxzNrXzt95N ehftd/9GtMoEqs0hjB7Y7D3su6I21X1USbUHtX5sYjcwz4EyRKyB2fPLw+JSmp24hyI4 Cv0U+L5aGHpx6MQLzrV/nddZQ4nzOgZ57ZK4C4YOhQ2cNrhTYfzw/UUP2FBqQxZHWIJM XgbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qAna91f+tExWr/xWBecqjF79wZKKeqItDZrQk9dt538=; b=QWqpkVIwfQ/hpT8GC6VVnQ8D+7xqvVXOt1pG7s/xbYcWhg1k1A/e3j7hIBC+qjiKgD rsxOSzY/n8R/L7O9lj/Btk40XbB5M101pIRrOqxAgQZBkyBZYPeKHPd43YetXlTlfP33 JUAHmIe/bzd5NuEB3KScbZPpjY+FsQSlIjpp+IVYOoeL21zbIeXK4vyZyW2FRsBkDGS4 nfBX6kK//bGQ7RpmX8RGsF4J29X7ZATqUAwH7JD+2mqT6KzOsYYm9yyKvdwB4THh/to5 0464cG+BAy1tIpWwE3WiVXweMzZTqSCZsyOsUmg8s7JrkrDtZzz5zDURzPyDcV5RBJIT 80mA== X-Gm-Message-State: AJIora8CiLUJVlM2aXUM/icsp/QAWXZKiFePcIEXnkVLkQRBmn8abGad G8tSfUjFxuWSUqJ07BhyzsA= X-Google-Smtp-Source: AGRyM1svJ8HWxHMKZ5Pu+TeawAFOCOEc/Rr1r9IR8nhjJ1l4ClmXg77Faof3WxaqAt2jTvIMO2mSpg== X-Received: by 2002:a05:6402:5384:b0:431:6d84:b451 with SMTP id ew4-20020a056402538400b004316d84b451mr22821873edb.46.1656420317609; Tue, 28 Jun 2022 05:45:17 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:17 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 1/9] dt-bindings: phy: lantiq: xway-rcu-usb2-phy: Convert to YAML Date: Tue, 28 Jun 2022 14:44:33 +0200 Message-Id: <20220628124441.2385023-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Convert the Lantiq XWAY RCU USB2 PHY bindings to YAML. Signed-off-by: Martin Blumenstingl --- .../phy/lantiq,xway-rcu-usb2-phy.yaml | 68 +++++++++++++++++++ .../bindings/phy/phy-lantiq-rcu-usb2.txt | 40 ----------- 2 files changed, 68 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt diff --git a/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml new file mode 100644 index 000000000000..702a8e8c64b5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/lantiq,xway-rcu-usb2-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/lantiq,xway-rcu-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding + +maintainers: + - Martin Blumenstingl + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - lantiq,ase-usb2-phy + - lantiq,danube-usb2-phy + - lantiq,xrx100-usb2-phy + - lantiq,xrx200-usb2-phy + - lantiq,xrx300-usb2-phy + + reg: + minItems: 2 + + clocks: + minItems: 1 + + clock-names: + items: + - const: phy + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + items: + - const: phy + - const: ctrl + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x18 4>, <0x38 4>; + + clocks = <&pmu_USB0_PHY>; + clock-names = "phy"; + + resets = <&reset1 4 4>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt deleted file mode 100644 index 643948b6b576..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt +++ /dev/null @@ -1,40 +0,0 @@ -Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding -=========================================== - -This binding describes the USB PHY hardware provided by the RCU module on the -Lantiq XWAY SoCs. - -This node has to be a sub node of the Lantiq RCU block. - -------------------------------------------------------------------------------- -Required properties (controller (parent) node): -- compatible : Should be one of - "lantiq,ase-usb2-phy" - "lantiq,danube-usb2-phy" - "lantiq,xrx100-usb2-phy" - "lantiq,xrx200-usb2-phy" - "lantiq,xrx300-usb2-phy" -- reg : Defines the following sets of registers in the parent - syscon device - - Offset of the USB PHY configuration register - - Offset of the USB Analog configuration - register (only for xrx200 and xrx200) -- clocks : References to the (PMU) "phy" clk gate. -- clock-names : Must be "phy" -- resets : References to the RCU USB configuration reset bits. -- reset-names : Must be one of the following: - "phy" (optional) - "ctrl" (shared) - -------------------------------------------------------------------------------- -Example for the USB PHYs on an xRX200 SoC: - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - clocks = <&pmu PMU_GATE_USB0_PHY>; - clock-names = "phy"; - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; From patchwork Tue Jun 28 12:44:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB2A1CCA479 for ; Tue, 28 Jun 2022 12:45:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344392AbiF1MpW (ORCPT ); Tue, 28 Jun 2022 08:45:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238586AbiF1MpV (ORCPT ); Tue, 28 Jun 2022 08:45:21 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2214E1D0DC; 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[95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:18 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 2/9] dt-bindings: reset: intel,rcu-gw: Allow up to three global reset items Date: Tue, 28 Jun 2022 14:44:34 +0200 Message-Id: <20220628124441.2385023-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Legacy SoCs use three elements for the global reset: - offset - reset bit - status bit Allow this in the dt-bindings as well. Fixes: b7ab0cb00d086b ("dt-bindings: reset: Add YAML schemas for the Intel Reset controller") Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml index 13bf6bb3f097..be64f8597710 100644 --- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -22,11 +22,15 @@ properties: intel,global-reset: description: Global reset register offset and bit offset. $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 items: - description: Register offset - description: Register bit offset minimum: 0 maximum: 31 + - description: Status bit offset (only if "#reset-cells" is 3) + minimum: 0 + maximum: 31 "#reset-cells": minimum: 2 From patchwork Tue Jun 28 12:44:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B991C433EF for ; Tue, 28 Jun 2022 12:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345291AbiF1MpX (ORCPT ); Tue, 28 Jun 2022 08:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240118AbiF1MpW (ORCPT ); Tue, 28 Jun 2022 08:45:22 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09DA11D0FE; Tue, 28 Jun 2022 05:45:21 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id ej4so17395557edb.7; Tue, 28 Jun 2022 05:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cnf6pcj5vpCMbTgtadV2bK80NwflBsx3RadXRu/q84M=; b=B+j85IdQS+Xntj9SF6zbCBxyVHzt4nedW5mC16gCblDiLxqEwiEKaGjBWnJxNbbxza WRQlNzQSy1+kmCH2Mao/5NdE5KOWsSMSQM5COm2vNU25odKJ17pCD+mW/MLQkVTPx3ZL ELDxzTSrWCbKZvdjGL3Igh0lMSffAp6M8J6cIBVsaQpd8Yg4APdkUH39sbEP3qRecjOe Ev0Ag1R6uY6KX3MS49lehzdzuU+SMTY3kyMBDd1v32FavGke7XXu89oKCXW4+ybqeaj3 yUoAimTthTjprexnZ0sntVrw/LKYm0xQmRrPstdQn7ApzHnlsm2HPMm3FJ7y//POtGN2 i6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cnf6pcj5vpCMbTgtadV2bK80NwflBsx3RadXRu/q84M=; b=rzIryrI09O8PkCL1gyo26XAOjw0lDdQRAHZ8Ywek4gRRaBBb/xXeIZjDAIf1I3CJzv J4i0EPBOm61aJQXBsdyXlUTpAl4vfBg8EtsVQCaQtOPiFPEuD3Nxuk5LaIoFbnNEtvre rZFW4JhuzG8BV6pDTcQJ/XYbAW78O3fF8T7T9c1R1RCn3w04ZVaWBVOZaYBiwJfGQtNs 7QsP91RaejSIiQXfKPqGhBnX1FUUks7jfdvld5aqCpJ9EztMDAxfpQQItOk3Nz+7ZCFI mkGF7kaOZgNWH2uFR6m+FzVwK+TBfm2jNJ99QXcJSCSokFgxz9rUXJB8XTg4MYeo2OmW Y56A== X-Gm-Message-State: AJIora9wSuTQUzbR+1Z9CDLfid/Q9ub+DqMaxEi8qsJ9r+eEvhj8bAmj ekJBZ1x3e4Rvub3XJYpIy/I= X-Google-Smtp-Source: AGRyM1uwTe6v4t4C+Cj8uTSAWOl21YQ49mX5FGF++g1vgFNyOS/JkYzaDrYYbPLO26Eiax2DA4KF1g== X-Received: by 2002:a05:6402:27c8:b0:435:d40e:c648 with SMTP id c8-20020a05640227c800b00435d40ec648mr23155962ede.200.1656420319512; Tue, 28 Jun 2022 05:45:19 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:19 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 3/9] dt-bindings: reset: intel,rcu-gw: Update bindings for "legacy" SoCs Date: Tue, 28 Jun 2022 14:44:35 +0200 Message-Id: <20220628124441.2385023-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The Lantiq Amazon-SE, Danube, xRX100 and xRX200 SoCs have up to two USB2 PHYs which are part of the RCU register space. The RCU registers on these SoCs are using big endian. Update the binding for these SoCs to properly describe this IP: - Add compatible strings for Amazon-SE, Danube and xRX100 - Rename the xRX200 compatible string (which is not used anywhere) and switch to the one previously documented in mips/lantiq/rcu.txt - Allow usage of "simple-mfd" and "syscon" in the compatible string so the child devices (USB2 PHYs) can be described - Allow #address-cells and #size-cells to be set to 1 for describing the child devices (USB2 PHYs) - #reset-cells must always be 3 (offset, reset bit and status bit) on the legacy SoCs while LGM uses a fixed value of 2 (offset and reset bit - status bit is always identical to the reset bit). Signed-off-by: Martin Blumenstingl --- .../bindings/reset/intel,rcu-gw.yaml | 84 +++++++++++++++++-- 1 file changed, 79 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml index be64f8597710..b90913c7b7d3 100644 --- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -11,9 +11,16 @@ maintainers: properties: compatible: - enum: - - intel,rcu-lgm - - intel,rcu-xrx200 + oneOf: + - items: + - enum: + - lantiq,ase-rcu + - lantiq,danube-rcu + - lantiq,xrx100-rcu + - lantiq,xrx200-rcu + - const: simple-mfd + - const: syscon + - const: intel,rcu-lgm reg: description: Reset controller registers. @@ -33,8 +40,6 @@ properties: maximum: 31 "#reset-cells": - minimum: 2 - maximum: 3 description: | First cell is reset request register offset. Second cell is bit offset in reset request register. @@ -43,6 +48,43 @@ properties: reset request and reset status registers is same. Whereas 3 for legacy SoCs as bit offset differs. + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + big-endian: true + +patternProperties: + "^usb2-phy@[0-9a-f]+$": + type: object + $ref: "../phy/lantiq,xway-rcu-usb2-phy.yaml" + +allOf: + - if: + properties: + compatible: + contains: + const: intel,rcu-lgm + then: + properties: + "#reset-cells": + const: 2 + - if: + properties: + compatible: + contains: + enum: + - lantiq,ase-rcu + - lantiq,danube-rcu + - lantiq,xrx100-rcu + - lantiq,xrx200-rcu + then: + properties: + "#reset-cells": + const: 3 + required: - compatible - reg @@ -67,3 +109,35 @@ examples: #pwm-cells = <2>; resets = <&rcu0 0x30 21>; }; + - | + rcu_xrx200: rcu@203000 { + compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x100>; + big-endian; + + #address-cells = <1>; + #size-cells = <1>; + + #reset-cells = <3>; + intel,global-reset = <0x10 30 29>; + + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x18 4>, <0x38 4>; + status = "disabled"; + + resets = <&rcu_xrx200 0x48 4 4>, <&rcu_xrx200 0x10 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + + usb_phy1: usb2-phy@34 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x34 4>, <0x3c 4>; + status = "disabled"; + + resets = <&rcu_xrx200 0x48 5 5>, <&rcu_xrx200 0x10 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + }; From patchwork Tue Jun 28 12:44:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3070EC43334 for ; Tue, 28 Jun 2022 12:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345348AbiF1MpZ (ORCPT ); Tue, 28 Jun 2022 08:45:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345290AbiF1MpX (ORCPT ); Tue, 28 Jun 2022 08:45:23 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 153DB193ED; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id h23so25450013ejj.12; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CKQyH9C8gO8jBo4jczcS1bhOdjsHy0Bi1N6w+JS8218=; b=LjmaQv+UaMIjunLurOL+z37Ha+0Ha5xCcz8TSNyiWiX4mT4KHEwjXmxN+fag+bM0Am yDXP1r7Xc6Zz5IsXYiUJh6k9bSR4DbvAQr6mvKlUF1GPcxRFliO3pFHhUdQEFvePNov0 +UIkfd/sF5nx41cPYL1xor8DJo3YHYiF/Im0ty1E8n7A12RL/Zo7VOtUYSr4JgaddVhr z/ErA31vpWhM9EtFwZomRV3mkYkLBlX1ziGbMxFswIl2irSQ/jybJ9VUylYimIv8ArsP Cdo7e59GNGqfPv89fyweeII2sry/rHE+H5XvLiw7049ZtQJl/rkSJiEKUNwVsOTBCfSr dryA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CKQyH9C8gO8jBo4jczcS1bhOdjsHy0Bi1N6w+JS8218=; b=FnduCv2gR+mc6t+K9JQaabi/FvXaRGMNA/Dfbe5MhmD+jVI4KccutYp053DVAMqhgt ALBbDlagVf5jLMwwNF11Vypvwn4aUuh4XLVyOi9UCYLgv6uvEPA7RtdH9IeW41K0LnIv zZ25xJqO/9GuBbzG8EeF2/IW8jpMVwR+Cmv2IaayowUi+MW/EHWxzRcst2kYArK5aHwp Zhnqxjw7fTIiNwH8gkgtvMvlHPhZ2DvdHZn3vbrZe5+gOiAtaX/YfPrDhpr5VY9belIV MktscxYnyM1BREJeC86rtJ7M4LgpJgtmhFW7qxzsCGQhP3ryGicOiSCn7TSa6JHjJAFn VASg== X-Gm-Message-State: AJIora/3uCq+swb0NAutNCoSmW4Dm1PQZpt51cbG9GV251CUks1Ich13 HPCriuuKZyQQfPDnPRcw4Qs= X-Google-Smtp-Source: AGRyM1uy7MEZIEthYVomXDaHu9jetS7Xdb/FUEi0ipDJra34TCTFPRGKmuJ7DXtAsyRDRkeBXtJgBQ== X-Received: by 2002:a17:906:e256:b0:726:abd9:1063 with SMTP id gq22-20020a170906e25600b00726abd91063mr8552132ejb.741.1656420320598; Tue, 28 Jun 2022 05:45:20 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:20 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 4/9] dt-bindings: mips: lantiq: rcu: Remove binding documentation Date: Tue, 28 Jun 2022 14:44:36 +0200 Message-Id: <20220628124441.2385023-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This is now part of: Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml The PHYs are still using sub-nodes while the reset-controller is moved to the main RCU node. Also the system reboot is now described directly in intel,rcu-gw.yaml which makes the syscon-reboot node obsolete. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring --- .../devicetree/bindings/mips/lantiq/rcu.txt | 69 ------------------- 1 file changed, 69 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt deleted file mode 100644 index 58d51f480c9e..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt +++ /dev/null @@ -1,69 +0,0 @@ -Lantiq XWAY SoC RCU binding -=========================== - -This binding describes the RCU (reset controller unit) multifunction device, -where each sub-device has it's own set of registers. - -The RCU register range is used for multiple purposes. Mostly one device -uses one or multiple register exclusively, but for some registers some -bits are for one driver and some other bits are for a different driver. -With this patch all accesses to the RCU registers will go through -syscon. - - -------------------------------------------------------------------------------- -Required properties: -- compatible : The first and second values must be: - "lantiq,xrx200-rcu", "simple-mfd", "syscon" -- reg : The address and length of the system control registers - - -------------------------------------------------------------------------------- -Example of the RCU bindings on a xRX200 SoC: - rcu0: rcu@203000 { - compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x100>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - reset1: reset-controller@48 { - compatible = "lantiq,xrx200-reset"; - reg = <0x48 4>, <0x24 4>; - - #reset-cells = <2>; - }; - - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - usb_phy1: usb2-phy@34 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x34 4>, <0x3C 4>; - - resets = <&reset1 5 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - reboot@10 { - compatible = "syscon-reboot"; - reg = <0x10 4>; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - }; From patchwork Tue Jun 28 12:44:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65578CCA480 for ; Tue, 28 Jun 2022 12:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345420AbiF1Mp0 (ORCPT ); Tue, 28 Jun 2022 08:45:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345328AbiF1MpY (ORCPT ); Tue, 28 Jun 2022 08:45:24 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE9C21D0FE; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id n8so3436883eda.0; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OC/Q0ZHSYivrSfFoAF8zUByQ32IP+ZgOcCZoC0yMQAM=; b=MHL34CI71jL8wxvfIo3kffmm6/Bzw/zxa4CCePVNSukTsqOG4zJCqZbR4IQ1WfSXda 23Cw8J9CMbGMEBKxBYOSkHrh3hqgyXrY2wjsTguu+bx9/hVf6/bJrHYeZXa//qVQAvqV ixOQEP8JPKMDauiCghdNu0zNGLPYfXSyVxJzTG0BI5K63EPR/gAhM5dKetJkrJmW/fR9 xXurrBhZHaOiYR2QC+De+xa+UbtcJk1Vv+rUmi8kSfu/3lv0L0DqWmkiwQzRfrTednpo fLbWFah/u1N234w0DqNvtk3UE/yt7Eh6z8M3ei1Pd0f5l51wej/FKIhVZyDeaIarLQh3 r7gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OC/Q0ZHSYivrSfFoAF8zUByQ32IP+ZgOcCZoC0yMQAM=; b=g0idSh+zYrhfi3gTCQXD+b8xjnkTMKSBF5bnGadF1Fhr/1IjKnA31n3XpcHYQ715bf abesNBmqFYur6XiU6fIQHfuyqy8RHvVr2BICGYZok16ktk0hWKI2aVzEcGQAmdebSPA+ i7jxT8gCRrye7Iy9qdYGUDb+/aA9RfbtOE9GKdHXnuxwD7VTT5Wsr2DwWjHxKefpqBJY +7tqdCMYKvTUmaJo7CfdrsN1M6Iw3OgC50FMRHlD+/T6jwX0kax3ZoLW9YlVSYUOjDkr VOQ4AqPMTjYURGw2jSXx6itycqMn6/8NXOlpeoFH76AyLXJfOoVGViZJKXg6sV43djE+ MKKQ== X-Gm-Message-State: AJIora/lJIxpMlAfopuauahbolXV1EPwRIJjHqiFHFAo7lcxwyAqTVIo NZZFryXtrXJoroivORFyr9wRhxxRtnY= X-Google-Smtp-Source: AGRyM1vqBRQVrT6TUJUFUK5kgHWfZrgH/Pox3xpk7zeJlTAV5RZe6o1hdfy1TmD9IPFIQ71bSiek+Q== X-Received: by 2002:a05:6402:5306:b0:437:8bbd:b313 with SMTP id eo6-20020a056402530600b004378bbdb313mr14675188edb.123.1656420321414; Tue, 28 Jun 2022 05:45:21 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:21 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 5/9] reset: intel: Allow enabling the driver on "LANTIQ" (MIPS) platforms Date: Tue, 28 Jun 2022 14:44:37 +0200 Message-Id: <20220628124441.2385023-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Lantiq MIPS SoC use CONFIG_LANTIQ. Allow enabling the Intel GW reset driver there as well so we can get rid of the reset-lantiq driver in future. Signed-off-by: Martin Blumenstingl --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..68a5ea44612e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -84,7 +84,7 @@ config RESET_IMX7 config RESET_INTEL_GW bool "Intel Reset Controller Driver" - depends on X86 || COMPILE_TEST + depends on X86 || LANTIQ || COMPILE_TEST depends on OF && HAS_IOMEM select REGMAP_MMIO help From patchwork Tue Jun 28 12:44:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E859C43334 for ; Tue, 28 Jun 2022 12:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345852AbiF1Mpg (ORCPT ); Tue, 28 Jun 2022 08:45:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345367AbiF1Mp0 (ORCPT ); Tue, 28 Jun 2022 08:45:26 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61EEA193ED; Tue, 28 Jun 2022 05:45:23 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id z7so17351981edm.13; Tue, 28 Jun 2022 05:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QkD5ZdlMfFp9BqXoXwOYIRoxn3i+2Ef4KXobvEMyiVo=; b=RARWGWYAnD1Tn9kDygIdnwtnUPjcHumdDo4lilQszfGD18lQdgNgi/Ryn1jc+D1oug D96C3smjnVPUr1RCcaPTZBUpoNhJsICKCnWV07vAJ+dil1HAN8mhg+3mc8S2vm0PAlDP tx6BBB8nKfouvX5z+OZPqAKaSu5FlF1sIgUgb7ml2HV5BKV16WYJx2jhYQYRirHYFpcH ongbZI5osfzqM9O1WAGweu+dmoyVyh7X66dqEPYg56HWLqVhBRX0Jjail790UpANcCmU 3L34pCNmjrfoVERLs7tKWqbCa0iwLMJcHEwa+k0+sjm3gYzkTxIsGzv8NTUgsz9vCGhI wx9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QkD5ZdlMfFp9BqXoXwOYIRoxn3i+2Ef4KXobvEMyiVo=; b=ddRE9AADGEdEnPkvqY2ZK9w39v37F9otLM1AEWtAKyxkslrE5nwjKsaBBujAda4Oyt 86rCWBl1tsO4/lxtk2BQaf1HOsxEkZCwZkhRU4hDGWnsIDxpKhbuwGgHDJ+dDT7EpDdg mUG8L4pxZe9SA22vxMQ+kJkVAi8log+yl7QwfgkQH1kMHqf3K5lwTAHxX8Xkljsko1ps nh3oVcHr9lidhey2gnv8uZbQRICOEMACArzNXycn76PYSgZCRqM49zQkZPm3jkl6j6V5 JPjKRHhAa2JzA3YR03gHLrkzRR+C9PCRwSs+vB8EXSXCpQ6uV9nFJBZ5p+2XfbV3xfRu bZCw== X-Gm-Message-State: AJIora+1oLIlYhN0tLDYKzS7Y7U10vgQWvqICZVaCI1Vcx/CG4qPCBSh TAKJwM11xs7n9KkVEK3yU5o= X-Google-Smtp-Source: AGRyM1ssn0vDK56CFH/r87RlWCyxx7oYUzSFnXO1WBdJwdhLCtV04NDaUAeCU7F3U3g+HfhhvVTPDg== X-Received: by 2002:a05:6402:51c7:b0:437:a22c:60f5 with SMTP id r7-20020a05640251c700b00437a22c60f5mr8917530edd.281.1656420322252; Tue, 28 Jun 2022 05:45:22 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:21 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 6/9] reset: intel: Add and update compatible strings Lantiq SoCs Date: Tue, 28 Jun 2022 14:44:38 +0200 Message-Id: <20220628124441.2385023-7-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Amazon-SE, Danube and xRX100 only have one reset request and one status register whereas xRX200 has two of each. Add compatible strings for the former three and update the compatible string for xRX200 to the same as in Documentation/devicetree/bindings/mips/lantiq/rcu.txt (old RCU binding documentation). Signed-off-by: Martin Blumenstingl --- drivers/reset/reset-intel-gw.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-intel-gw.c b/drivers/reset/reset-intel-gw.c index effc177db80a..46ed7a693666 100644 --- a/drivers/reset/reset-intel-gw.c +++ b/drivers/reset/reset-intel-gw.c @@ -223,7 +223,7 @@ static int intel_reset_probe(struct platform_device *pdev) return 0; } -static const struct intel_reset_soc xrx200_data = { +static const struct intel_reset_soc xway_data = { .legacy = true, .reset_cell_count = 3, }; @@ -235,7 +235,10 @@ static const struct intel_reset_soc lgm_data = { static const struct of_device_id intel_reset_match[] = { { .compatible = "intel,rcu-lgm", .data = &lgm_data }, - { .compatible = "intel,rcu-xrx200", .data = &xrx200_data }, + { .compatible = "lantiq,ase-rcu", .data = &xway_data }, + { .compatible = "lantiq,danube-rcu", .data = &xway_data }, + { .compatible = "lantiq,xrx100-rcu", .data = &xway_data }, + { .compatible = "lantiq,xrx200-rcu", .data = &xway_data }, {} }; From patchwork Tue Jun 28 12:44:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C157C433EF for ; Tue, 28 Jun 2022 12:45:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345857AbiF1Mpg (ORCPT ); Tue, 28 Jun 2022 08:45:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345476AbiF1Mp0 (ORCPT ); Tue, 28 Jun 2022 08:45:26 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A16BB205DE; Tue, 28 Jun 2022 05:45:24 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id ay16so25533193ejb.6; Tue, 28 Jun 2022 05:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X+4C91pBPuruAy2SRc0UhNyMy5LTHEOk4TXkwRVqGsA=; b=DSh1qQ0rIGt4CcyCfN6ZANz2B9InOMMi8Y8ooiZhU/J2JSd6dMIR4sTY2nB1Z83mDM 21c2NAjI9GWt5JSsAxSVz6lHVn7s1LX9G9byRpY03+c/i7jyxysdlN3QmkLwUe3CIsmY CRVpalQd5kQUqUp+/w/o1svh2ZcshK7VEC77pWrApzObYapwgR7nxJTEc6s1p8jsIgRl qgHk8TPwFpTGUt6ynhNvD5AZ1cfUS4AQRgIKIDe0VtHBy8cn4XLr5Mq59SQJML3tFWny howy9kNXIDizrIwmYrQNqtBXM8OMfEFCv7sGq4gCfUbH+ufj/7vjhC2ScSnZlxWZJD12 ztQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X+4C91pBPuruAy2SRc0UhNyMy5LTHEOk4TXkwRVqGsA=; b=A6pXQdV/M9QB0m34tHVS/5glTBWEo0l0q9+FcqX7ZJ7Wv5rzHxjVpo6h5ggJbqhJiE +3twkOQdtn41HVIPMI/4X2Z8pH3aqUSeu5CcRgCYSa9N/3zH6LsDi/avhlJzum8JEZPJ T4w/NmdRTW6AZhMDKe2Mhqv8cjfj26ZoFM2IUGmtX35ZenjqSys6lydCbKg9xbzSI83G P73GdGIYrJUfma4hSdOCDmECgMWN0p1hKTavJkxZKxvvLtZ/ISBLr8HkY7HnwfvZLMSC uabZVfI+T7/OeUmXZj1NRVLE+2CX3b93bNMTfDULdh3bZ8xGxzIg/V8dYa2yoFDUdo3e J5+Q== X-Gm-Message-State: AJIora/QgXN4iS1J5d3bOiGYzVb2Wue64MUNmiTa+ZF5n7+/wdeTbfjR DT8i+Bl30jtdPZ1dikQXjKA= X-Google-Smtp-Source: AGRyM1tqzBvDQCUi6RRScG2xpFlt5U6tlV23lkx33B4FpNGHMgJQZEy49e5pO+76w3Lr/SNE+MEY6w== X-Received: by 2002:a17:906:9b93:b0:722:f3e8:3f5e with SMTP id dd19-20020a1709069b9300b00722f3e83f5emr17953859ejc.65.1656420323128; Tue, 28 Jun 2022 05:45:23 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:22 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 7/9] reset: intel: Use syscon_node_to_regmap on legacy SoCs Date: Tue, 28 Jun 2022 14:44:39 +0200 Message-Id: <20220628124441.2385023-8-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Older Lantiq (called "legacy") SoCs the RCU registers have more than just the reset controller registers. It additionally contains boot media selection information, up to two USB2 PHYs and configuration for various other peripherals (such as the PCIe PHY). use syscon_node_to_regmap() to obtain the regmap on these SoCs. Signed-off-by: Martin Blumenstingl --- drivers/reset/Kconfig | 3 ++- drivers/reset/reset-intel-gw.c | 29 +++++++++++++++++++---------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 68a5ea44612e..fb49c465078f 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -86,7 +86,8 @@ config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || LANTIQ || COMPILE_TEST depends on OF && HAS_IOMEM - select REGMAP_MMIO + select REGMAP_MMIO if X86 + select MFD_SYSCON if LANTIQ help This enables the reset controller driver for Intel Gateway SoCs. Say Y to control the reset signals provided by reset controller. diff --git a/drivers/reset/reset-intel-gw.c b/drivers/reset/reset-intel-gw.c index 46ed7a693666..0bf7fe4e77ae 100644 --- a/drivers/reset/reset-intel-gw.c +++ b/drivers/reset/reset-intel-gw.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -170,7 +171,6 @@ static int intel_reset_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct intel_reset_data *data; - void __iomem *base; u32 rb_id[3]; int ret; @@ -182,15 +182,24 @@ static int intel_reset_probe(struct platform_device *pdev) if (!data->soc_data) return -ENODEV; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - data->regmap = devm_regmap_init_mmio(dev, base, - &intel_rcu_regmap_config); - if (IS_ERR(data->regmap)) { - dev_err(dev, "regmap initialization failed\n"); - return PTR_ERR(data->regmap); + if (data->soc_data->legacy) { + data->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), + "Failed to get regmap from syscon node\n"); + } else { + void __iomem *base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + data->regmap = devm_regmap_init_mmio(dev, base, + &intel_rcu_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(dev, "regmap initialization failed\n"); + return PTR_ERR(data->regmap); + } } ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id, From patchwork Tue Jun 28 12:44:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12898231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CF17C43334 for ; Tue, 28 Jun 2022 12:45:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345860AbiF1Mph (ORCPT ); Tue, 28 Jun 2022 08:45:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345810AbiF1Mpe (ORCPT ); Tue, 28 Jun 2022 08:45:34 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AD7F1D0DC; Tue, 28 Jun 2022 05:45:25 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id u15so25492228ejc.10; Tue, 28 Jun 2022 05:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FUvTBZSvTkQG8k5ahx+vCE8pnavlPjrhJsWTl2v7qY4=; b=YUsA1imIhupuf9Wojjd9t1tkr06B/Q5S+154aH/XHbZiBawjU/E3OSL0UxsAjaTQSq 2Ttr42qCSlo9mEQGVAEd7GFglPPvmNBMTDfpZ4Np4BSsCmSm4lltW8n0WAZgY4Tl7j6n oOGDhXVfcxu4RL5rhr/VynR6l7ATR5G7koin5wvSdPynWfmgUzEMouVgCIwuF3bZlnHN pYPE9fYeE1mCy7z7AkDBi5LV0Kl6de/fqQ6yZib5eMkINF4h/QJS1b7zCFrX6RX8nQXf DWHLqxAoYTHHbO8yBlxzMzVzVFOprF5e+duPfuyyB+obihpjp1V6Pl9W+Fz2Pher7Jmi TjdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FUvTBZSvTkQG8k5ahx+vCE8pnavlPjrhJsWTl2v7qY4=; b=Ln30lMjp66Ap7wnOlQClsfvcDAjen2P7OOjl+iol17zrWqYb9oLtSGQz782NqmDeZZ gpigUGJEXQccuDr15JSunJndXqdiWDgpWs3Rnp24K60doEVILCME3WgiMrdPgAr6wZB6 1vrpvajNF1GxCV8BQrlnl5bi1MlX7igI9e7XFMEGqPW7kpTUXxLV6BDzfEMcy3vyu2p9 PK4kVtn0ZoDCQJcexKWd+/Rss3tnsfLXJzNkVFEiSPqy27wfsUFYO/YIZMN+E87adGq+ jsX27kafbaf8QJ5o03ItGPeJ6fTYpn3x0zcstxE3iW5WF95Li0ZswRKFonFr9oQDVmh3 U8ug== X-Gm-Message-State: AJIora+07xdsgbjEHNV2O5pEgjzlUS91/kGrOthp2eFq7Icx8Ni9ZXhB Lw4CAuURQIib7NCqyvxbg5M= X-Google-Smtp-Source: AGRyM1uyuIl2+iwMosBXcvxSsRRQMisrWpqCTCRI2n8Z/h8yD5HhzesYWyv9VyZ3X2v8ii8N8r1Org== X-Received: by 2002:a17:907:3ea6:b0:726:3554:cf7a with SMTP id hs38-20020a1709073ea600b007263554cf7amr17753304ejc.384.1656420324011; Tue, 28 Jun 2022 05:45:24 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-114-061-215.95.114.pool.telefonica.de. [95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:23 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 8/9] reset: lantiq: Remove driver as it has been replaced by reset-intel-gw Date: Tue, 28 Jun 2022 14:44:40 +0200 Message-Id: <20220628124441.2385023-9-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Now that we have replaced the reset-lantiq driver with the reset-intel-gw driver we can remove the old code. Signed-off-by: Martin Blumenstingl --- drivers/reset/Kconfig | 6 - drivers/reset/Makefile | 1 - drivers/reset/reset-lantiq.c | 210 ----------------------------------- 3 files changed, 217 deletions(-) delete mode 100644 drivers/reset/reset-lantiq.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index fb49c465078f..22e28f5cf154 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -103,12 +103,6 @@ config RESET_K210 Say Y if you want to control reset signals provided by this controller. -config RESET_LANTIQ - bool "Lantiq XWAY Reset Driver" if COMPILE_TEST - default SOC_TYPE_XWAY - help - This enables the reset controller driver for Lantiq / Intel XWAY SoCs. - config RESET_LPC18XX bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST default ARCH_LPC18XX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..9cb37e7890f1 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_K210) += reset-k210.o -obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o diff --git a/drivers/reset/reset-lantiq.c b/drivers/reset/reset-lantiq.c deleted file mode 100644 index b936cfe85641..000000000000 --- a/drivers/reset/reset-lantiq.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * - * Copyright (C) 2010 John Crispin - * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG - * Copyright (C) 2016 Martin Blumenstingl - * Copyright (C) 2017 Hauke Mehrtens - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define LANTIQ_RCU_RESET_TIMEOUT 10000 - -struct lantiq_rcu_reset_priv { - struct reset_controller_dev rcdev; - struct device *dev; - struct regmap *regmap; - u32 reset_offset; - u32 status_offset; -}; - -static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv( - struct reset_controller_dev *rcdev) -{ - return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev); -} - -static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev); - unsigned int status = (id >> 8) & 0x1f; - u32 val; - int ret; - - ret = regmap_read(priv->regmap, priv->status_offset, &val); - if (ret) - return ret; - - return !!(val & BIT(status)); -} - -static int lantiq_rcu_reset_status_timeout(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) -{ - int ret; - int retry = LANTIQ_RCU_RESET_TIMEOUT; - - do { - ret = lantiq_rcu_reset_status(rcdev, id); - if (ret < 0) - return ret; - if (ret == assert) - return 0; - usleep_range(20, 40); - } while (--retry); - - return -ETIMEDOUT; -} - -static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) -{ - struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev); - unsigned int set = id & 0x1f; - u32 val = assert ? BIT(set) : 0; - int ret; - - ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set), - val); - if (ret) { - dev_err(priv->dev, "Failed to set reset bit %u\n", set); - return ret; - } - - - ret = lantiq_rcu_reset_status_timeout(rcdev, id, assert); - if (ret) - dev_err(priv->dev, "Failed to %s bit %u\n", - assert ? "assert" : "deassert", set); - - return ret; -} - -static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return lantiq_rcu_reset_update(rcdev, id, true); -} - -static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return lantiq_rcu_reset_update(rcdev, id, false); -} - -static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - int ret; - - ret = lantiq_rcu_reset_assert(rcdev, id); - if (ret) - return ret; - - return lantiq_rcu_reset_deassert(rcdev, id); -} - -static const struct reset_control_ops lantiq_rcu_reset_ops = { - .assert = lantiq_rcu_reset_assert, - .deassert = lantiq_rcu_reset_deassert, - .status = lantiq_rcu_reset_status, - .reset = lantiq_rcu_reset_reset, -}; - -static int lantiq_rcu_reset_of_parse(struct platform_device *pdev, - struct lantiq_rcu_reset_priv *priv) -{ - struct device *dev = &pdev->dev; - const __be32 *offset; - - priv->regmap = syscon_node_to_regmap(dev->of_node->parent); - if (IS_ERR(priv->regmap)) { - dev_err(&pdev->dev, "Failed to lookup RCU regmap\n"); - return PTR_ERR(priv->regmap); - } - - offset = of_get_address(dev->of_node, 0, NULL, NULL); - if (!offset) { - dev_err(&pdev->dev, "Failed to get RCU reset offset\n"); - return -ENOENT; - } - priv->reset_offset = __be32_to_cpu(*offset); - - offset = of_get_address(dev->of_node, 1, NULL, NULL); - if (!offset) { - dev_err(&pdev->dev, "Failed to get RCU status offset\n"); - return -ENOENT; - } - priv->status_offset = __be32_to_cpu(*offset); - - return 0; -} - -static int lantiq_rcu_reset_xlate(struct reset_controller_dev *rcdev, - const struct of_phandle_args *reset_spec) -{ - unsigned int status, set; - - set = reset_spec->args[0]; - status = reset_spec->args[1]; - - if (set >= rcdev->nr_resets || status >= rcdev->nr_resets) - return -EINVAL; - - return (status << 8) | set; -} - -static int lantiq_rcu_reset_probe(struct platform_device *pdev) -{ - struct lantiq_rcu_reset_priv *priv; - int err; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = &pdev->dev; - platform_set_drvdata(pdev, priv); - - err = lantiq_rcu_reset_of_parse(pdev, priv); - if (err) - return err; - - priv->rcdev.ops = &lantiq_rcu_reset_ops; - priv->rcdev.owner = THIS_MODULE; - priv->rcdev.of_node = pdev->dev.of_node; - priv->rcdev.nr_resets = 32; - priv->rcdev.of_xlate = lantiq_rcu_reset_xlate; - priv->rcdev.of_reset_n_cells = 2; - - return devm_reset_controller_register(&pdev->dev, &priv->rcdev); -} - -static const struct of_device_id lantiq_rcu_reset_dt_ids[] = { - { .compatible = "lantiq,danube-reset", }, - { .compatible = "lantiq,xrx200-reset", }, - { }, -}; -MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids); - -static struct platform_driver lantiq_rcu_reset_driver = { - .probe = lantiq_rcu_reset_probe, - .driver = { - .name = "lantiq-reset", - .of_match_table = lantiq_rcu_reset_dt_ids, - }, -}; -module_platform_driver(lantiq_rcu_reset_driver); - -MODULE_AUTHOR("Martin Blumenstingl "); -MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver"); 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[95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:24 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 9/9] mips: dts: lantiq: Update the RCU node to match the intel,rcu-gw binding Date: Tue, 28 Jun 2022 14:44:41 +0200 Message-Id: <20220628124441.2385023-10-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use the updated compatible string and also add the USB2 PHY child node. Signed-off-by: Martin Blumenstingl --- arch/mips/boot/dts/lantiq/danube.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi index 510be63c8bdf..8ac806662083 100644 --- a/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/arch/mips/boot/dts/lantiq/danube.dtsi @@ -57,8 +57,26 @@ cgu0: cgu@103000 { }; rcu0: rcu@203000 { - compatible = "lantiq,rcu-xway"; + compatible = "lantiq,danube-rcu", "simple-mfd", "syscon"; reg = <0x203000 0x1000>; + ranges = <0x0 0x203000 0x100>; + big-endian; + + #address-cells = <1>; + #size-cells = <1>; + + #reset-cells = <3>; + intel,global-reset = <0x10 30 29>; + + usb_phy: usb2-phy@18 { + compatible = "lantiq,danube-usb2-phy"; + reg = <0x18 4>; + status = "disabled"; + + resets = <&rcu0 0x10 4 4>; + reset-names = "ctrl"; + #phy-cells = <0>; + }; }; };