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Wed, 29 Jun 2022 19:25:27 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20220629102527epcas2p21c9ba830afdf5ec5a8afde4707206186~9EHPVm0tG2062420624epcas2p2j; Wed, 29 Jun 2022 10:25:27 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220629102527epsmtrp231f9d6a2252219ed0d75911379fa898e~9EHPU0PqD0374703747epsmtrp2h; Wed, 29 Jun 2022 10:25:27 +0000 (GMT) X-AuditID: b6c32a45-471ff700000025c2-76-62bc28973237 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 1B.D6.08905.7982CB26; Wed, 29 Jun 2022 19:25:27 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220629102527epsmtip1843173c8e07f9f04c035f0e5dfd5e270~9EHPKHDRS2685226852epsmtip1Z; Wed, 29 Jun 2022 10:25:27 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v3 1/4] spi: s3c64xx: support loopback mode Date: Wed, 29 Jun 2022 19:23:01 +0900 Message-Id: <20220629102304.65712-2-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629102304.65712-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCJsWRmVeSWpSXmKPExsWy7bCmqe50jT1JBvPnW1s8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTM wFDX0NLCXEkhLzE31VbJxSdA1y0zB+g6JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpB Sk6BeYFecWJucWleul5eaomVoYGBkSlQYUJ2xss1mxgLzghVXJwwm7mBcQN/FyMHh4SAicTr 1zxdjFwcQgI7GCXeH3zABOF8YpQ4/u4lO4TzjVGi88xUti5GTrCOk7OXMYLYQgJ7GSWuLwiG KPrIKHFw3nl2kASbgK7EluevGEESIgI3GSWmn+0Dm8sscINRYu+M9WDtwgLWEt/X7WICsVkE VCWu9p5gAbF5BewkZrcuYIZYJy+xYX4vmM0pYC/x9spqVogaQYmTM5+A1TMD1TRvnc0MskBC oJND4urEySwQzS4SJzZcZIewhSVeHd8CZUtJfH63F+qfYomlsz4xQTQ3MEpc3vYLKmEsMetZ OyMomJgFNCXW79KHhJiyxJFbUHv5JDoO/2WHCPNKdLQJQTSqSxzYPh3qAlmJ7jmfWSFsD4mm jb9ZIaE1iVHiUdtJ9gmMCrOQvDMLyTuzEBYvYGRexSiWWlCcm55abFRgCI/i5PzcTYzg5Krl uoNx8tsPeocYmTgYDzFKcDArifAuPLMzSYg3JbGyKrUoP76oNCe1+BCjKTCwJzJLiSbnA9N7 Xkm8oYmlgYmZmaG5kamBuZI4r1fKhkQhgfTEktTs1NSC1CKYPiYOTqkGJv5rntGZj9+s3CHs l7a/aYrgbZN/DB0xdtM2umTd/KU5aaHAVyPza7secG15a3D1kP6KB1e7cgt2dsf9/ijRM+1e Qs+7HjcJr64Fq5r61j3j27mGSS3sZZ5cMH/e3nxW322rjtxKT5MrWzy198UElVNejz+FHdmr 2v2k/rGn+F+ZtK3yN/YbJkxR3lD++Mny9pJP7MX2ab+unjl/TH+CFcMN5Wu7m2VzLdUc517m WrPi/N73K98qvb+4ZtW2x+sWsAvWbu6v0ZUMKbmc1dHNIGWYr9RYua9jWn3l1rf+hySWr07b 0H5N1Oe9/Nmaqyza6fc0rmUbvU96dOejXEP7xVfN7+QVYj+ZPL1bldpQUKvEUpyRaKjFXFSc CACOF7jaNwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSnO50jT1JBv9fK1o8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtissmJTUnsyy1SN8ugSvj5ZpNjAVnhCouTpjN 3MC4gb+LkZNDQsBE4uTsZYxdjFwcQgK7GSUerHrODpGQlXj2bgeULSxxv+UIK0TRe0aJk5u/ gCXYBHQltjx/BdYtInCbUeJv4zY2EIdZ4A6jxKPle5hAqoQFrCW+r9sFZrMIqEpc7T3BAmLz CthJzG5dwAyxQl5iw/xeMJtTwF7i7ZXVrCC2EFDNkus7oeoFJU7OfAJmMwPVN2+dzTyBUWAW ktQsJKkFjEyrGCVTC4pz03OLDQsM81LL9YoTc4tL89L1kvNzNzGCI0FLcwfj9lUf9A4xMnEw HmKU4GBWEuFdeGZnkhBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeC10n44UE0hNLUrNTUwtSi2Cy TBycUg1M54IEpVsW/mVx5z4uX20QV6VTWbzXaesbsdRzs+XDGr3jj3/4xmbXdtnitcj30H0G mi817JOXdHpJRyRFnhdUj1gz6cmsHRoqWwy/OmtetMss2ngg4EH8rzl39Rp3z39e3TF5utpT zpKAt48OPNtb9jO43LK/J2dRl+mrmzfWtM+8NOu8zPPlWr2SyXNcMv7sSNtsZZ/Pbdhstuyb HuPijorosOjjG/4bCZ1OMSrhedqUu/jRavGG1b5VHheWvrXr57wsznI17lLrX+k9smlbsltW h2l/6M98bztXJnChbf7pf9uPvGgM2vZ4hrNzwDTDtXVHeOZ8Els2/XfyXNMS1+vrDroINX4p nbWhh7NWiaU4I9FQi7moOBEA25ieC/MCAAA= X-CMS-MailID: 20220629102527epcas2p21c9ba830afdf5ec5a8afde4707206186 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220629102527epcas2p21c9ba830afdf5ec5a8afde4707206186 References: <20220629102304.65712-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_032536_935211_36971628 X-CRM114-Status: GOOD ( 19.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Modern exynos SoCs can support self loopback mode via setting BIT(3) of MODE_CFG register. Previous SoCs don't have the bit so we need to add has_loopback field in the s3c64xx_spi_port_config. Exynos Auto v9 SoC has the bit and it will define the field to "true". When it is set, SPI_LOOP mode will be marked. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Signed-off-by: Chanho Park --- drivers/spi/spi-s3c64xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 302c1d4a28b1..0c917cf891ca 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -59,6 +59,7 @@ #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) #define S3C64XX_SPI_MODE_4BURST (1<<0) @@ -135,6 +136,7 @@ struct s3c64xx_spi_dma_data { * @clk_from_cmu: True, if the controller does not include a clock mux and * prescaler unit. * @clk_ioclk: True if clock is present on this device + * @has_loopback: True if loopback mode can be supported * * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but * differ in some aspects such as the size of the fifo and spi bus clock @@ -149,6 +151,7 @@ struct s3c64xx_spi_port_config { bool high_speed; bool clk_from_cmu; bool clk_ioclk; + bool has_loopback; }; /** @@ -659,6 +662,9 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) break; } + if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) + val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; + writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { @@ -1148,6 +1154,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) SPI_BPW_MASK(8); /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + if (sdd->port_conf->has_loopback) + master->mode_bits |= SPI_LOOP; master->auto_runtime_pm = true; if (!is_polling(sdd)) master->can_dma = s3c64xx_spi_can_dma; From patchwork Wed Jun 29 10:23:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 12899713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6BE9C43334 for ; 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Wed, 29 Jun 2022 19:25:27 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220629102527epsmtip1fff8c16f6a2b2db49c0b525a828e845f~9EHPON5Hb2596825968epsmtip1j; Wed, 29 Jun 2022 10:25:27 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider Date: Wed, 29 Jun 2022 19:23:02 +0900 Message-Id: <20220629102304.65712-3-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629102304.65712-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMJsWRmVeSWpSXmKPExsWy7bCmue4MjT1JBg/WaVs8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTM wFDX0NLCXEkhLzE31VbJxSdA1y0zB+g6JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpB Sk6BeYFecWJucWleul5eaomVoYGBkSlQYUJ2RuOnw6wFf7Qr1l3rZGxg7FfuYuTkkBAwkZi+ /gpTFyMXh5DADkaJTT2vmCGcT4wS/bf/QGW+MUo8OX2SDabl15pFbBCJvYwSHY2rWUESQgIf gfo/aIPYbAK6Eluev2IEKRIRuMkoMf1sH9goZoEbjBJ7Z6xnBKkSFgiTePDyGpjNIqAqMf/d YvYuRg4OXgE7ibunIiG2yUtsmN/LDGJzCthLvL0CsYxXQFDi5MwnLCA2M1BN89bZYHdLCEzk kOicvJsFZI6EgIvE7u5MiDnCEq+Ob2GHsKUkPr/bC/VNscTSWZ+YIHobGCUub/sFlTCWmPWs nRFkDrOApsT6XfoQI5UljtyCWssn0XH4LztEmFeio00IolFd4sD26SwQtqxE95zPrBC2h8S8 e7OhATqJUeLEuudsExgVZiH5ZhaSb2YhLF7AyLyKUSy1oDg3PbXYqMAQHsPJ+bmbGMGpVct1 B+Pktx/0DjEycTAeYpTgYFYS4V14ZmeSEG9KYmVValF+fFFpTmrxIUZTYFBPZJYSTc4HJve8 knhDE0sDEzMzQ3MjUwNzJXFer5QNiUIC6YklqdmpqQWpRTB9TBycUg1M+U5nOFa2LrAJX1A5 8XQue0Iah86UPc8Lv3qx7PXbeuZdb+2MHvF+0VfPPrt9dY7yrnNO5r8cNWH1970ORyubtT54 3T1SWiiku+rnwjnqWRk/9tV09SXPuXhS81dZuLzX2yMPXipt+RzXaJhzMNNloX34j2Wits+N Cs0unXuSO+uFRNJZJ7F50oZLJ101OBXjmxp4oiHXTyF6k5b4nCrhqSFVSrU28jm/V4n8evVy 9+czf7N2uEv1rA3e47ZTc+m+P5KxfEILD9zOURH8VTvX7fHsxhm1G2ccbFwwR+Ou7h7LglLb jgVXK5h261wMYJvzRJg/7Rivwyy25UYBNdo5qbskNrzf7vPMqFXC6FebEktxRqKhFnNRcSIA KdXyaDYEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWy7bCSnO50jT1JBnd/qFo8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtissmJTUnsyy1SN8ugSuj8dNh1oI/2hXrrnUy NjD2K3cxcnJICJhI/FqziK2LkYtDSGA3o8TXt49ZIRKyEs/e7WCHsIUl7rccAYsLCbxnlOh6 XA5iswnoSmx5/ooRpFlE4DajxN/GbWCTmAXuMEo8Wr6HCaRKWCBE4vG8FYwgNouAqsT8d4uB pnJw8ArYSdw9FQmxQF5iw/xeZhCbU8Be4u2V1VDL7CSWXN/JAmLzCghKnJz5BMxmBqpv3jqb eQKjwCwkqVlIUgsYmVYxSqYWFOem5xYbFhjmpZbrFSfmFpfmpesl5+duYgRHgZbmDsbtqz7o HWJk4mA8xCjBwawkwrvwzM4kId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rwXuk7GCwmkJ5akZqem FqQWwWSZODilGpjOrJs7S7e7alafpIz3+a8d9TtMLm/c3pj8fG+JnlfT5DQnZsHJ9+z/cliq LUh4Uv56acmpBr3r9VOdjPNn3n7b3ba54tUf0W4ed0fz/esmf6jffIGLo0k2dbv7voMXbpZP y6473+s235DpaPWbGfXXpjWsuf/RPOdd0Aynkx7+DlLOO15Flv7Nnz1f0L5gzj0GzfV2OY9W tsdurNx5T9Ul0HNvjLhlsGe870WhsKmCHbyPjsvw8O6Ij2/52l7pFR7+bPav3X+rLpSItM9/ rnNL7UYnv8Nqvagsj6ce37bdlQnZvUqIRbU6wSN35TyXyOZ17tu0T62Q+HLKYx/T3UCuddv+ fNm8yGrqTn6xIxOVWIozEg21mIuKEwEc/WB78QIAAA== X-CMS-MailID: 20220629102527epcas2p42e99f44d529d215623bd0e12a082d1dd X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220629102527epcas2p42e99f44d529d215623bd0e12a082d1dd References: <20220629102304.65712-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_032533_427648_2B75F613 X-CRM114-Status: GOOD ( 23.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Modern exynos SoCs such as Exynos Auto v9 have different internal clock divider, for example "4". To support this internal value, this adds clk_div of the s3c64xx_spi_port_config and assign "2" as the default value to existing s3c64xx_spi_port_config. Signed-off-by: Chanho Park Reviewed-by: Andi Shyti Reviewed-by: Krzysztof Kozlowski --- drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 0c917cf891ca..ff565e57736b 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. + * @clk_div: Internal clock divider * @quirks: Bitmask of known quirks * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. * @clk_from_cmu: True, if the controller does not include a clock mux and @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config { int rx_lvl_offset; int tx_st_done; int quirks; + int clk_div; bool high_speed; bool clk_from_cmu; bool clk_ioclk; @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) void __iomem *regs = sdd->regs; int ret; u32 val; + int div = sdd->port_conf->clk_div; /* Disable Clock */ if (!sdd->port_conf->clk_from_cmu) { @@ -668,16 +671,15 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* The src_clk clock is divided internally by 2 */ - ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); + ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); if (ret) return ret; - sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); val &= ~S3C64XX_SPI_PSR_MASK; - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) & S3C64XX_SPI_PSR_MASK); writel(val, regs + S3C64XX_SPI_CLK_CFG); @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_csinfo *cs = spi->controller_data; struct s3c64xx_spi_driver_data *sdd; int err; + int div; sdd = spi_master_get_devdata(spi->master); if (spi->dev.of_node) { @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) pm_runtime_get_sync(&sdd->pdev->dev); + div = sdd->port_conf->clk_div; + /* Check if we can provide the requested rate */ if (!sdd->port_conf->clk_from_cmu) { u32 psr, speed; /* Max possible */ - speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); + speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); if (spi->max_speed_hz > speed) spi->max_speed_hz = speed; - psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; + psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; psr &= S3C64XX_SPI_PSR_MASK; if (psr == S3C64XX_SPI_PSR_MASK) psr--; - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz < speed) { if (psr+1 < S3C64XX_SPI_PSR_MASK) { psr++; @@ -914,7 +919,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } } - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz >= speed) { spi->max_speed_hz = speed; } else { @@ -1396,6 +1401,7 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { .fifo_lvl_mask = { 0x7f }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, .high_speed = true, }; @@ -1403,12 +1409,14 @@ static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7F }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, }; @@ -1416,6 +1424,7 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1425,6 +1434,7 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1434,6 +1444,7 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = true, @@ -1444,6 +1455,7 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = false, From patchwork Wed Jun 29 10:23:03 2022 Content-Type: text/plain; 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Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Signed-off-by: Chanho Park --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index ef59ff62e88d..e0a465d70b0a 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -22,6 +22,7 @@ properties: - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos4210-spi - samsung,exynos5433-spi + - samsung,exynosautov9-spi - tesla,fsd-spi - const: samsung,exynos7-spi deprecated: true @@ -86,7 +87,9 @@ allOf: properties: compatible: contains: - const: samsung,exynos5433-spi + enum: + - samsung,exynos5433-spi + - samsung,exynosautov9-spi then: properties: clocks: From patchwork Wed Jun 29 10:23:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 12899714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C58E9C433EF for ; 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Wed, 29 Jun 2022 19:25:27 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220629102527epsmtip1319246b7935d580b80ddc633f2a4d368~9EHPY1KrL2691826918epsmtip1S; Wed, 29 Jun 2022 10:25:27 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v3 4/4] spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC Date: Wed, 29 Jun 2022 19:23:04 +0900 Message-Id: <20220629102304.65712-5-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629102304.65712-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMJsWRmVeSWpSXmKPExsWy7bCmme4MjT1JBuemy1k8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTM wFDX0NLCXEkhLzE31VbJxSdA1y0zB+g6JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpB Sk6BeYFecWJucWleul5eaomVoYGBkSlQYUJ2xrYbb5kLrvFXXF/7naWB8R9PFyMnh4SAicTM k/OZQGwhgR2MErMv53cxcgHZnxglls+7xAzhfGOU+DdpGjtMR/OuqewQHXsZJT58yYIo+sgo 8XHqd7BRbAK6Eluev2IESYgI3GSUmH62jwnEYRa4wSixd8Z6RpAqYYFIiRk/TzGD2CwCqkBF 98HivAJ2Env2XGaCWCcvsWF+L1gNp4C9xNsrq1khagQlTs58wgJiMwPVNG+dDXarhMBEDomf H7cDORxAjovE4RZJiDnCEq+Ob4F6QUriZX8blF0ssXTWJyaI3gZGicvbfrFBJIwlZj1rZwSZ wyygKbF+lz7ESGWJI7eg1vJJdBz+yw4R5pXoaBOCaFSXOLB9OguELSvRPeczK4TtIdGz7SE0 RCcxSnyb/5R9AqPCLCTfzELyzSyExQsYmVcxiqUWFOempxYbFRjDYzg5P3cTIzi1arnvYJzx 9oPeIUYmDsZDjBIczEoivAvP7EwS4k1JrKxKLcqPLyrNSS0+xGgKDOuJzFKiyfnA5J5XEm9o YmlgYmZmaG5kamCuJM7rlbIhUUggPbEkNTs1tSC1CKaPiYNTqoGpXL08+XbEyruZc04xXvyS ce/TL9WIad5rrjeqZTctvnzz1sFrh2T7avIauzweRsps0Ton9dTs7P85FtePB9Q8Xe0+f9/x HUpqt4+be2uZ524qOBkR11G5WSi5d8Ul4RsR07xuOkv/E7paZJmYsXX9DL5tW4zn8GUVdezq C7v47PDxNUUZc0PDS56lOnKuXNZys/mD+M77H+17c58Erf9zX/3E3/gzX84X5K45vOLinLVy qzblHT3VzM5ywHPLm+x4AZF3DP7bHggLvGCNOj5dfuIH2TCv4k2/HjYvmxgdytCxRObBaj3z qysE956fdM59hUjp5Y1vyw9nnv38oS9szddzlQrng+Vq3YplPwWaHFNiKc5INNRiLipOBADV B5q4NgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSnO50jT1JBvseG1g8mLeNzWLxj+dM FlMfPmGzuLxf22L+kXOsFn0vHjJb7H29ld1i0+NrrBYzzu9jsmj8eJPdonXvEXYHbo/rSz4x e2xa1cnmcefaHjaPzUvqPfq2rGL0+LxJLoAtissmJTUnsyy1SN8ugStj2423zAXX+Cuur/3O 0sD4j6eLkZNDQsBEonnXVPYuRi4OIYHdjBIdnY9YIBKyEs/e7WCHsIUl7rccYYUoes8osWzj CSaQBJuArsSW568YQRIiArcZJf42bmMDcZgF7jBKPFq+B6xKWCBc4tisc2BjWQRUJaafvc8I YvMK2Ens2XOZCWKFvMSG+b3MIDangL3E2yurWUFsIaCaJdd3skDUC0qcnPkEzGYGqm/eOpt5 AqPALCSpWUhSCxiZVjFKphYU56bnFhsWGOallusVJ+YWl+al6yXn525iBEeCluYOxu2rPugd YmTiYDzEKMHBrCTCu/DMziQh3pTEyqrUovz4otKc1OJDjNIcLErivBe6TsYLCaQnlqRmp6YW pBbBZJk4OKUamOYtV6++HH/aLSzu4Nbnrb/qwoSOpB9U+TrZorX4hJTkgsptzWvEqv3jP3P7 yDIJ1vhklS49Ly888eijx3/902dE8712f//wa/nEi+VZEr3LfB8p/1Tv6dCTMXm8YfObLXrb N6+5EFK0fFGO7Hkp8wyem2sETh5eOl9OdZKz+hIp1yT2Wfu/n9uewup0e3PwyrUHg7/qPfix aU/9olv6WllNNz0zN/FPVJvh1lIrEnA779PH+4FzPl9KzGnbvFVfvXEG9/26oONCLf8f7E84 au4joKXpMv1hoOhPmXjn0s0WX7lEJmzdnLT8q5HZjZpr6w6khVw7epHfY0/StIUmUyTqrtnq Jj0yiVuTX9t8oFKJpTgj0VCLuag4EQA/gJk28wIAAA== X-CMS-MailID: 20220629102527epcas2p19e967e3647084cbfad1bff0b9390b4ad X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220629102527epcas2p19e967e3647084cbfad1bff0b9390b4ad References: <20220629102304.65712-1-chanho61.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_032536_934048_752938CD X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add exynosautov9 spi port configuration. It supports up to 12 spis so MAX_SPI_PORTS should be increased from 6 to 12. It has DIV_4 as the default internal clock divider and an internal loopback mode to run a loopback test. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Signed-off-by: Chanho Park --- drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index ff565e57736b..7f346866614a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -18,7 +18,7 @@ #include -#define MAX_SPI_PORTS 6 +#define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -1451,6 +1451,19 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .clk_ioclk = true, + .has_loopback = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset = 15, @@ -1492,6 +1505,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos5433-spi", .data = (void *)&exynos5433_spi_port_config, }, + { .compatible = "samsung,exynosautov9-spi", + .data = (void *)&exynosautov9_spi_port_config, + }, { .compatible = "tesla,fsd-spi", .data = (void *)&fsd_spi_port_config, },